library IEEE;
use  IEEE.STD_LOGIC_1164.all;
use  IEEE.STD_LOGIC_ARITH.all;
use  IEEE.STD_LOGIC_UNSIGNED.all;

ENTITY s7segm IS
	PORT(
		DIN	: IN	STD_LOGIC_VECTOR(3 downto 0);
		a	: OUT	STD_LOGIC;
		b	: OUT	STD_LOGIC;
		c	: OUT	STD_LOGIC;
		d	: OUT	STD_LOGIC;
		e	: OUT	STD_LOGIC;
		f	: OUT	STD_LOGIC;
		g	: OUT	STD_LOGIC
		);
END s7segm;

architecture angel of s7segm is
signal s7out	: STD_LOGIC_VECTOR(6 downto 0);
signal dintg	: Integer range 0 to 15;
begin
	dintg <= CONV_INTEGER(din);
	with DINtg select
--           abcdefg
	s7out <= "1111110" when 0,
			 "0110000" when 1,
			 "1101101" when 2,
			 "1111001" when 3,
			 "0110011" when 4,
			 "1011011" when 5,
			 "1011111" when 6,
			 "1110000" when 7,
			 "1111111" when 8,
			 "1110011" when 9,
			 "1110111" when 10,
			 "0011111" when 11,
			 "1001110" when 12,
			 "0111101" when 13,
			 "1001111" when 14,
			 "1000111" when others;

	a <= not s7out(6);
	b <= not s7out(5);
	c <= not s7out(4);
	d <= not s7out(3);
	e <= not s7out(2);
	f <= not s7out(1);
	g <= not s7out(0);

end;