Timing Analyzer report for top_trap_pci Thu Sep 28 16:32:59 2006 Version 5.0 Build 148 04/26/2005 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. Timing Analyzer Summary 3. Timing Analyzer Settings 4. Clock Settings Summary 5. Clock Setup: 'DES_CLK' 6. Clock Setup: 'pci_clk' 7. Clock Hold: 'DES_CLK' 8. Clock Hold: 'pci_clk' 9. tsu 10. tco 11. th 12. Timing Analyzer Messages ---------------- ; Legal Notice ; ---------------- Copyright (C) 1991-2005 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Timing Analyzer Summary ; +------------------------------+-----------+----------------------------------+----------------------------------+-----------------------------------------------------------------+---------------------------------------------------+------------+----------+--------------+ ; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ; +------------------------------+-----------+----------------------------------+----------------------------------+-----------------------------------------------------------------+---------------------------------------------------+------------+----------+--------------+ ; Worst-case tsu ; 3.800 ns ; 1.500 ns ; -2.300 ns ; DES_DATA[0] ; dpm_ni2f_reg_des_data_r_0 ; ; DES_CLK ; 0 ; ; Worst-case tco ; N/A ; None ; 19.400 ns ; sg_reg_mx_q ; R7S[4] ; pci_clk ; ; 0 ; ; Worst-case th ; -5.400 ns ; 0.100 ns ; 5.500 ns ; DES_ER ; dpm_ni2f_reg_des_er_r ; ; DES_CLK ; 18 ; ; Clock Setup: 'DES_CLK' ; 0.000 ns ; 125.00 MHz ( period = 8.000 ns ) ; 125.00 MHz ( period = 8.000 ns ) ; dpm_ni2f_reg_des_valid_data ; dpm_ni2f_fifo_h_reg_nwords_9 ; DES_CLK ; DES_CLK ; 0 ; ; Clock Setup: 'pci_clk' ; 10.111 ns ; 34.00 MHz ( period = 29.411 ns ) ; 51.81 MHz ( period = 19.300 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[0] ; pci_clk ; pci_clk ; 0 ; ; Clock Hold: 'DES_CLK' ; 0.600 ns ; 125.00 MHz ( period = 8.000 ns ) ; N/A ; dpm_ni2f_fifo_h_reg_fifo_empty ; dpm_ni2f_fifo_h_reg_fifo_empty ; DES_CLK ; DES_CLK ; 0 ; ; Clock Hold: 'pci_clk' ; 0.600 ns ; 34.00 MHz ( period = 29.411 ns ) ; N/A ; sg_reg_mx_q ; sg_reg_mx_q ; pci_clk ; pci_clk ; 0 ; ; Total number of failed paths ; ; ; ; ; ; ; ; 18 ; +------------------------------+-----------+----------------------------------+----------------------------------+-----------------------------------------------------------------+---------------------------------------------------+------------+----------+--------------+ +----------------------------------------------------------------------------------------------------------------+ ; Timing Analyzer Settings ; +-------------------------------------------------------+--------------------+------+--------------+-------------+ ; Option ; Setting ; From ; To ; Entity Name ; +-------------------------------------------------------+--------------------+------+--------------+-------------+ ; Device Name ; EP1K100QC208-1 ; ; ; ; ; Timing Models ; Final ; ; ; ; ; Number of source nodes to report per destination node ; 10 ; ; ; ; ; Number of destination nodes to report ; 10 ; ; ; ; ; Number of paths to report ; 200 ; ; ; ; ; Report Minimum Timing Checks ; Off ; ; ; ; ; Use Fast Timing Models ; Off ; ; ; ; ; Report IO Paths Separately ; Off ; ; ; ; ; Default hold multicycle ; Same as Multicycle ; ; ; ; ; Cut paths between unrelated clock domains ; On ; ; ; ; ; Cut off read during write signal paths ; On ; ; ; ; ; Cut off feedback from I/O pins ; On ; ; ; ; ; Report Combined Fast/Slow Timing ; Off ; ; ; ; ; Ignore Clock Settings ; Off ; ; ; ; ; Analyze latches as synchronous elements ; Off ; ; ; ; ; Enable Recovery/Removal analysis ; Off ; ; ; ; ; Enable Clock Latency ; Off ; ; ; ; ; th Requirement ; 0.1ns ; ; DES_DATA[0] ; ; ; th Requirement ; 0.1ns ; ; DES_DATA[10] ; ; ; th Requirement ; 0.1ns ; ; DES_DATA[11] ; ; ; th Requirement ; 0.1ns ; ; DES_DATA[12] ; ; ; th Requirement ; 0.1ns ; ; DES_DATA[13] ; ; ; th Requirement ; 0.1ns ; ; DES_DATA[14] ; ; ; th Requirement ; 0.1ns ; ; DES_DATA[15] ; ; ; th Requirement ; 0.1ns ; ; DES_DATA[1] ; ; ; th Requirement ; 0.1ns ; ; DES_DATA[2] ; ; ; th Requirement ; 0.1ns ; ; DES_DATA[3] ; ; ; th Requirement ; 0.1ns ; ; DES_DATA[4] ; ; ; th Requirement ; 0.1ns ; ; DES_DATA[5] ; ; ; th Requirement ; 0.1ns ; ; DES_DATA[6] ; ; ; th Requirement ; 0.1ns ; ; DES_DATA[7] ; ; ; th Requirement ; 0.1ns ; ; DES_DATA[8] ; ; ; th Requirement ; 0.1ns ; ; DES_DATA[9] ; ; ; th Requirement ; 0.1ns ; ; DES_EN ; ; ; th Requirement ; 0.1ns ; ; DES_ER ; ; ; tsu Requirement ; 1.5ns ; ; DES_DATA[0] ; ; ; tsu Requirement ; 1.5ns ; ; DES_DATA[10] ; ; ; tsu Requirement ; 1.5ns ; ; DES_DATA[11] ; ; ; tsu Requirement ; 1.5ns ; ; DES_DATA[12] ; ; ; tsu Requirement ; 1.5ns ; ; DES_DATA[13] ; ; ; tsu Requirement ; 1.5ns ; ; DES_DATA[14] ; ; ; tsu Requirement ; 1.5ns ; ; DES_DATA[15] ; ; ; tsu Requirement ; 1.5ns ; ; DES_DATA[1] ; ; ; tsu Requirement ; 1.5ns ; ; DES_DATA[2] ; ; ; tsu Requirement ; 1.5ns ; ; DES_DATA[3] ; ; ; tsu Requirement ; 1.5ns ; ; DES_DATA[4] ; ; ; tsu Requirement ; 1.5ns ; ; DES_DATA[5] ; ; ; tsu Requirement ; 1.5ns ; ; DES_DATA[6] ; ; ; tsu Requirement ; 1.5ns ; ; DES_DATA[7] ; ; ; tsu Requirement ; 1.5ns ; ; DES_DATA[8] ; ; ; tsu Requirement ; 1.5ns ; ; DES_DATA[9] ; ; ; tsu Requirement ; 1.5ns ; ; DES_EN ; ; ; tsu Requirement ; 1.5ns ; ; DES_ER ; ; ; Clock Settings ; clk strobe ; ; DES_CLK ; ; ; Clock Settings ; clk pci ; ; pci_clk ; ; +-------------------------------------------------------+--------------------+------+--------------+-------------+ +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Clock Settings Summary ; +-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+ ; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ; +-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+ ; DES_CLK ; clk_strobe ; User Pin ; 125.0 MHz ; 0.000 ns ; 0.000 ns ; NONE ; N/A ; N/A ; N/A ; ; ; pci_clk ; clk_pci ; User Pin ; 34.0 MHz ; 0.000 ns ; 0.000 ns ; NONE ; N/A ; N/A ; N/A ; ; +-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Clock Setup: 'DES_CLK' ; +-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------------------------+---------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+ ; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ; +-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------------------------+---------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+ ; 0.000 ns ; 125.00 MHz ( period = 8.000 ns ) ; dpm_ni2f_reg_des_valid_data ; dpm_ni2f_fifo_h_reg_nwords_9 ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 7.000 ns ; ; 0.100 ns ; 126.58 MHz ( period = 7.900 ns ) ; dpm_ni2f_reg_des_valid_data ; dpm_ni2f_fifo_h_reg_nwords_0 ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.900 ns ; ; 0.300 ns ; 129.87 MHz ( period = 7.700 ns ) ; dpm_ni2f_reg_des_valid_data ; dpm_ni2f_fifo_h_reg_nwords_8 ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.700 ns ; ; 0.400 ns ; 131.58 MHz ( period = 7.600 ns ) ; dpm_ni2f_reg_des_valid_data ; dpm_ni2f_fifo_h_reg_nwords_7 ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.600 ns ; ; 0.400 ns ; 131.58 MHz ( period = 7.600 ns ) ; dpm_ni2f_reg_des_valid_data ; dpm_ni2f_fifo_h_reg_nwords_6 ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.600 ns ; ; 0.500 ns ; 133.33 MHz ( period = 7.500 ns ) ; dpm_ni2f_reg_sm_1 ; dpm_ni2f_reg_addr_13 ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.500 ns ; ; 0.500 ns ; 133.33 MHz ( period = 7.500 ns ) ; dpm_ni2f_reg_des_valid_data ; dpm_ni2f_fifo_h_reg_nwords_2 ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.500 ns ; ; 0.600 ns ; 135.14 MHz ( period = 7.400 ns ) ; dpm_ni2f_reg_rdreq_fifo ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[0] ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.400 ns ; ; 0.600 ns ; 135.14 MHz ( period = 7.400 ns ) ; dpm_ni2f_reg_rdreq_fifo ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[1] ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.400 ns ; ; 0.600 ns ; 135.14 MHz ( period = 7.400 ns ) ; dpm_ni2f_reg_rdreq_fifo ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[2] ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.400 ns ; ; 0.600 ns ; 135.14 MHz ( period = 7.400 ns ) ; dpm_ni2f_reg_rdreq_fifo ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[3] ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.400 ns ; ; 0.600 ns ; 135.14 MHz ( period = 7.400 ns ) ; dpm_ni2f_reg_rdreq_fifo ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[4] ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.400 ns ; ; 0.600 ns ; 135.14 MHz ( period = 7.400 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[1] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[2] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 6.000 ns ; ; 0.600 ns ; 135.14 MHz ( period = 7.400 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[1] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[4] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 6.000 ns ; ; 0.600 ns ; 135.14 MHz ( period = 7.400 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[1] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[7] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 6.000 ns ; ; 0.600 ns ; 135.14 MHz ( period = 7.400 ns ) ; dpm_ni2f_reg_des_valid_data ; dpm_ni2f_fifo_h_reg_nwords_1 ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.400 ns ; ; 0.600 ns ; 135.14 MHz ( period = 7.400 ns ) ; dpm_ni2f_reg_des_valid_data ; dpm_ni2f_fifo_h_reg_nwords_10 ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.400 ns ; ; 0.600 ns ; 135.14 MHz ( period = 7.400 ns ) ; dpm_ni2f_reg_des_valid_data ; dpm_ni2f_fifo_h_reg_nwords_5 ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.400 ns ; ; 0.600 ns ; 135.14 MHz ( period = 7.400 ns ) ; dpm_ni2f_reg_des_valid_data ; dpm_ni2f_fifo_h_reg_nwords_4 ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.400 ns ; ; 0.600 ns ; 135.14 MHz ( period = 7.400 ns ) ; dpm_ni2f_reg_des_valid_data ; dpm_ni2f_fifo_h_reg_nwords_3 ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.400 ns ; ; 0.600 ns ; 135.14 MHz ( period = 7.400 ns ) ; dpm_ni2f_fifo_l_reg_nwords_0 ; dpm_ni2f_fifo_l_reg_nwords_7 ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.400 ns ; ; 0.700 ns ; 136.99 MHz ( period = 7.300 ns ) ; dpm_ni2f_reg_sm_1 ; dpm_ni2f_reg_addr_2 ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.300 ns ; ; 0.700 ns ; 136.99 MHz ( period = 7.300 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[10] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[6] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.900 ns ; ; 0.700 ns ; 136.99 MHz ( period = 7.300 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[9] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[6] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.900 ns ; ; 0.700 ns ; 136.99 MHz ( period = 7.300 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[8] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[6] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.900 ns ; ; 0.700 ns ; 136.99 MHz ( period = 7.300 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[7] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[6] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.900 ns ; ; 0.700 ns ; 136.99 MHz ( period = 7.300 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[6] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[6] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.900 ns ; ; 0.700 ns ; 136.99 MHz ( period = 7.300 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[5] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[6] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.900 ns ; ; 0.700 ns ; 136.99 MHz ( period = 7.300 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[4] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[6] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.900 ns ; ; 0.700 ns ; 136.99 MHz ( period = 7.300 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[3] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[6] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.900 ns ; ; 0.700 ns ; 136.99 MHz ( period = 7.300 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[2] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[6] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.900 ns ; ; 0.700 ns ; 136.99 MHz ( period = 7.300 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[1] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[6] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.900 ns ; ; 0.700 ns ; 136.99 MHz ( period = 7.300 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[0] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[6] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.900 ns ; ; 0.700 ns ; 136.99 MHz ( period = 7.300 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[1] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[0] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.900 ns ; ; 0.700 ns ; 136.99 MHz ( period = 7.300 ns ) ; dpm_ni2f_reg_rdreq_fifo ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[5] ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.300 ns ; ; 0.700 ns ; 136.99 MHz ( period = 7.300 ns ) ; dpm_ni2f_reg_rdreq_fifo ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[6] ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.300 ns ; ; 0.700 ns ; 136.99 MHz ( period = 7.300 ns ) ; dpm_ni2f_reg_rdreq_fifo ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[7] ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.300 ns ; ; 0.700 ns ; 136.99 MHz ( period = 7.300 ns ) ; dpm_ni2f_reg_rdreq_fifo ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[8] ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.300 ns ; ; 0.700 ns ; 136.99 MHz ( period = 7.300 ns ) ; dpm_ni2f_reg_rdreq_fifo ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[9] ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.300 ns ; ; 0.700 ns ; 136.99 MHz ( period = 7.300 ns ) ; dpm_ni2f_reg_rdreq_fifo ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[10] ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.300 ns ; ; 0.700 ns ; 136.99 MHz ( period = 7.300 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[1] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[1] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.900 ns ; ; 0.700 ns ; 136.99 MHz ( period = 7.300 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[10] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[2] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.900 ns ; ; 0.700 ns ; 136.99 MHz ( period = 7.300 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[9] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[2] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.900 ns ; ; 0.700 ns ; 136.99 MHz ( period = 7.300 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[8] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[2] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.900 ns ; ; 0.700 ns ; 136.99 MHz ( period = 7.300 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[7] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[2] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.900 ns ; ; 0.700 ns ; 136.99 MHz ( period = 7.300 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[6] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[2] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.900 ns ; ; 0.700 ns ; 136.99 MHz ( period = 7.300 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[5] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[2] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.900 ns ; ; 0.700 ns ; 136.99 MHz ( period = 7.300 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[4] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[2] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.900 ns ; ; 0.700 ns ; 136.99 MHz ( period = 7.300 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[3] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[2] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.900 ns ; ; 0.700 ns ; 136.99 MHz ( period = 7.300 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[2] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[2] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.900 ns ; ; 0.700 ns ; 136.99 MHz ( period = 7.300 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[0] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[2] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.900 ns ; ; 0.700 ns ; 136.99 MHz ( period = 7.300 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[1] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[3] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.900 ns ; ; 0.700 ns ; 136.99 MHz ( period = 7.300 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[10] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[4] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.900 ns ; ; 0.700 ns ; 136.99 MHz ( period = 7.300 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[9] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[4] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.900 ns ; ; 0.700 ns ; 136.99 MHz ( period = 7.300 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[8] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[4] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.900 ns ; ; 0.700 ns ; 136.99 MHz ( period = 7.300 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[7] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[4] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.900 ns ; ; 0.700 ns ; 136.99 MHz ( period = 7.300 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[6] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[4] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.900 ns ; ; 0.700 ns ; 136.99 MHz ( period = 7.300 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[5] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[4] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.900 ns ; ; 0.700 ns ; 136.99 MHz ( period = 7.300 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[4] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[4] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.900 ns ; ; 0.700 ns ; 136.99 MHz ( period = 7.300 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[3] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[4] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.900 ns ; ; 0.700 ns ; 136.99 MHz ( period = 7.300 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[2] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[4] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.900 ns ; ; 0.700 ns ; 136.99 MHz ( period = 7.300 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[0] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[4] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.900 ns ; ; 0.700 ns ; 136.99 MHz ( period = 7.300 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[10] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[7] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.900 ns ; ; 0.700 ns ; 136.99 MHz ( period = 7.300 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[9] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[7] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.900 ns ; ; 0.700 ns ; 136.99 MHz ( period = 7.300 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[8] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[7] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.900 ns ; ; 0.700 ns ; 136.99 MHz ( period = 7.300 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[7] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[7] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.900 ns ; ; 0.700 ns ; 136.99 MHz ( period = 7.300 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[6] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[7] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.900 ns ; ; 0.700 ns ; 136.99 MHz ( period = 7.300 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[5] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[7] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.900 ns ; ; 0.700 ns ; 136.99 MHz ( period = 7.300 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[4] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[7] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.900 ns ; ; 0.700 ns ; 136.99 MHz ( period = 7.300 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[3] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[7] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.900 ns ; ; 0.700 ns ; 136.99 MHz ( period = 7.300 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[2] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[7] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.900 ns ; ; 0.700 ns ; 136.99 MHz ( period = 7.300 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[0] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[7] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.900 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[10] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[2] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[9] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[2] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[8] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[2] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[7] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[2] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[6] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[2] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[5] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[2] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[4] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[2] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[3] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[2] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[2] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[2] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[1] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[2] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[0] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[2] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[10] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[4] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[9] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[4] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[8] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[4] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[7] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[4] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[6] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[4] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[5] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[4] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[4] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[4] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[3] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[4] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[2] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[4] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[1] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[4] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[0] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[4] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[10] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[5] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[9] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[5] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[8] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[5] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[7] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[5] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[6] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[5] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[5] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[5] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[4] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[5] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[3] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[5] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[2] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[5] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[1] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[5] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[0] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[5] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[10] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[0] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[9] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[0] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[8] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[0] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[7] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[0] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[6] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[0] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[5] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[0] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[4] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[0] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[3] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[0] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[2] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[0] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[0] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[0] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; dpm_ni2f_fifo_h_reg_fifo_full ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[0] ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.200 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; dpm_ni2f_fifo_h_reg_fifo_full ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[1] ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.200 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; dpm_ni2f_fifo_h_reg_fifo_full ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[2] ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.200 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; dpm_ni2f_fifo_h_reg_fifo_full ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[3] ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.200 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; dpm_ni2f_fifo_h_reg_fifo_full ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[4] ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.200 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[10] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[1] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[9] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[1] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[8] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[1] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[7] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[1] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[6] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[1] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[5] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[1] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[4] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[1] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[3] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[1] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[2] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[1] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[0] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[1] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[10] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[3] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[9] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[3] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[8] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[3] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[7] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[3] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[6] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[3] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[5] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[3] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[4] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[3] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[3] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[3] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[2] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[3] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[0] ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[3] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.800 ns ; ; 0.800 ns ; 138.89 MHz ( period = 7.200 ns ) ; dpm_ni2f_fifo_l_reg_nwords_2 ; dpm_ni2f_fifo_l_reg_nwords_7 ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.200 ns ; ; 0.900 ns ; 140.85 MHz ( period = 7.100 ns ) ; dpm_ni2f_reg_sm_5 ; dpm_ni2f_reg_clk_sram_i ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.100 ns ; ; 0.900 ns ; 140.85 MHz ( period = 7.100 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[10] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[1] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.700 ns ; ; 0.900 ns ; 140.85 MHz ( period = 7.100 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[9] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[1] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.700 ns ; ; 0.900 ns ; 140.85 MHz ( period = 7.100 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[8] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[1] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.700 ns ; ; 0.900 ns ; 140.85 MHz ( period = 7.100 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[7] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[1] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.700 ns ; ; 0.900 ns ; 140.85 MHz ( period = 7.100 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[6] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[1] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.700 ns ; ; 0.900 ns ; 140.85 MHz ( period = 7.100 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[5] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[1] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.700 ns ; ; 0.900 ns ; 140.85 MHz ( period = 7.100 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[4] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[1] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.700 ns ; ; 0.900 ns ; 140.85 MHz ( period = 7.100 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[3] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[1] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.700 ns ; ; 0.900 ns ; 140.85 MHz ( period = 7.100 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[2] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[1] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.700 ns ; ; 0.900 ns ; 140.85 MHz ( period = 7.100 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[1] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[1] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.700 ns ; ; 0.900 ns ; 140.85 MHz ( period = 7.100 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[0] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[1] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.700 ns ; ; 0.900 ns ; 140.85 MHz ( period = 7.100 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[10] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[3] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.700 ns ; ; 0.900 ns ; 140.85 MHz ( period = 7.100 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[9] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[3] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.700 ns ; ; 0.900 ns ; 140.85 MHz ( period = 7.100 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[8] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[3] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.700 ns ; ; 0.900 ns ; 140.85 MHz ( period = 7.100 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[7] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[3] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.700 ns ; ; 0.900 ns ; 140.85 MHz ( period = 7.100 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[6] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[3] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.700 ns ; ; 0.900 ns ; 140.85 MHz ( period = 7.100 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[5] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[3] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.700 ns ; ; 0.900 ns ; 140.85 MHz ( period = 7.100 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[4] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[3] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.700 ns ; ; 0.900 ns ; 140.85 MHz ( period = 7.100 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[3] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[3] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.700 ns ; ; 0.900 ns ; 140.85 MHz ( period = 7.100 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[2] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[3] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.700 ns ; ; 0.900 ns ; 140.85 MHz ( period = 7.100 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[1] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[3] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.700 ns ; ; 0.900 ns ; 140.85 MHz ( period = 7.100 ns ) ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[0] ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[3] ; DES_CLK ; DES_CLK ; 8.000 ns ; 6.600 ns ; 5.700 ns ; ; 0.900 ns ; 140.85 MHz ( period = 7.100 ns ) ; dpm_ni2f_fifo_h_reg_fifo_full ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[5] ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.100 ns ; ; 0.900 ns ; 140.85 MHz ( period = 7.100 ns ) ; dpm_ni2f_fifo_h_reg_fifo_full ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[6] ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.100 ns ; ; 0.900 ns ; 140.85 MHz ( period = 7.100 ns ) ; dpm_ni2f_fifo_h_reg_fifo_full ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[7] ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.100 ns ; ; 0.900 ns ; 140.85 MHz ( period = 7.100 ns ) ; dpm_ni2f_fifo_h_reg_fifo_full ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[8] ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.100 ns ; ; 0.900 ns ; 140.85 MHz ( period = 7.100 ns ) ; dpm_ni2f_fifo_h_reg_fifo_full ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[9] ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.100 ns ; ; 0.900 ns ; 140.85 MHz ( period = 7.100 ns ) ; dpm_ni2f_fifo_h_reg_fifo_full ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[10] ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.100 ns ; ; 0.900 ns ; 140.85 MHz ( period = 7.100 ns ) ; dpm_ni2f_reg_des_valid_data ; lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[0] ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.100 ns ; ; 0.900 ns ; 140.85 MHz ( period = 7.100 ns ) ; dpm_ni2f_reg_des_valid_data ; lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[1] ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.100 ns ; ; 0.900 ns ; 140.85 MHz ( period = 7.100 ns ) ; dpm_ni2f_reg_des_valid_data ; lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[2] ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.100 ns ; ; 0.900 ns ; 140.85 MHz ( period = 7.100 ns ) ; dpm_ni2f_reg_des_valid_data ; lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[3] ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.100 ns ; ; 0.900 ns ; 140.85 MHz ( period = 7.100 ns ) ; dpm_ni2f_reg_des_valid_data ; lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[4] ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.100 ns ; ; 0.900 ns ; 140.85 MHz ( period = 7.100 ns ) ; dpm_ni2f_reg_des_valid_data ; lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[5] ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.100 ns ; ; 0.900 ns ; 140.85 MHz ( period = 7.100 ns ) ; dpm_ni2f_reg_des_valid_data ; lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[6] ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.100 ns ; ; 0.900 ns ; 140.85 MHz ( period = 7.100 ns ) ; dpm_ni2f_reg_des_valid_data ; lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[7] ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.100 ns ; ; 0.900 ns ; 140.85 MHz ( period = 7.100 ns ) ; dpm_ni2f_reg_des_valid_data ; lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[8] ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.100 ns ; ; 0.900 ns ; 140.85 MHz ( period = 7.100 ns ) ; dpm_ni2f_reg_des_valid_data ; lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[9] ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.100 ns ; ; 0.900 ns ; 140.85 MHz ( period = 7.100 ns ) ; dpm_ni2f_reg_des_valid_data ; lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[10] ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.100 ns ; ; 0.900 ns ; 140.85 MHz ( period = 7.100 ns ) ; dpm_ni2f_fifo_l_reg_nwords_3 ; dpm_ni2f_fifo_l_reg_nwords_7 ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.100 ns ; ; 0.900 ns ; 140.85 MHz ( period = 7.100 ns ) ; dpm_ni2f_fifo_l_reg_nwords_4 ; dpm_ni2f_fifo_l_reg_nwords_7 ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.100 ns ; ; 0.900 ns ; 140.85 MHz ( period = 7.100 ns ) ; dpm_ni2f_fifo_l_reg_nwords_7 ; dpm_ni2f_fifo_l_reg_nwords_7 ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.100 ns ; ; 1.000 ns ; 142.86 MHz ( period = 7.000 ns ) ; dpm_ni2f_fifo_h_reg_fifo_empty ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[0] ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.000 ns ; ; 1.000 ns ; 142.86 MHz ( period = 7.000 ns ) ; dpm_ni2f_fifo_h_reg_fifo_empty ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[1] ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.000 ns ; ; 1.000 ns ; 142.86 MHz ( period = 7.000 ns ) ; dpm_ni2f_fifo_h_reg_fifo_empty ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[2] ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.000 ns ; ; 1.000 ns ; 142.86 MHz ( period = 7.000 ns ) ; dpm_ni2f_fifo_h_reg_fifo_empty ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[3] ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.000 ns ; ; 1.000 ns ; 142.86 MHz ( period = 7.000 ns ) ; dpm_ni2f_fifo_h_reg_fifo_empty ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[4] ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.000 ns ; ; 1.000 ns ; 142.86 MHz ( period = 7.000 ns ) ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[31] ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[7] ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.000 ns ; ; 1.000 ns ; 142.86 MHz ( period = 7.000 ns ) ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[31] ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[6] ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.000 ns ; ; 1.000 ns ; 142.86 MHz ( period = 7.000 ns ) ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[31] ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[5] ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.000 ns ; ; 1.000 ns ; 142.86 MHz ( period = 7.000 ns ) ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[31] ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[4] ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.000 ns ; ; 1.000 ns ; 142.86 MHz ( period = 7.000 ns ) ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[31] ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[3] ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.000 ns ; ; 1.000 ns ; 142.86 MHz ( period = 7.000 ns ) ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[31] ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[2] ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.000 ns ; ; 1.000 ns ; 142.86 MHz ( period = 7.000 ns ) ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[31] ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[1] ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.000 ns ; ; 1.000 ns ; 142.86 MHz ( period = 7.000 ns ) ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[31] ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[0] ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 6.000 ns ; ; 1.100 ns ; 144.93 MHz ( period = 6.900 ns ) ; dpm_ni2f_reg_sm_9 ; dpm_ni2f_reg_clk_sram_i ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 5.900 ns ; ; 1.100 ns ; 144.93 MHz ( period = 6.900 ns ) ; dpm_ni2f_fifo_h_reg_fifo_empty ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[5] ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 5.900 ns ; ; 1.100 ns ; 144.93 MHz ( period = 6.900 ns ) ; dpm_ni2f_fifo_h_reg_fifo_empty ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[6] ; DES_CLK ; DES_CLK ; 8.000 ns ; 7.000 ns ; 5.900 ns ; ; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ; +-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------------------------+---------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+ +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Clock Setup: 'pci_clk' ; +-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------+----------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+ ; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ; +-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------+----------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+ ; 10.111 ns ; 51.81 MHz ( period = 19.300 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[0] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 18.300 ns ; ; 10.211 ns ; 52.08 MHz ( period = 19.200 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[0] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 18.200 ns ; ; 11.811 ns ; 56.82 MHz ( period = 17.600 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[0] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 16.600 ns ; ; 11.911 ns ; 57.14 MHz ( period = 17.500 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[0] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 16.500 ns ; ; 12.011 ns ; 57.47 MHz ( period = 17.400 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[4] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[0] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 16.400 ns ; ; 12.111 ns ; 57.80 MHz ( period = 17.300 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[7] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 16.300 ns ; ; 12.111 ns ; 57.80 MHz ( period = 17.300 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[4] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[0] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 16.300 ns ; ; 12.211 ns ; 58.14 MHz ( period = 17.200 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[7] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 16.200 ns ; ; 12.811 ns ; 60.24 MHz ( period = 16.600 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[6] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 15.600 ns ; ; 12.811 ns ; 60.24 MHz ( period = 16.600 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[1] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 15.600 ns ; ; 12.911 ns ; 60.61 MHz ( period = 16.500 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[5] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 15.500 ns ; ; 12.911 ns ; 60.61 MHz ( period = 16.500 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[1] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 15.500 ns ; ; 12.911 ns ; 60.61 MHz ( period = 16.500 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[6] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 15.500 ns ; ; 13.011 ns ; 60.98 MHz ( period = 16.400 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[5] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 15.400 ns ; ; 13.111 ns ; 61.35 MHz ( period = 16.300 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[16] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 15.300 ns ; ; 13.111 ns ; 61.35 MHz ( period = 16.300 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[17] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 15.300 ns ; ; 13.111 ns ; 61.35 MHz ( period = 16.300 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[18] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 15.300 ns ; ; 13.111 ns ; 61.35 MHz ( period = 16.300 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[19] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 15.300 ns ; ; 13.211 ns ; 61.73 MHz ( period = 16.200 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[20] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 15.200 ns ; ; 13.211 ns ; 61.73 MHz ( period = 16.200 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[17] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 15.200 ns ; ; 13.211 ns ; 61.73 MHz ( period = 16.200 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[18] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 15.200 ns ; ; 13.311 ns ; 62.11 MHz ( period = 16.100 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[23] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 15.100 ns ; ; 13.311 ns ; 62.11 MHz ( period = 16.100 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[19] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 15.100 ns ; ; 13.311 ns ; 62.11 MHz ( period = 16.100 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[20] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 15.100 ns ; ; 13.411 ns ; 62.50 MHz ( period = 16.000 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[4] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 15.000 ns ; ; 13.411 ns ; 62.50 MHz ( period = 16.000 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[23] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 15.000 ns ; ; 13.511 ns ; 62.89 MHz ( period = 15.900 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[2] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 14.900 ns ; ; 13.511 ns ; 62.89 MHz ( period = 15.900 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[27] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 14.900 ns ; ; 13.511 ns ; 62.89 MHz ( period = 15.900 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[28] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 14.900 ns ; ; 13.511 ns ; 62.89 MHz ( period = 15.900 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[4] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 14.900 ns ; ; 13.611 ns ; 63.29 MHz ( period = 15.800 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[12] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 14.800 ns ; ; 13.611 ns ; 63.29 MHz ( period = 15.800 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[25] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 14.800 ns ; ; 13.611 ns ; 63.29 MHz ( period = 15.800 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[26] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 14.800 ns ; ; 13.611 ns ; 63.29 MHz ( period = 15.800 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[2] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 14.800 ns ; ; 13.611 ns ; 63.29 MHz ( period = 15.800 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[27] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 14.800 ns ; ; 13.611 ns ; 63.29 MHz ( period = 15.800 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[28] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 14.800 ns ; ; 13.711 ns ; 63.69 MHz ( period = 15.700 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[8] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 14.700 ns ; ; 13.711 ns ; 63.69 MHz ( period = 15.700 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[24] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 14.700 ns ; ; 13.711 ns ; 63.69 MHz ( period = 15.700 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[12] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 14.700 ns ; ; 13.711 ns ; 63.69 MHz ( period = 15.700 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[25] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 14.700 ns ; ; 13.711 ns ; 63.69 MHz ( period = 15.700 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[26] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 14.700 ns ; ; 13.811 ns ; 64.10 MHz ( period = 15.600 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[7] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 14.600 ns ; ; 13.811 ns ; 64.10 MHz ( period = 15.600 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[21] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 14.600 ns ; ; 13.811 ns ; 64.10 MHz ( period = 15.600 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[8] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 14.600 ns ; ; 13.811 ns ; 64.10 MHz ( period = 15.600 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[24] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 14.600 ns ; ; 13.911 ns ; 64.52 MHz ( period = 15.500 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[30] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 14.500 ns ; ; 13.911 ns ; 64.52 MHz ( period = 15.500 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[7] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 14.500 ns ; ; 13.911 ns ; 64.52 MHz ( period = 15.500 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[21] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 14.500 ns ; ; 14.011 ns ; 64.94 MHz ( period = 15.400 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[4] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[7] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 14.400 ns ; ; 14.011 ns ; 64.94 MHz ( period = 15.400 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[10] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 14.400 ns ; ; 14.011 ns ; 64.94 MHz ( period = 15.400 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[11] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 14.400 ns ; ; 14.011 ns ; 64.94 MHz ( period = 15.400 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[30] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 14.400 ns ; ; 14.111 ns ; 65.36 MHz ( period = 15.300 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[3] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 14.300 ns ; ; 14.111 ns ; 65.36 MHz ( period = 15.300 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[4] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[7] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 14.300 ns ; ; 14.111 ns ; 65.36 MHz ( period = 15.300 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[10] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 14.300 ns ; ; 14.111 ns ; 65.36 MHz ( period = 15.300 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[11] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 14.300 ns ; ; 14.211 ns ; 65.79 MHz ( period = 15.200 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[19] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[0] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 14.200 ns ; ; 14.211 ns ; 65.79 MHz ( period = 15.200 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[3] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 14.200 ns ; ; 14.211 ns ; 65.79 MHz ( period = 15.200 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[16] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 14.200 ns ; ; 14.311 ns ; 66.23 MHz ( period = 15.100 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[22] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 14.100 ns ; ; 14.311 ns ; 66.23 MHz ( period = 15.100 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[19] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[0] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 14.100 ns ; ; 14.411 ns ; 66.67 MHz ( period = 15.000 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[22] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 14.000 ns ; ; 14.511 ns ; 67.11 MHz ( period = 14.900 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[6] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.900 ns ; ; 14.511 ns ; 67.11 MHz ( period = 14.900 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[9] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.900 ns ; ; 14.511 ns ; 67.11 MHz ( period = 14.900 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[1] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.900 ns ; ; 14.611 ns ; 67.57 MHz ( period = 14.800 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[5] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.800 ns ; ; 14.611 ns ; 67.57 MHz ( period = 14.800 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[29] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.800 ns ; ; 14.611 ns ; 67.57 MHz ( period = 14.800 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[1] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.800 ns ; ; 14.611 ns ; 67.57 MHz ( period = 14.800 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[6] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.800 ns ; ; 14.611 ns ; 67.57 MHz ( period = 14.800 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[9] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.800 ns ; ; 14.611 ns ; 67.57 MHz ( period = 14.800 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[13] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.800 ns ; ; 14.711 ns ; 68.03 MHz ( period = 14.700 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[4] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[6] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.700 ns ; ; 14.711 ns ; 68.03 MHz ( period = 14.700 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[19] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[8] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.700 ns ; ; 14.711 ns ; 68.03 MHz ( period = 14.700 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[4] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[1] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.700 ns ; ; 14.711 ns ; 68.03 MHz ( period = 14.700 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[31] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.700 ns ; ; 14.711 ns ; 68.03 MHz ( period = 14.700 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[5] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.700 ns ; ; 14.711 ns ; 68.03 MHz ( period = 14.700 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[29] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.700 ns ; ; 14.811 ns ; 68.49 MHz ( period = 14.600 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[4] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[5] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.600 ns ; ; 14.811 ns ; 68.49 MHz ( period = 14.600 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[14] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.600 ns ; ; 14.811 ns ; 68.49 MHz ( period = 14.600 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[15] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.600 ns ; ; 14.811 ns ; 68.49 MHz ( period = 14.600 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[16] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.600 ns ; ; 14.811 ns ; 68.49 MHz ( period = 14.600 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[17] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.600 ns ; ; 14.811 ns ; 68.49 MHz ( period = 14.600 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[18] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.600 ns ; ; 14.811 ns ; 68.49 MHz ( period = 14.600 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[19] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.600 ns ; ; 14.811 ns ; 68.49 MHz ( period = 14.600 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[4] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[1] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.600 ns ; ; 14.811 ns ; 68.49 MHz ( period = 14.600 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[4] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[6] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.600 ns ; ; 14.811 ns ; 68.49 MHz ( period = 14.600 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[19] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[8] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.600 ns ; ; 14.811 ns ; 68.49 MHz ( period = 14.600 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[31] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.600 ns ; ; 14.911 ns ; 68.97 MHz ( period = 14.500 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[20] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.500 ns ; ; 14.911 ns ; 68.97 MHz ( period = 14.500 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[4] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[5] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.500 ns ; ; 14.911 ns ; 68.97 MHz ( period = 14.500 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[14] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.500 ns ; ; 14.911 ns ; 68.97 MHz ( period = 14.500 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[15] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.500 ns ; ; 14.911 ns ; 68.97 MHz ( period = 14.500 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[17] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.500 ns ; ; 14.911 ns ; 68.97 MHz ( period = 14.500 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[18] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.500 ns ; ; 15.011 ns ; 69.44 MHz ( period = 14.400 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[13] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.400 ns ; ; 15.011 ns ; 69.44 MHz ( period = 14.400 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[4] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[16] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.400 ns ; ; 15.011 ns ; 69.44 MHz ( period = 14.400 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[4] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[17] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.400 ns ; ; 15.011 ns ; 69.44 MHz ( period = 14.400 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[4] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[18] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.400 ns ; ; 15.011 ns ; 69.44 MHz ( period = 14.400 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[3] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[0] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.400 ns ; ; 15.011 ns ; 69.44 MHz ( period = 14.400 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[4] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[19] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.400 ns ; ; 15.011 ns ; 69.44 MHz ( period = 14.400 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[23] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.400 ns ; ; 15.011 ns ; 69.44 MHz ( period = 14.400 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[19] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.400 ns ; ; 15.011 ns ; 69.44 MHz ( period = 14.400 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[20] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.400 ns ; ; 15.111 ns ; 69.93 MHz ( period = 14.300 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[4] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.300 ns ; ; 15.111 ns ; 69.93 MHz ( period = 14.300 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_IDLE_not ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[6] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.300 ns ; ; 15.111 ns ; 69.93 MHz ( period = 14.300 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[4] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[20] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.300 ns ; ; 15.111 ns ; 69.93 MHz ( period = 14.300 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[3] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[0] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.300 ns ; ; 15.111 ns ; 69.93 MHz ( period = 14.300 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[4] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[17] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.300 ns ; ; 15.111 ns ; 69.93 MHz ( period = 14.300 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[4] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[18] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.300 ns ; ; 15.111 ns ; 69.93 MHz ( period = 14.300 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[23] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.300 ns ; ; 15.211 ns ; 70.42 MHz ( period = 14.200 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[2] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.200 ns ; ; 15.211 ns ; 70.42 MHz ( period = 14.200 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[4] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[23] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.200 ns ; ; 15.211 ns ; 70.42 MHz ( period = 14.200 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[27] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.200 ns ; ; 15.211 ns ; 70.42 MHz ( period = 14.200 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[28] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.200 ns ; ; 15.211 ns ; 70.42 MHz ( period = 14.200 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[4] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.200 ns ; ; 15.211 ns ; 70.42 MHz ( period = 14.200 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[4] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[19] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.200 ns ; ; 15.211 ns ; 70.42 MHz ( period = 14.200 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[4] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[20] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.200 ns ; ; 15.311 ns ; 70.92 MHz ( period = 14.100 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[4] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[4] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.100 ns ; ; 15.311 ns ; 70.92 MHz ( period = 14.100 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[12] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.100 ns ; ; 15.311 ns ; 70.92 MHz ( period = 14.100 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[25] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.100 ns ; ; 15.311 ns ; 70.92 MHz ( period = 14.100 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[26] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.100 ns ; ; 15.311 ns ; 70.92 MHz ( period = 14.100 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[2] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.100 ns ; ; 15.311 ns ; 70.92 MHz ( period = 14.100 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[4] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[23] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.100 ns ; ; 15.311 ns ; 70.92 MHz ( period = 14.100 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[27] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.100 ns ; ; 15.311 ns ; 70.92 MHz ( period = 14.100 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[28] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.100 ns ; ; 15.411 ns ; 71.43 MHz ( period = 14.000 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[4] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[2] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.000 ns ; ; 15.411 ns ; 71.43 MHz ( period = 14.000 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[8] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.000 ns ; ; 15.411 ns ; 71.43 MHz ( period = 14.000 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[24] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.000 ns ; ; 15.411 ns ; 71.43 MHz ( period = 14.000 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[4] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[27] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.000 ns ; ; 15.411 ns ; 71.43 MHz ( period = 14.000 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[4] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[28] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.000 ns ; ; 15.411 ns ; 71.43 MHz ( period = 14.000 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[4] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[4] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.000 ns ; ; 15.411 ns ; 71.43 MHz ( period = 14.000 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[12] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.000 ns ; ; 15.411 ns ; 71.43 MHz ( period = 14.000 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[25] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.000 ns ; ; 15.411 ns ; 71.43 MHz ( period = 14.000 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[26] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 13.000 ns ; ; 15.511 ns ; 71.94 MHz ( period = 13.900 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[19] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[9] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.900 ns ; ; 15.511 ns ; 71.94 MHz ( period = 13.900 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[4] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[12] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.900 ns ; ; 15.511 ns ; 71.94 MHz ( period = 13.900 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[21] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.900 ns ; ; 15.511 ns ; 71.94 MHz ( period = 13.900 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[4] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[25] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.900 ns ; ; 15.511 ns ; 71.94 MHz ( period = 13.900 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[4] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[26] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.900 ns ; ; 15.511 ns ; 71.94 MHz ( period = 13.900 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[4] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[2] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.900 ns ; ; 15.511 ns ; 71.94 MHz ( period = 13.900 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[8] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.900 ns ; ; 15.511 ns ; 71.94 MHz ( period = 13.900 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[24] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.900 ns ; ; 15.511 ns ; 71.94 MHz ( period = 13.900 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[4] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[27] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.900 ns ; ; 15.511 ns ; 71.94 MHz ( period = 13.900 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[4] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[28] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.900 ns ; ; 15.611 ns ; 72.46 MHz ( period = 13.800 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[4] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[8] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.800 ns ; ; 15.611 ns ; 72.46 MHz ( period = 13.800 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[4] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[24] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.800 ns ; ; 15.611 ns ; 72.46 MHz ( period = 13.800 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[30] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.800 ns ; ; 15.611 ns ; 72.46 MHz ( period = 13.800 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[19] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[9] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.800 ns ; ; 15.611 ns ; 72.46 MHz ( period = 13.800 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[4] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[12] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.800 ns ; ; 15.611 ns ; 72.46 MHz ( period = 13.800 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[21] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.800 ns ; ; 15.611 ns ; 72.46 MHz ( period = 13.800 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[4] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[25] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.800 ns ; ; 15.611 ns ; 72.46 MHz ( period = 13.800 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[4] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[26] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.800 ns ; ; 15.711 ns ; 72.99 MHz ( period = 13.700 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[10] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.700 ns ; ; 15.711 ns ; 72.99 MHz ( period = 13.700 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[11] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.700 ns ; ; 15.711 ns ; 72.99 MHz ( period = 13.700 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[4] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[21] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.700 ns ; ; 15.711 ns ; 72.99 MHz ( period = 13.700 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_IDLE_not ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[31] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.700 ns ; ; 15.711 ns ; 72.99 MHz ( period = 13.700 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_IDLE_not ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|trdy_OR_NOT ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.700 ns ; ; 15.711 ns ; 72.99 MHz ( period = 13.700 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[4] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[8] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.700 ns ; ; 15.711 ns ; 72.99 MHz ( period = 13.700 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[4] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[24] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.700 ns ; ; 15.711 ns ; 72.99 MHz ( period = 13.700 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[30] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.700 ns ; ; 15.811 ns ; 73.53 MHz ( period = 13.600 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[3] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.600 ns ; ; 15.811 ns ; 73.53 MHz ( period = 13.600 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|cfg_cyc ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[5] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.600 ns ; ; 15.811 ns ; 73.53 MHz ( period = 13.600 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|cfg_cyc ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[6] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.600 ns ; ; 15.811 ns ; 73.53 MHz ( period = 13.600 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[4] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[30] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.600 ns ; ; 15.811 ns ; 73.53 MHz ( period = 13.600 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[10] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.600 ns ; ; 15.811 ns ; 73.53 MHz ( period = 13.600 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[11] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.600 ns ; ; 15.811 ns ; 73.53 MHz ( period = 13.600 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[4] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[21] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.600 ns ; ; 15.911 ns ; 74.07 MHz ( period = 13.500 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[19] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[7] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.500 ns ; ; 15.911 ns ; 74.07 MHz ( period = 13.500 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|cfg_cyc ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[8] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.500 ns ; ; 15.911 ns ; 74.07 MHz ( period = 13.500 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[4] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[10] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.500 ns ; ; 15.911 ns ; 74.07 MHz ( period = 13.500 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[4] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[11] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.500 ns ; ; 15.911 ns ; 74.07 MHz ( period = 13.500 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|cfg_cyc ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[1] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.500 ns ; ; 15.911 ns ; 74.07 MHz ( period = 13.500 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[3] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.500 ns ; ; 15.911 ns ; 74.07 MHz ( period = 13.500 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[16] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.500 ns ; ; 15.911 ns ; 74.07 MHz ( period = 13.500 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[4] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[30] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.500 ns ; ; 16.011 ns ; 74.63 MHz ( period = 13.400 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[4] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[3] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.400 ns ; ; 16.011 ns ; 74.63 MHz ( period = 13.400 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_IDLE_not ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[4] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.400 ns ; ; 16.011 ns ; 74.63 MHz ( period = 13.400 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|cfg_cyc ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[7] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.400 ns ; ; 16.011 ns ; 74.63 MHz ( period = 13.400 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[22] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.400 ns ; ; 16.011 ns ; 74.63 MHz ( period = 13.400 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[19] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[7] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.400 ns ; ; 16.011 ns ; 74.63 MHz ( period = 13.400 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[4] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[10] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.400 ns ; ; 16.011 ns ; 74.63 MHz ( period = 13.400 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[4] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[11] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.400 ns ; ; 16.111 ns ; 75.19 MHz ( period = 13.300 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[19] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[6] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.300 ns ; ; 16.111 ns ; 75.19 MHz ( period = 13.300 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|cfg_cyc ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[11] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.300 ns ; ; 16.111 ns ; 75.19 MHz ( period = 13.300 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_IDLE_not ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[21] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.300 ns ; ; 16.111 ns ; 75.19 MHz ( period = 13.300 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[19] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[31] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.300 ns ; ; 16.111 ns ; 75.19 MHz ( period = 13.300 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[4] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[3] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.300 ns ; ; 16.111 ns ; 75.19 MHz ( period = 13.300 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[4] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[16] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.300 ns ; ; 16.111 ns ; 75.19 MHz ( period = 13.300 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[22] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.300 ns ; ; 16.211 ns ; 75.76 MHz ( period = 13.200 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|cfg_cyc ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[2] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.200 ns ; ; 16.211 ns ; 75.76 MHz ( period = 13.200 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|cfg_cyc ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[4] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.200 ns ; ; 16.211 ns ; 75.76 MHz ( period = 13.200 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[9] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.200 ns ; ; 16.211 ns ; 75.76 MHz ( period = 13.200 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[4] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[22] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.200 ns ; ; 16.211 ns ; 75.76 MHz ( period = 13.200 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|cfg_cyc ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[31] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.200 ns ; ; 16.211 ns ; 75.76 MHz ( period = 13.200 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[19] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[6] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.200 ns ; ; 16.211 ns ; 75.76 MHz ( period = 13.200 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[19] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[31] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.200 ns ; ; 16.311 ns ; 76.34 MHz ( period = 13.100 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_IDLE_not ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[16] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.100 ns ; ; 16.311 ns ; 76.34 MHz ( period = 13.100 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_IDLE_not ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[17] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.100 ns ; ; 16.311 ns ; 76.34 MHz ( period = 13.100 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[29] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.100 ns ; ; 16.311 ns ; 76.34 MHz ( period = 13.100 ns ) ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[9] ; pci_clk ; pci_clk ; 29.411 ns ; 28.411 ns ; 12.100 ns ; ; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ; +-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------+----------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+ +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Clock Hold: 'DES_CLK' ; +-----------------------------------------+----------------------------------------------------------------------------------+----------------------------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+ ; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ; +-----------------------------------------+----------------------------------------------------------------------------------+----------------------------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+ ; 0.600 ns ; dpm_ni2f_fifo_h_reg_fifo_empty ; dpm_ni2f_fifo_h_reg_fifo_empty ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; dpm_ni2f_reg_not_empty ; dpm_ni2f_reg_not_empty ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; dpm_ni2f_reg_sm_4 ; dpm_ni2f_reg_sm_5 ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; dpm_ni2f_reg_addr_1 ; dpm_ni2f_reg_addr_1 ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; dpm_ni2f_reg_addr_2 ; dpm_ni2f_reg_addr_2 ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; dpm_ni2f_reg_addr_3 ; dpm_ni2f_reg_addr_3 ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; dpm_ni2f_reg_addr_4 ; dpm_ni2f_reg_addr_4 ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; dpm_ni2f_reg_addr_5 ; dpm_ni2f_reg_addr_5 ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; dpm_ni2f_reg_addr_6 ; dpm_ni2f_reg_addr_6 ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; dpm_ni2f_reg_addr_7 ; dpm_ni2f_reg_addr_7 ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; dpm_ni2f_reg_addr_8 ; dpm_ni2f_reg_addr_8 ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; dpm_ni2f_reg_addr_9 ; dpm_ni2f_reg_addr_9 ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; dpm_ni2f_reg_addr_10 ; dpm_ni2f_reg_addr_10 ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; dpm_ni2f_reg_addr_11 ; dpm_ni2f_reg_addr_11 ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; dpm_ni2f_reg_addr_12 ; dpm_ni2f_reg_addr_12 ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; dpm_ni2f_reg_addr_13 ; dpm_ni2f_reg_addr_13 ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; dpm_ni2f_reg_addr_14 ; dpm_ni2f_reg_addr_14 ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; dpm_ni2f_reg_addr_15 ; dpm_ni2f_reg_addr_15 ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; dpm_ni2f_reg_addr_16 ; dpm_ni2f_reg_addr_16 ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; dpm_ni2f_reg_addr_17 ; dpm_ni2f_reg_addr_17 ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; dpm_ni2f_reg_rdreq_fifo ; dpm_ni2f_reg_re_n ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; dpm_ni2f_reg_sm_9 ; dpm_ni2f_reg_sm_10 ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; dpm_ni2f_fifo_l_reg_fifo_empty ; dpm_ni2f_fifo_l_reg_fifo_empty ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; dpm_ni2f_reg_sm_7 ; dpm_ni2f_reg_sm_8 ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; dpm_ni2f_reg_sm_6 ; dpm_ni2f_reg_sm_7 ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.700 ns ; dpm_ni2f_reg_addr_0 ; dpm_ni2f_reg_addr_0 ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[0] ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[0] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[1] ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[1] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[0] ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[1] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[2] ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[2] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[1] ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[2] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[3] ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[3] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[2] ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[3] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[4] ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[4] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[3] ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[4] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[5] ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[5] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[6] ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[6] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[5] ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[6] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[7] ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[7] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[6] ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[7] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[8] ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[8] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[7] ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[8] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[9] ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[9] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[8] ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[9] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[10] ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[10] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[9] ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[10] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[11] ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[11] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[10] ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[11] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[12] ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[12] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[11] ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[12] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[13] ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[13] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[14] ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[14] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[13] ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[14] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[15] ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[15] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[14] ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[15] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[16] ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[16] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[15] ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[16] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[17] ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[17] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[16] ; lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[17] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[0] ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[0] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[1] ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[1] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[0] ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[1] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[2] ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[2] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[1] ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[2] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[3] ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[3] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[2] ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[3] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[4] ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[4] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[3] ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[4] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[5] ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[5] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[6] ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[6] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[5] ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[6] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[7] ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[7] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[6] ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[7] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[8] ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[8] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[7] ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[8] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[9] ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[9] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[8] ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[9] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[10] ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[10] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[9] ; lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[10] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[0] ; lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[0] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[1] ; lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[1] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[0] ; lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[1] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[2] ; lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[2] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[1] ; lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[2] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[3] ; lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[3] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[2] ; lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[3] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[4] ; lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[4] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[3] ; lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[4] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[5] ; lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[5] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[6] ; lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[6] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[5] ; lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[6] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[7] ; lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[7] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[6] ; lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[7] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[8] ; lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[8] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[7] ; lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[8] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[9] ; lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[9] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[8] ; lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[9] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[10] ; lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[10] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[9] ; lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[10] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[0] ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[0] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[1] ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[1] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[0] ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[1] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[2] ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[2] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[1] ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[2] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[3] ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[3] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[2] ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[3] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[4] ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[4] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[3] ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[4] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[5] ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[5] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[6] ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[6] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[5] ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[6] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[7] ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[7] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[6] ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[7] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[8] ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[8] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[7] ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[8] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[9] ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[9] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[8] ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[9] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[10] ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[10] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[9] ; lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[10] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[0] ; lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[0] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[1] ; lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[1] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[0] ; lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[1] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[2] ; lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[2] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[1] ; lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[2] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[3] ; lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[3] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[2] ; lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[3] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[4] ; lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[4] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[3] ; lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[4] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[5] ; lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[5] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[6] ; lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[6] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[5] ; lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[6] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[7] ; lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[7] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[6] ; lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[7] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[8] ; lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[8] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[7] ; lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[8] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[9] ; lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[9] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[8] ; lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[9] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[10] ; lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[10] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[9] ; lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[10] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[8] ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[8] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[6] ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[7] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[7] ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[7] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[5] ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[6] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[6] ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[6] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[4] ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[5] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[5] ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[5] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[3] ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[4] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[4] ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[4] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[2] ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[3] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[3] ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[3] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[1] ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[2] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[2] ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[2] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[0] ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[1] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[1] ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[1] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[0] ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[0] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[30] ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[31] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[31] ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[31] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[9] ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[9] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[8] ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[9] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[10] ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[10] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[9] ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[10] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[11] ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[11] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[10] ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[11] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[12] ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[12] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[11] ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[12] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[13] ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[13] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[12] ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[13] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[14] ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[14] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[13] ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[14] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[15] ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[15] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[14] ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[15] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[16] ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[16] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[17] ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[17] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[16] ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[17] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_rcounter_ix7|alt_counter_f10ke:wysi_counter|q[0] ; lpm_counter:dpm_ni2f_rcounter_ix7|alt_counter_f10ke:wysi_counter|q[0] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[18] ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[18] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[17] ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[18] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_rcounter_ix7|alt_counter_f10ke:wysi_counter|q[1] ; lpm_counter:dpm_ni2f_rcounter_ix7|alt_counter_f10ke:wysi_counter|q[1] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_rcounter_ix7|alt_counter_f10ke:wysi_counter|q[0] ; lpm_counter:dpm_ni2f_rcounter_ix7|alt_counter_f10ke:wysi_counter|q[1] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[19] ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[19] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[18] ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[19] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_rcounter_ix7|alt_counter_f10ke:wysi_counter|q[2] ; lpm_counter:dpm_ni2f_rcounter_ix7|alt_counter_f10ke:wysi_counter|q[2] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_rcounter_ix7|alt_counter_f10ke:wysi_counter|q[1] ; lpm_counter:dpm_ni2f_rcounter_ix7|alt_counter_f10ke:wysi_counter|q[2] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[20] ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[20] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[19] ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[20] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_rcounter_ix7|alt_counter_f10ke:wysi_counter|q[3] ; lpm_counter:dpm_ni2f_rcounter_ix7|alt_counter_f10ke:wysi_counter|q[3] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_rcounter_ix7|alt_counter_f10ke:wysi_counter|q[2] ; lpm_counter:dpm_ni2f_rcounter_ix7|alt_counter_f10ke:wysi_counter|q[3] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[21] ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[21] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[20] ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[21] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_rcounter_ix7|alt_counter_f10ke:wysi_counter|q[4] ; lpm_counter:dpm_ni2f_rcounter_ix7|alt_counter_f10ke:wysi_counter|q[4] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_rcounter_ix7|alt_counter_f10ke:wysi_counter|q[3] ; lpm_counter:dpm_ni2f_rcounter_ix7|alt_counter_f10ke:wysi_counter|q[4] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[22] ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[22] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[21] ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[22] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_rcounter_ix7|alt_counter_f10ke:wysi_counter|q[5] ; lpm_counter:dpm_ni2f_rcounter_ix7|alt_counter_f10ke:wysi_counter|q[5] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_rcounter_ix7|alt_counter_f10ke:wysi_counter|q[4] ; lpm_counter:dpm_ni2f_rcounter_ix7|alt_counter_f10ke:wysi_counter|q[5] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[23] ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[23] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[22] ; lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[23] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[24] ; lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[24] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[22] ; lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[23] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[23] ; lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[23] ; DES_CLK ; DES_CLK ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; +-----------------------------------------+----------------------------------------------------------------------------------+----------------------------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+ +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Clock Hold: 'pci_clk' ; +-----------------------------------------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+ ; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ; +-----------------------------------------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+ ; 0.600 ns ; sg_reg_mx_q ; sg_reg_mx_q ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LW_IDLE_NOT ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_sr:wr_rdn_FF|REG ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|dac_cyc_reg ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|dac_cyc_reg ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|TS_IDLE_NOT ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|TS_ADR_VLD ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|TURN_AR_R ; pci_contr:pci|pci_mt32:pci_mt32_inst|perr_oe_r ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[6] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|cmd_reg[6] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MS_TAR ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|wr_rdn ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|TS_DXFR ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|TS_DXFR_R ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|frame_IR ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|frame_I1R ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; dpm_dec_reg_tmp3 ; dpm_dec_reg_LT_RDY_n_pci ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; dpm_dec_reg_tmp2 ; dpm_dec_reg_tmp3 ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|cmd_reg[0] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[0] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[2] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|pcimt32_cd:cfg_adr_dec|decR[2] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|cmd_reg[1] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[2] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|pcimt32_cd:cfg_adr_dec|decR[3] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|cache_line[3] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[3] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|cmd_reg[4] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[4] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|cache_line[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[5] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|cache_line[7] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[7] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[11] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|lat_tmr_reg[0] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[12] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|lat_tmr_reg[1] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[13] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|lat_tmr_reg[2] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|lat_tmr_reg[3] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[14] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[15] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|lat_tmr_reg[4] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[20] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|bar0_reg[20] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[21] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|bar0_reg[21] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[22] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|bar0_reg[22] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[25] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|bar0_reg[25] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[26] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|bar0_reg[26] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[27] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|bar0_reg[27] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|pcimt32_sr:$00213|REG ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[28] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|pcimt32_sr:$00215|REG ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[29] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|pcimt32_sr:$00217|REG ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[30] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_IDLE_not ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_IDLE_not ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[0] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|cache_line[0] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|cache_line[1] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[29] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|bar0_reg[29] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[30] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|bar0_reg[30] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; dpm_dec_reg_tmp1 ; dpm_dec_reg_tmp2 ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MS_TAR ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MS_TAR_R ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|latcntr_toR ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|latcntr_toR ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.600 ns ; dpm_dec_reg_tmp ; dpm_dec_reg_tmp1 ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.500 ns ; ; 0.700 ns ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[14] ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|q[15] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|q[15] ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|q[15] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; dpm_dec_reg_rdata_LED_5 ; dpm_dec_reg_rdata_LED_5 ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; dpm_dec_reg_rdata_LED_1 ; dpm_dec_reg_rdata_LED_1 ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; dpm_dec_reg_rdata_LED_4 ; dpm_dec_reg_rdata_LED_4 ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; dpm_dec_reg_rdata_LED_0 ; dpm_dec_reg_rdata_LED_0 ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; dpm_dec_reg_rdata_LED_7 ; dpm_dec_reg_rdata_LED_7 ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; dpm_dec_reg_rdata_LED_3 ; dpm_dec_reg_rdata_LED_3 ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; dpm_dec_reg_rdata_LED_6 ; dpm_dec_reg_rdata_LED_6 ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; dpm_dec_reg_rdata_LED_2 ; dpm_dec_reg_rdata_LED_2 ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[13] ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[14] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[14] ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[14] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[12] ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[13] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[13] ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[13] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[11] ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[12] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[12] ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[12] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[10] ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[11] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[11] ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[11] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[9] ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[10] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[10] ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[10] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[8] ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[9] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[9] ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[9] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[8] ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[8] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[6] ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[7] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[7] ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[7] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[5] ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[6] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[6] ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[6] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[4] ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[5] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[5] ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[5] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[3] ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[4] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[4] ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[4] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[2] ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[3] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[3] ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[3] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[1] ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[2] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[2] ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[2] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[0] ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[1] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[1] ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[1] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[0] ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[0] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LW_IDLE_NOT ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LW_IDLE_NOT ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|wr_rdn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|wr_rdn ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[2] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|pcimt32_cd:cfg_adr_dec|decR[1] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|bar_hitR[0] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|bar_hitR[0] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_IDLE_not ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_IDLE_not ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[11] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|WAIT_wait32 ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; dpm_dec_reg_rdata_CNF_0 ; dpm_dec_reg_rdata_CNF_0 ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; dpm_dec_reg_rdata_CNF_1 ; dpm_dec_reg_rdata_CNF_1 ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; dpm_dec_reg_rdata_CNF_2 ; dpm_dec_reg_rdata_CNF_2 ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; dpm_dec_reg_rdata_CNF_3 ; dpm_dec_reg_rdata_CNF_3 ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; dpm_dec_reg_rdata_CNF_4 ; dpm_dec_reg_rdata_CNF_4 ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; dpm_dec_reg_rdata_CNF_5 ; dpm_dec_reg_rdata_CNF_5 ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; dpm_dec_reg_rdata_CNF_6 ; dpm_dec_reg_rdata_CNF_6 ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; dpm_dec_reg_rdata_CNF_7 ; dpm_dec_reg_rdata_CNF_7 ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[2] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|pcimt32_cd:cfg_adr_dec|decR[0] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|cache_line[2] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[2] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; dpm_dec_reg_rdata_LED_8 ; dpm_dec_reg_rdata_LED_8 ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|cmd_reg[8] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[8] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; dpm_dec_reg_rdata_LED_9 ; dpm_dec_reg_rdata_LED_9 ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[2] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|pcimt32_cd:cfg_adr_dec|decR[4] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|stat_reg[8] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|stat_reg[8] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|pcimt32_sr:$00213|REG ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|pcimt32_sr:$00213|REG ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|pcimt32_sr:$00215|REG ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|pcimt32_sr:$00215|REG ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|pcimt32_sr:$00217|REG ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|pcimt32_sr:$00217|REG ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|pcimt32_sr:$00219|REG ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|pcimt32_sr:$00219|REG ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|retry ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|retry ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MS_TAR_R ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|perr_rep_setR ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_IDLE_NOT ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_IDLE_NOT ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_WAIT_32 ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_WAIT_32 ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:devsel_cntr|alt_counter_f10ke:wysi_counter|q[0] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:devsel_cntr|alt_counter_f10ke:wysi_counter|q[0] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:devsel_cntr|alt_counter_f10ke:wysi_counter|q[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:devsel_cntr|alt_counter_f10ke:wysi_counter|q[2] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:devsel_cntr|alt_counter_f10ke:wysi_counter|q[2] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:devsel_cntr|alt_counter_f10ke:wysi_counter|q[2] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:devsel_cntr|alt_counter_f10ke:wysi_counter|q[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:devsel_cntr|alt_counter_f10ke:wysi_counter|q[1] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:devsel_cntr|alt_counter_f10ke:wysi_counter|q[0] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:devsel_cntr|alt_counter_f10ke:wysi_counter|q[1] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_IDLE_not ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_END_r[2] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lreg_busy ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lreg_busy ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[0] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[0] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[6] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[7] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[7] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[7] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[6] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[6] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[6] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[4] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[5] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[5] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[3] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[4] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[4] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[4] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[2] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[3] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[3] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[3] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[2] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[2] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[2] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[1] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.700 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[0] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[1] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.600 ns ; ; 0.800 ns ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[13] ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|q[15] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.700 ns ; ; 0.800 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[1] ; dpm_dec_reg_rdata_LED_1 ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.700 ns ; ; 0.800 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[4] ; dpm_dec_reg_rdata_LED_4 ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.700 ns ; ; 0.800 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[6] ; dpm_dec_reg_rdata_LED_6 ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.700 ns ; ; 0.800 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[2] ; dpm_dec_reg_rdata_LED_2 ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.700 ns ; ; 0.800 ns ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[12] ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[14] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.700 ns ; ; 0.800 ns ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[11] ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[13] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.700 ns ; ; 0.800 ns ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[10] ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[12] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.700 ns ; ; 0.800 ns ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[9] ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[11] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.700 ns ; ; 0.800 ns ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[8] ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[10] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.700 ns ; ; 0.800 ns ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[5] ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[7] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.700 ns ; ; 0.800 ns ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[4] ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[6] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.700 ns ; ; 0.800 ns ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[3] ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[5] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.700 ns ; ; 0.800 ns ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[2] ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[4] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.700 ns ; ; 0.800 ns ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[1] ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[3] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.700 ns ; ; 0.800 ns ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[0] ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[2] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.700 ns ; ; 0.800 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_sr:wr_rdn_FF|REG ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_sr:wr_rdn_FF|REG ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.700 ns ; ; 0.800 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MS_PARK ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MS_PARK ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.700 ns ; ; 0.800 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lm_adr_ack_R ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lm_adr_ack_R ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.700 ns ; ; 0.800 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MS_ENA ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|dac_cyc_strobe ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.700 ns ; ; 0.800 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|cfg_cyc ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|cfg_cyc ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.700 ns ; ; 0.800 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[1] ; dpm_dec_reg_rdata_CNF_1 ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.700 ns ; ; 0.800 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[2] ; dpm_dec_reg_rdata_CNF_2 ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.700 ns ; ; 0.800 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[4] ; dpm_dec_reg_rdata_CNF_4 ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.700 ns ; ; 0.800 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[6] ; dpm_dec_reg_rdata_CNF_6 ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.700 ns ; ; 0.800 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|no_op_reg[6] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_END ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.700 ns ; ; 0.800 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LW_WAIT ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LW_WAIT ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.700 ns ; ; 0.800 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[9] ; dpm_dec_reg_rdata_LED_9 ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.700 ns ; ; 0.800 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|perr_rep_setR ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|stat_reg[8] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.700 ns ; ; 0.800 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|tabrt_set ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|pcimt32_sr:$00213|REG ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.700 ns ; ; 0.800 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|perr_det_setR_r3 ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|pcimt32_sr:$00219|REG ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.700 ns ; ; 0.800 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_WAIT ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_WAIT ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.700 ns ; ; 0.800 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MS_TAR ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|perr_rep_setR ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.700 ns ; ; 0.800 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:devsel_cntr|alt_counter_f10ke:wysi_counter|q[0] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:devsel_cntr|alt_counter_f10ke:wysi_counter|q[2] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.700 ns ; ; 0.800 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MS_ENA ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|adr_phase_end ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.700 ns ; ; 0.800 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[7] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.700 ns ; ; 0.800 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[4] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[6] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.700 ns ; ; 0.800 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[3] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[5] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.700 ns ; ; 0.800 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[2] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[4] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.700 ns ; ; 0.800 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[3] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.700 ns ; ; 0.800 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[0] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[2] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.700 ns ; ; 0.900 ns ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[12] ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|q[15] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.800 ns ; ; 0.900 ns ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[11] ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[14] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.800 ns ; ; 0.900 ns ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[10] ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[13] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.800 ns ; ; 0.900 ns ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[9] ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[12] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.800 ns ; ; 0.900 ns ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[8] ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[11] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.800 ns ; ; 0.900 ns ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[4] ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[7] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.800 ns ; ; 0.900 ns ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[3] ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[6] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.800 ns ; ; 0.900 ns ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[2] ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[5] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.800 ns ; ; 0.900 ns ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[1] ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[4] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.800 ns ; ; 0.900 ns ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[0] ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[3] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.800 ns ; ; 0.900 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|TS_DISC ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|TS_DISC ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.800 ns ; ; 0.900 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_LXFR ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_LXFR ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.800 ns ; ; 0.900 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|perr_det_setR_r1 ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|pcimt32_sr:$00219|REG ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.800 ns ; ; 0.900 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_WAIT ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_PXFR_r2 ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.800 ns ; ; 0.900 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_sr:burst_trans|REG ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_sr:burst_trans|REG ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.800 ns ; ; 0.900 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|TS_ADR_CLMD ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|trg_OR_advance ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.800 ns ; ; 0.900 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[4] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[7] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.800 ns ; ; 0.900 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[3] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[6] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.800 ns ; ; 0.900 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[2] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[5] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.800 ns ; ; 0.900 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[4] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.800 ns ; ; 0.900 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[0] ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[3] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.800 ns ; ; 1.000 ns ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[11] ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|q[15] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.900 ns ; ; 1.000 ns ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[10] ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[14] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.900 ns ; ; 1.000 ns ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[9] ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[13] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.900 ns ; ; 1.000 ns ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[8] ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[12] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.900 ns ; ; 1.000 ns ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[3] ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[7] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.900 ns ; ; 1.000 ns ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[2] ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[6] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.900 ns ; ; 1.000 ns ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[1] ; lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[5] ; pci_clk ; pci_clk ; 0.000 ns ; -0.100 ns ; 0.900 ns ; ; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; +-----------------------------------------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+ +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; tsu ; +-----------------------------------------+-----------------------------------------------------+------------+--------------+-------------------------------------------------------------------------------+----------+ ; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ; +-----------------------------------------+-----------------------------------------------------+------------+--------------+-------------------------------------------------------------------------------+----------+ ; 3.800 ns ; 1.500 ns ; -2.300 ns ; DES_DATA[0] ; dpm_ni2f_reg_des_data_r_0 ; DES_CLK ; ; 3.800 ns ; 1.500 ns ; -2.300 ns ; DES_DATA[9] ; dpm_ni2f_reg_des_data_r_9 ; DES_CLK ; ; 3.800 ns ; 1.500 ns ; -2.300 ns ; DES_DATA[10] ; dpm_ni2f_reg_des_data_r_10 ; DES_CLK ; ; 3.800 ns ; 1.500 ns ; -2.300 ns ; DES_DATA[11] ; dpm_ni2f_reg_des_data_r_11 ; DES_CLK ; ; 3.900 ns ; 1.500 ns ; -2.400 ns ; DES_DATA[8] ; dpm_ni2f_reg_des_data_r_8 ; DES_CLK ; ; 3.900 ns ; 1.500 ns ; -2.400 ns ; DES_DATA[12] ; dpm_ni2f_reg_des_data_r_12 ; DES_CLK ; ; 3.900 ns ; 1.500 ns ; -2.400 ns ; DES_DATA[13] ; dpm_ni2f_reg_des_data_r_13 ; DES_CLK ; ; 4.000 ns ; 1.500 ns ; -2.500 ns ; DES_DATA[7] ; dpm_ni2f_reg_des_data_r_7 ; DES_CLK ; ; 4.000 ns ; 1.500 ns ; -2.500 ns ; DES_DATA[14] ; dpm_ni2f_reg_des_data_r_14 ; DES_CLK ; ; 4.100 ns ; 1.500 ns ; -2.600 ns ; DES_DATA[15] ; dpm_ni2f_reg_des_data_r_15 ; DES_CLK ; ; 4.200 ns ; 1.500 ns ; -2.700 ns ; DES_DATA[4] ; dpm_ni2f_reg_des_data_r_4 ; DES_CLK ; ; 4.200 ns ; 1.500 ns ; -2.700 ns ; DES_DATA[5] ; dpm_ni2f_reg_des_data_r_5 ; DES_CLK ; ; 4.200 ns ; 1.500 ns ; -2.700 ns ; DES_DATA[6] ; dpm_ni2f_reg_des_data_r_6 ; DES_CLK ; ; 4.300 ns ; 1.500 ns ; -2.800 ns ; DES_DATA[3] ; dpm_ni2f_reg_des_data_r_3 ; DES_CLK ; ; 4.400 ns ; 1.500 ns ; -2.900 ns ; DES_EN ; dpm_ni2f_reg_des_en_r ; DES_CLK ; ; 4.500 ns ; 1.500 ns ; -3.000 ns ; DES_DATA[2] ; dpm_ni2f_reg_des_data_r_2 ; DES_CLK ; ; 4.600 ns ; 1.500 ns ; -3.100 ns ; DES_DATA[1] ; dpm_ni2f_reg_des_data_r_1 ; DES_CLK ; ; 5.500 ns ; 1.500 ns ; -4.000 ns ; DES_ER ; dpm_ni2f_reg_des_er_r ; DES_CLK ; ; N/A ; None ; 8.300 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[6] ; pci_clk ; ; N/A ; None ; 8.100 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[6] ; pci_clk ; ; N/A ; None ; 7.600 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[31] ; pci_clk ; ; N/A ; None ; 7.400 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[21] ; pci_clk ; ; N/A ; None ; 7.400 ns ; pci_cben[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|cben_ir_address[1] ; pci_clk ; ; N/A ; None ; 7.300 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[4] ; pci_clk ; ; N/A ; None ; 7.300 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[31] ; pci_clk ; ; N/A ; None ; 7.200 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[4] ; pci_clk ; ; N/A ; None ; 7.200 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[21] ; pci_clk ; ; N/A ; None ; 7.100 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[16] ; pci_clk ; ; N/A ; None ; 7.100 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[17] ; pci_clk ; ; N/A ; None ; 7.100 ns ; pci_cben[0] ; pci_contr:pci|pci_mt32:pci_mt32_inst|cben_ir_address[0] ; pci_clk ; ; N/A ; None ; 7.000 ns ; pci_cben[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|par_or ; pci_clk ; ; N/A ; None ; 6.900 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[16] ; pci_clk ; ; N/A ; None ; 6.900 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[17] ; pci_clk ; ; N/A ; None ; 6.800 ns ; pci_cben[0] ; pci_contr:pci|pci_mt32:pci_mt32_inst|par_or ; pci_clk ; ; N/A ; None ; 6.600 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[29] ; pci_clk ; ; N/A ; None ; 6.500 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[2] ; pci_clk ; ; N/A ; None ; 6.400 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[2] ; pci_clk ; ; N/A ; None ; 6.400 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[0] ; pci_clk ; ; N/A ; None ; 6.400 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[29] ; pci_clk ; ; N/A ; None ; 6.300 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[3] ; pci_clk ; ; N/A ; None ; 6.300 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[9] ; pci_clk ; ; N/A ; None ; 6.300 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[0] ; pci_clk ; ; N/A ; None ; 6.300 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[10] ; pci_clk ; ; N/A ; None ; 6.200 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[10] ; pci_clk ; ; N/A ; None ; 6.200 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[13] ; pci_clk ; ; N/A ; None ; 6.200 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[25] ; pci_clk ; ; N/A ; None ; 6.200 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[9] ; pci_clk ; ; N/A ; None ; 6.100 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[12] ; pci_clk ; ; N/A ; None ; 6.100 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[14] ; pci_clk ; ; N/A ; None ; 6.100 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[15] ; pci_clk ; ; N/A ; None ; 6.100 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_PXFR_r2 ; pci_clk ; ; N/A ; None ; 6.100 ns ; pci_cben[3] ; pci_contr:pci|pci_mt32:pci_mt32_inst|cben_ir_address[3] ; pci_clk ; ; N/A ; None ; 6.100 ns ; pci_framen ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_PXFR_r2 ; pci_clk ; ; N/A ; None ; 6.100 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[3] ; pci_clk ; ; N/A ; None ; 6.100 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[25] ; pci_clk ; ; N/A ; None ; 6.100 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_DXFR_32_r[3] ; pci_clk ; ; N/A ; None ; 6.000 ns ; pci_stopn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|WAIT_WAIT32 ; pci_clk ; ; N/A ; None ; 6.000 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[13] ; pci_clk ; ; N/A ; None ; 6.000 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[14] ; pci_clk ; ; N/A ; None ; 6.000 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[15] ; pci_clk ; ; N/A ; None ; 6.000 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|irdy_or_not ; pci_clk ; ; N/A ; None ; 5.900 ns ; pci_ad[31] ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[31] ; pci_clk ; ; N/A ; None ; 5.900 ns ; pci_ad[31] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[31] ; pci_clk ; ; N/A ; None ; 5.900 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[1] ; pci_clk ; ; N/A ; None ; 5.900 ns ; pci_stopn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|irdy_or_not ; pci_clk ; ; N/A ; None ; 5.800 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[7] ; pci_clk ; ; N/A ; None ; 5.800 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[12] ; pci_clk ; ; N/A ; None ; 5.800 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_DXFR_r1 ; pci_clk ; ; N/A ; None ; 5.700 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[11] ; pci_clk ; ; N/A ; None ; 5.700 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LW_DONE ; pci_clk ; ; N/A ; None ; 5.700 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LW_LXFR ; pci_clk ; ; N/A ; None ; 5.700 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LW_WAIT ; pci_clk ; ; N/A ; None ; 5.700 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_PXFR_32_r2 ; pci_clk ; ; N/A ; None ; 5.700 ns ; pci_framen ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_PXFR_32_r2 ; pci_clk ; ; N/A ; None ; 5.700 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[1] ; pci_clk ; ; N/A ; None ; 5.600 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[24] ; pci_clk ; ; N/A ; None ; 5.600 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[27] ; pci_clk ; ; N/A ; None ; 5.600 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[28] ; pci_clk ; ; N/A ; None ; 5.600 ns ; pci_cben[3] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_cben_IR_data[3] ; pci_clk ; ; N/A ; None ; 5.600 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[7] ; pci_clk ; ; N/A ; None ; 5.600 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[11] ; pci_clk ; ; N/A ; None ; 5.600 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[27] ; pci_clk ; ; N/A ; None ; 5.500 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[23] ; pci_clk ; ; N/A ; None ; 5.500 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[26] ; pci_clk ; ; N/A ; None ; 5.500 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_ack_R_r4 ; pci_clk ; ; N/A ; None ; 5.500 ns ; pci_stopn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_DXFR_r4 ; pci_clk ; ; N/A ; None ; 5.500 ns ; pci_stopn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_WAIT_32_r[2] ; pci_clk ; ; N/A ; None ; 5.500 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[24] ; pci_clk ; ; N/A ; None ; 5.500 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[26] ; pci_clk ; ; N/A ; None ; 5.500 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[28] ; pci_clk ; ; N/A ; None ; 5.400 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[22] ; pci_clk ; ; N/A ; None ; 5.400 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[30] ; pci_clk ; ; N/A ; None ; 5.400 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|trdy_OR_NOT ; pci_clk ; ; N/A ; None ; 5.400 ns ; pci_stopn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_LAST_r[1] ; pci_clk ; ; N/A ; None ; 5.400 ns ; pci_stopn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_WAIT ; pci_clk ; ; N/A ; None ; 5.400 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[22] ; pci_clk ; ; N/A ; None ; 5.400 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[23] ; pci_clk ; ; N/A ; None ; 5.400 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[30] ; pci_clk ; ; N/A ; None ; 5.300 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[5] ; pci_clk ; ; N/A ; None ; 5.300 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[20] ; pci_clk ; ; N/A ; None ; 5.300 ns ; pci_stopn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_LAST_r[3] ; pci_clk ; ; N/A ; None ; 5.300 ns ; pci_stopn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_WAIT_32_r[1] ; pci_clk ; ; N/A ; None ; 5.300 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[20] ; pci_clk ; ; N/A ; None ; 5.300 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_LAST_r[3] ; pci_clk ; ; N/A ; None ; 5.300 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_DXFR_r4 ; pci_clk ; ; N/A ; None ; 5.300 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_WAIT_32_r[2] ; pci_clk ; ; N/A ; None ; 5.300 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_WAIT ; pci_clk ; ; N/A ; None ; 5.200 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[8] ; pci_clk ; ; N/A ; None ; 5.200 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|devsel_OR_not ; pci_clk ; ; N/A ; None ; 5.200 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|stop_OR_NOT ; pci_clk ; ; N/A ; None ; 5.200 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_ack_R_r3 ; pci_clk ; ; N/A ; None ; 5.200 ns ; pci_devseln ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_HOLD ; pci_clk ; ; N/A ; None ; 5.200 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|WAIT_WAIT32 ; pci_clk ; ; N/A ; None ; 5.200 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_LAST_r[1] ; pci_clk ; ; N/A ; None ; 5.200 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_WAIT_32_r[1] ; pci_clk ; ; N/A ; None ; 5.100 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[18] ; pci_clk ; ; N/A ; None ; 5.100 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[19] ; pci_clk ; ; N/A ; None ; 5.100 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_WAIT_32 ; pci_clk ; ; N/A ; None ; 5.100 ns ; pci_framen ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|stop_OR_NOT ; pci_clk ; ; N/A ; None ; 5.100 ns ; pci_devseln ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_DXFR_32_r[2] ; pci_clk ; ; N/A ; None ; 5.100 ns ; pci_stopn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|DXFR_write ; pci_clk ; ; N/A ; None ; 5.000 ns ; pci_devseln ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|irdy_or_not ; pci_clk ; ; N/A ; None ; 5.000 ns ; pci_stopn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_DXFR_r1 ; pci_clk ; ; N/A ; None ; 5.000 ns ; pci_stopn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_DXFR_32_r[3] ; pci_clk ; ; N/A ; None ; 5.000 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[5] ; pci_clk ; ; N/A ; None ; 5.000 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[8] ; pci_clk ; ; N/A ; None ; 5.000 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[18] ; pci_clk ; ; N/A ; None ; 5.000 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[19] ; pci_clk ; ; N/A ; None ; 5.000 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_DXFR_32_r[1] ; pci_clk ; ; N/A ; None ; 4.900 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|WAIT_wait32 ; pci_clk ; ; N/A ; None ; 4.900 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_WAIT ; pci_clk ; ; N/A ; None ; 4.900 ns ; pci_ad[0] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[0] ; pci_clk ; ; N/A ; None ; 4.900 ns ; pci_ad[0] ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[0] ; pci_clk ; ; N/A ; None ; 4.900 ns ; pci_framen ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|frame_IR ; pci_clk ; ; N/A ; None ; 4.900 ns ; pci_stopn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|frame_or_not ; pci_clk ; ; N/A ; None ; 4.900 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_END_r[1] ; pci_clk ; ; N/A ; None ; 4.900 ns ; pci_ad[4] ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[4] ; pci_clk ; ; N/A ; None ; 4.800 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_sr:burst_trans|REG ; pci_clk ; ; N/A ; None ; 4.800 ns ; pci_framen ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|adoe ; pci_clk ; ; N/A ; None ; 4.800 ns ; pci_framen ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|devsel_OR_not ; pci_clk ; ; N/A ; None ; 4.800 ns ; pci_framen ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_WAIT_32 ; pci_clk ; ; N/A ; None ; 4.800 ns ; pci_stopn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|cbe_oer_not ; pci_clk ; ; N/A ; None ; 4.800 ns ; pci_ad[14] ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[14] ; pci_clk ; ; N/A ; None ; 4.800 ns ; pci_ad[6] ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[6] ; pci_clk ; ; N/A ; None ; 4.800 ns ; pci_ad[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[5] ; pci_clk ; ; N/A ; None ; 4.700 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_ack_R_r2 ; pci_clk ; ; N/A ; None ; 4.700 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|perr_vldR ; pci_clk ; ; N/A ; None ; 4.700 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|idle_reg ; pci_clk ; ; N/A ; None ; 4.700 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|park ; pci_clk ; ; N/A ; None ; 4.700 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_LXFR ; pci_clk ; ; N/A ; None ; 4.700 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_PXFR_r1 ; pci_clk ; ; N/A ; None ; 4.700 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_PXFR_32_r1 ; pci_clk ; ; N/A ; None ; 4.700 ns ; pci_framen ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_LXFR ; pci_clk ; ; N/A ; None ; 4.700 ns ; pci_framen ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_PXFR_r1 ; pci_clk ; ; N/A ; None ; 4.700 ns ; pci_stopn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|ad_oer ; pci_clk ; ; N/A ; None ; 4.700 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_LXFR_r[1] ; pci_clk ; ; N/A ; None ; 4.700 ns ; pci_ad[15] ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[15] ; pci_clk ; ; N/A ; None ; 4.700 ns ; pci_ad[13] ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[13] ; pci_clk ; ; N/A ; None ; 4.700 ns ; pci_ad[2] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[2] ; pci_clk ; ; N/A ; None ; 4.700 ns ; pci_ad[2] ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[2] ; pci_clk ; ; N/A ; None ; 4.600 ns ; pci_perrn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|perr_rep_setR ; pci_clk ; ; N/A ; None ; 4.600 ns ; pci_framen ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|TS_TURN_AR ; pci_clk ; ; N/A ; None ; 4.600 ns ; pci_framen ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_ack_R_r4 ; pci_clk ; ; N/A ; None ; 4.600 ns ; pci_framen ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_WAIT ; pci_clk ; ; N/A ; None ; 4.600 ns ; pci_framen ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_PXFR_32_r1 ; pci_clk ; ; N/A ; None ; 4.600 ns ; pci_stopn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_PXFR_r1 ; pci_clk ; ; N/A ; None ; 4.600 ns ; pci_ad[12] ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[12] ; pci_clk ; ; N/A ; None ; 4.600 ns ; pci_ad[11] ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[11] ; pci_clk ; ; N/A ; None ; 4.500 ns ; pci_framen ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_ack_R_r3 ; pci_clk ; ; N/A ; None ; 4.500 ns ; pci_framen ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_ack_R_r1 ; pci_clk ; ; N/A ; None ; 4.500 ns ; pci_stopn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MS_TAR ; pci_clk ; ; N/A ; None ; 4.500 ns ; pci_stopn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_END ; pci_clk ; ; N/A ; None ; 4.500 ns ; pci_stopn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_PXFR_r2 ; pci_clk ; ; N/A ; None ; 4.400 ns ; pci_framen ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|trdy_OR_NOT ; pci_clk ; ; N/A ; None ; 4.400 ns ; pci_framen ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|park ; pci_clk ; ; N/A ; None ; 4.400 ns ; pci_framen ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_DONE ; pci_clk ; ; N/A ; None ; 4.400 ns ; pci_stopn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_DXFR_32_r[1] ; pci_clk ; ; N/A ; None ; 4.300 ns ; pci_gntn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|latcntr_toR ; pci_clk ; ; N/A ; None ; 4.300 ns ; pci_stopn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MS_DXFR ; pci_clk ; ; N/A ; None ; 4.300 ns ; pci_stopn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LLXFR_r1 ; pci_clk ; ; N/A ; None ; 4.300 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_PXFR_r2 ; pci_clk ; ; N/A ; None ; 4.200 ns ; pci_ad[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[1] ; pci_clk ; ; N/A ; None ; 4.200 ns ; pci_framen ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_sr:burst_trans|REG ; pci_clk ; ; N/A ; None ; 4.200 ns ; pci_stopn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LWAIT ; pci_clk ; ; N/A ; None ; 4.200 ns ; pci_stopn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_LXFR_r[1] ; pci_clk ; ; N/A ; None ; 4.200 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|frame_or_not ; pci_clk ; ; N/A ; None ; 4.200 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|DXFR_write ; pci_clk ; ; N/A ; None ; 4.200 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_END ; pci_clk ; ; N/A ; None ; 4.100 ns ; pci_framen ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|WAIT_wait32 ; pci_clk ; ; N/A ; None ; 4.100 ns ; pci_framen ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|idle_reg ; pci_clk ; ; N/A ; None ; 4.100 ns ; pci_devseln ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|devsel_toR ; pci_clk ; ; N/A ; None ; 4.100 ns ; pci_stopn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_HOLD ; pci_clk ; ; N/A ; None ; 4.100 ns ; pci_stopn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_DXFR_32_r[2] ; pci_clk ; ; N/A ; None ; 4.100 ns ; pci_stopn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_END_r[2] ; pci_clk ; ; N/A ; None ; 4.100 ns ; pci_ad[8] ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[8] ; pci_clk ; ; N/A ; None ; 4.100 ns ; pci_ad[8] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[8] ; pci_clk ; ; N/A ; None ; 4.000 ns ; pci_devseln ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|tabrt_set ; pci_clk ; ; N/A ; None ; 4.000 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LWAIT ; pci_clk ; ; N/A ; None ; 3.900 ns ; pci_ad[30] ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[30] ; pci_clk ; ; N/A ; None ; 3.900 ns ; pci_framen ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|TS_DISC ; pci_clk ; ; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; +-----------------------------------------+-----------------------------------------------------+------------+--------------+-------------------------------------------------------------------------------+----------+ +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; tco ; +-----------------------------------------+-----------------------------------------------------+------------+------------------------------------------------------------------+-------------+------------+ ; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ; +-----------------------------------------+-----------------------------------------------------+------------+------------------------------------------------------------------+-------------+------------+ ; N/A ; None ; 19.400 ns ; sg_reg_mx_q ; R7S[1] ; pci_clk ; ; N/A ; None ; 19.400 ns ; sg_reg_mx_q ; R7S[4] ; pci_clk ; ; N/A ; None ; 19.300 ns ; dpm_dec_reg_rdata_LED_3 ; R7S[1] ; pci_clk ; ; N/A ; None ; 19.300 ns ; dpm_dec_reg_rdata_LED_3 ; R7S[4] ; pci_clk ; ; N/A ; None ; 19.300 ns ; sg_reg_mx_q ; R7S[5] ; pci_clk ; ; N/A ; None ; 19.200 ns ; dpm_dec_reg_rdata_LED_3 ; R7S[5] ; pci_clk ; ; N/A ; None ; 18.900 ns ; dpm_dec_reg_rdata_LED_2 ; R7S[1] ; pci_clk ; ; N/A ; None ; 18.900 ns ; dpm_dec_reg_rdata_LED_2 ; R7S[4] ; pci_clk ; ; N/A ; None ; 18.800 ns ; dpm_dec_reg_rdata_LED_6 ; R7S[1] ; pci_clk ; ; N/A ; None ; 18.800 ns ; dpm_dec_reg_rdata_LED_6 ; R7S[4] ; pci_clk ; ; N/A ; None ; 18.800 ns ; dpm_dec_reg_rdata_LED_2 ; R7S[5] ; pci_clk ; ; N/A ; None ; 18.700 ns ; dpm_dec_reg_rdata_LED_6 ; R7S[5] ; pci_clk ; ; N/A ; None ; 18.200 ns ; dpm_dec_reg_rdata_LED_7 ; R7S[1] ; pci_clk ; ; N/A ; None ; 18.200 ns ; dpm_dec_reg_rdata_LED_7 ; R7S[4] ; pci_clk ; ; N/A ; None ; 18.100 ns ; dpm_dec_reg_rdata_LED_7 ; R7S[5] ; pci_clk ; ; N/A ; None ; 18.000 ns ; dpm_ni2f_reg_we_n ; SRAM_IO[15] ; DES_CLK ; ; N/A ; None ; 18.000 ns ; dpm_ni2f_reg_we_n ; SRAM_IO[14] ; DES_CLK ; ; N/A ; None ; 18.000 ns ; dpm_ni2f_reg_we_n ; SRAM_IO[2] ; DES_CLK ; ; N/A ; None ; 18.000 ns ; dpm_ni2f_reg_we_n ; SRAM_IO[1] ; DES_CLK ; ; N/A ; None ; 18.000 ns ; dpm_ni2f_reg_we_n ; SRAM_IO[0] ; DES_CLK ; ; N/A ; None ; 17.700 ns ; dpm_ni2f_reg_we_n ; SRAM_IO[13] ; DES_CLK ; ; N/A ; None ; 17.700 ns ; dpm_ni2f_reg_we_n ; SRAM_IO[3] ; DES_CLK ; ; N/A ; None ; 17.600 ns ; dpm_ni2f_reg_we_n ; SRAM_IO[12] ; DES_CLK ; ; N/A ; None ; 17.600 ns ; dpm_dec_reg_rdata_LED_3 ; R7S[2] ; pci_clk ; ; N/A ; None ; 17.500 ns ; dpm_ni2f_reg_we_n ; SRAM_IO[4] ; DES_CLK ; ; N/A ; None ; 17.400 ns ; dpm_ni2f_reg_we_n ; SRAM_IO[11] ; DES_CLK ; ; N/A ; None ; 17.400 ns ; dpm_ni2f_reg_we_n ; SRAM_IO[5] ; DES_CLK ; ; N/A ; None ; 17.300 ns ; dpm_ni2f_reg_we_n ; SRAM_IO[10] ; DES_CLK ; ; N/A ; None ; 17.300 ns ; dpm_dec_reg_rdata_LED_4 ; R7S[1] ; pci_clk ; ; N/A ; None ; 17.300 ns ; sg_reg_mx_q ; R7S[2] ; pci_clk ; ; N/A ; None ; 17.200 ns ; sg_reg_mx_q ; R7S[6] ; pci_clk ; ; N/A ; None ; 17.100 ns ; dpm_ni2f_reg_we_n ; SRAM_IO[7] ; DES_CLK ; ; N/A ; None ; 17.100 ns ; dpm_ni2f_reg_we_n ; SRAM_IO[6] ; DES_CLK ; ; N/A ; None ; 17.100 ns ; dpm_dec_reg_rdata_LED_0 ; R7S[1] ; pci_clk ; ; N/A ; None ; 17.100 ns ; dpm_dec_reg_rdata_LED_4 ; R7S[4] ; pci_clk ; ; N/A ; None ; 17.100 ns ; dpm_dec_reg_rdata_LED_3 ; R7S[6] ; pci_clk ; ; N/A ; None ; 17.000 ns ; dpm_ni2f_reg_we_n ; SRAM_IO[9] ; DES_CLK ; ; N/A ; None ; 17.000 ns ; dpm_dec_reg_rdata_LED_4 ; R7S[5] ; pci_clk ; ; N/A ; None ; 16.900 ns ; dpm_dec_reg_rdata_LED_1 ; R7S[2] ; pci_clk ; ; N/A ; None ; 16.900 ns ; dpm_dec_reg_rdata_LED_0 ; R7S[4] ; pci_clk ; ; N/A ; None ; 16.800 ns ; dpm_dec_reg_rdata_LED_2 ; R7S[2] ; pci_clk ; ; N/A ; None ; 16.800 ns ; dpm_dec_reg_rdata_LED_0 ; R7S[5] ; pci_clk ; ; N/A ; None ; 16.800 ns ; dpm_dec_reg_rdata_LED_3 ; R7S[7] ; pci_clk ; ; N/A ; None ; 16.700 ns ; dpm_ni2f_reg_we_n ; SRAM_IO[8] ; DES_CLK ; ; N/A ; None ; 16.700 ns ; dpm_dec_reg_rdata_LED_6 ; R7S[2] ; pci_clk ; ; N/A ; None ; 16.700 ns ; dpm_dec_reg_rdata_LED_2 ; R7S[6] ; pci_clk ; ; N/A ; None ; 16.600 ns ; dpm_dec_reg_rdata_LED_3 ; R7S[3] ; pci_clk ; ; N/A ; None ; 16.600 ns ; dpm_dec_reg_rdata_LED_6 ; R7S[6] ; pci_clk ; ; N/A ; None ; 16.600 ns ; sg_reg_mx_q ; R7S[7] ; pci_clk ; ; N/A ; None ; 16.500 ns ; dpm_dec_reg_rdata_LED_1 ; R7S[1] ; pci_clk ; ; N/A ; None ; 16.500 ns ; dpm_dec_reg_rdata_LED_5 ; R7S[2] ; pci_clk ; ; N/A ; None ; 16.500 ns ; dpm_dec_reg_rdata_LED_7 ; R7S[2] ; pci_clk ; ; N/A ; None ; 16.300 ns ; dpm_dec_reg_rdata_LED_4 ; R7S[2] ; pci_clk ; ; N/A ; None ; 16.300 ns ; dpm_ni2f_reg_we_n ; KCLK ; DES_CLK ; ; N/A ; None ; 16.200 ns ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[5] ; SRAM_IO[13] ; DES_CLK ; ; N/A ; None ; 16.100 ns ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[3] ; SRAM_IO[11] ; DES_CLK ; ; N/A ; None ; 16.100 ns ; dpm_dec_reg_rdata_LED_5 ; R7S[1] ; pci_clk ; ; N/A ; None ; 16.100 ns ; dpm_dec_reg_rdata_LED_0 ; R7S[2] ; pci_clk ; ; N/A ; None ; 16.100 ns ; dpm_dec_reg_rdata_LED_1 ; R7S[7] ; pci_clk ; ; N/A ; None ; 16.100 ns ; dpm_dec_reg_rdata_LED_2 ; R7S[7] ; pci_clk ; ; N/A ; None ; 16.000 ns ; dpm_dec_reg_rdata_LED_1 ; R7S[4] ; pci_clk ; ; N/A ; None ; 16.000 ns ; dpm_dec_reg_rdata_LED_7 ; R7S[6] ; pci_clk ; ; N/A ; None ; 16.000 ns ; dpm_dec_reg_rdata_LED_6 ; R7S[7] ; pci_clk ; ; N/A ; None ; 15.900 ns ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[4] ; SRAM_IO[12] ; DES_CLK ; ; N/A ; None ; 15.900 ns ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[4] ; SRAM_IO[4] ; DES_CLK ; ; N/A ; None ; 15.900 ns ; dpm_dec_reg_rdata_LED_1 ; R7S[5] ; pci_clk ; ; N/A ; None ; 15.800 ns ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[7] ; SRAM_IO[15] ; DES_CLK ; ; N/A ; None ; 15.800 ns ; sg_reg_mx_q ; R7S[3] ; pci_clk ; ; N/A ; None ; 15.700 ns ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[0] ; SRAM_IO[8] ; DES_CLK ; ; N/A ; None ; 15.700 ns ; dpm_dec_reg_rdata_LED_5 ; R7S[7] ; pci_clk ; ; N/A ; None ; 15.700 ns ; dpm_dec_reg_rdata_LED_7 ; R7S[7] ; pci_clk ; ; N/A ; None ; 15.600 ns ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[2] ; SRAM_IO[10] ; DES_CLK ; ; N/A ; None ; 15.600 ns ; dpm_dec_reg_rdata_LED_5 ; R7S[4] ; pci_clk ; ; N/A ; None ; 15.500 ns ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[1] ; SRAM_IO[9] ; DES_CLK ; ; N/A ; None ; 15.500 ns ; dpm_dec_reg_rdata_LED_7 ; R7S[3] ; pci_clk ; ; N/A ; None ; 15.500 ns ; dpm_dec_reg_rdata_LED_5 ; R7S[5] ; pci_clk ; ; N/A ; None ; 15.400 ns ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[5] ; SRAM_IO[5] ; DES_CLK ; ; N/A ; None ; 15.200 ns ; dpm_dec_reg_rdata_LED_2 ; R7S[3] ; pci_clk ; ; N/A ; None ; 15.100 ns ; dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[6] ; SRAM_IO[14] ; DES_CLK ; ; N/A ; None ; 15.100 ns ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[6] ; SRAM_IO[6] ; DES_CLK ; ; N/A ; None ; 15.100 ns ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[3] ; SRAM_IO[3] ; DES_CLK ; ; N/A ; None ; 15.100 ns ; dpm_dec_reg_rdata_LED_6 ; R7S[3] ; pci_clk ; ; N/A ; None ; 14.900 ns ; dpm_dec_reg_rdata_LED_1 ; R7S[6] ; pci_clk ; ; N/A ; None ; 14.900 ns ; dpm_dec_reg_rdata_LED_4 ; R7S[6] ; pci_clk ; ; N/A ; None ; 14.700 ns ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[7] ; SRAM_IO[7] ; DES_CLK ; ; N/A ; None ; 14.700 ns ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[0] ; SRAM_IO[0] ; DES_CLK ; ; N/A ; None ; 14.700 ns ; dpm_dec_reg_rdata_LED_0 ; R7S[6] ; pci_clk ; ; N/A ; None ; 14.500 ns ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[2] ; SRAM_IO[2] ; DES_CLK ; ; N/A ; None ; 14.500 ns ; dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[1] ; SRAM_IO[1] ; DES_CLK ; ; N/A ; None ; 14.500 ns ; dpm_dec_reg_rdata_LED_5 ; R7S[6] ; pci_clk ; ; N/A ; None ; 14.400 ns ; dpm_ni2f_reg_addr_7 ; SRAM_AD[7] ; DES_CLK ; ; N/A ; None ; 14.400 ns ; dpm_dec_reg_rdata_LED_4 ; R7S[7] ; pci_clk ; ; N/A ; None ; 14.200 ns ; dpm_ni2f_reg_re_n ; SRAM_OEn ; DES_CLK ; ; N/A ; None ; 14.200 ns ; dpm_ni2f_reg_clk_sram_i ; SRAM_CLK ; DES_CLK ; ; N/A ; None ; 14.200 ns ; dpm_dec_reg_rdata_LED_0 ; R7S[7] ; pci_clk ; ; N/A ; None ; 14.100 ns ; dpm_ni2f_reg_addr_8 ; SRAM_AD[8] ; DES_CLK ; ; N/A ; None ; 14.000 ns ; dpm_ni2f_reg_ce_n ; SRAM_CEn ; DES_CLK ; ; N/A ; None ; 13.800 ns ; dpm_dec_reg_rdata_LED_4 ; R7S[3] ; pci_clk ; ; N/A ; None ; 13.800 ns ; dpm_ni2f_reg_ds_en_reg ; MCLK ; DES_CLK ; ; N/A ; None ; 13.700 ns ; dpm_dec_reg_rdata_LED_1 ; R7S[3] ; pci_clk ; ; N/A ; None ; 13.600 ns ; dpm_dec_reg_rdata_LED_0 ; R7S[3] ; pci_clk ; ; N/A ; None ; 13.500 ns ; dpm_ni2f_reg_addr_4 ; SRAM_AD[4] ; DES_CLK ; ; N/A ; None ; 13.500 ns ; dpm_ni2f_reg_not_empty ; KDAT ; DES_CLK ; ; N/A ; None ; 13.400 ns ; dpm_ni2f_reg_we_n~4 ; SRAM_IO[17] ; DES_CLK ; ; N/A ; None ; 13.300 ns ; dpm_ni2f_reg_addr_3 ; SRAM_AD[3] ; DES_CLK ; ; N/A ; None ; 13.300 ns ; dpm_dec_reg_rdata_LED_5 ; R7S[3] ; pci_clk ; ; N/A ; None ; 13.300 ns ; dpm_ni2f_reg_not_empty~2 ; LED_RED ; DES_CLK ; ; N/A ; None ; 13.300 ns ; dpm_ni2f_reg_not_empty~1 ; LED_GRN ; DES_CLK ; ; N/A ; None ; 13.200 ns ; dpm_ni2f_reg_addr_9 ; SRAM_AD[9] ; DES_CLK ; ; N/A ; None ; 13.200 ns ; dpm_ni2f_reg_addr_6 ; SRAM_AD[6] ; DES_CLK ; ; N/A ; None ; 13.100 ns ; dpm_ni2f_reg_we_n~3 ; SRAM_IO[16] ; DES_CLK ; ; N/A ; None ; 13.100 ns ; dpm_ni2f_reg_we_n~2 ; SRAM_BW2n ; DES_CLK ; ; N/A ; None ; 13.100 ns ; dpm_ni2f_reg_we_n~1 ; SRAM_BW1n ; DES_CLK ; ; N/A ; None ; 13.100 ns ; dpm_ni2f_reg_addr_17 ; SRAM_AD[17] ; DES_CLK ; ; N/A ; None ; 13.100 ns ; dpm_ni2f_reg_addr_16 ; SRAM_AD[16] ; DES_CLK ; ; N/A ; None ; 13.100 ns ; dpm_ni2f_reg_addr_15 ; SRAM_AD[15] ; DES_CLK ; ; N/A ; None ; 13.100 ns ; dpm_ni2f_reg_addr_14 ; SRAM_AD[14] ; DES_CLK ; ; N/A ; None ; 13.100 ns ; dpm_ni2f_reg_addr_13 ; SRAM_AD[13] ; DES_CLK ; ; N/A ; None ; 13.100 ns ; dpm_ni2f_reg_addr_12 ; SRAM_AD[12] ; DES_CLK ; ; N/A ; None ; 13.100 ns ; dpm_ni2f_reg_addr_11 ; SRAM_AD[11] ; DES_CLK ; ; N/A ; None ; 13.100 ns ; dpm_ni2f_reg_addr_10 ; SRAM_AD[10] ; DES_CLK ; ; N/A ; None ; 13.100 ns ; dpm_ni2f_reg_addr_2 ; SRAM_AD[2] ; DES_CLK ; ; N/A ; None ; 13.100 ns ; dpm_ni2f_reg_addr_1 ; SRAM_AD[1] ; DES_CLK ; ; N/A ; None ; 13.100 ns ; dpm_ni2f_reg_addr_0 ; SRAM_AD[0] ; DES_CLK ; ; N/A ; None ; 13.000 ns ; dpm_ni2f_reg_addr_5 ; SRAM_AD[5] ; DES_CLK ; ; N/A ; None ; 12.500 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|targ_oeR_reg ; pci_devseln ; pci_clk ; ; N/A ; None ; 12.500 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|targ_oeR_reg ; pci_stopn ; pci_clk ; ; N/A ; None ; 12.500 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|targ_oeR_reg ; pci_trdyn ; pci_clk ; ; N/A ; None ; 11.400 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|trdy_OR_NOT ; pci_trdyn ; pci_clk ; ; N/A ; None ; 11.300 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|ad_oer ; pci_ad[15] ; pci_clk ; ; N/A ; None ; 11.300 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|ad_oer ; pci_ad[14] ; pci_clk ; ; N/A ; None ; 11.300 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|ad_oer ; pci_ad[13] ; pci_clk ; ; N/A ; None ; 11.300 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|ad_oer ; pci_ad[12] ; pci_clk ; ; N/A ; None ; 11.200 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|ad_oer ; pci_ad[11] ; pci_clk ; ; N/A ; None ; 11.200 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|ad_oer ; pci_ad[10] ; pci_clk ; ; N/A ; None ; 11.200 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|ad_oer ; pci_ad[9] ; pci_clk ; ; N/A ; None ; 11.200 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|ad_oer ; pci_ad[8] ; pci_clk ; ; N/A ; None ; 11.200 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|ad_oer ; pci_ad[7] ; pci_clk ; ; N/A ; None ; 11.200 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|par_oeR ; pci_par ; pci_clk ; ; N/A ; None ; 11.100 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|irdy_or_not ; pci_irdyn ; pci_clk ; ; N/A ; None ; 11.100 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|ad_oer ; pci_ad[6] ; pci_clk ; ; N/A ; None ; 11.100 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|ad_oer ; pci_ad[5] ; pci_clk ; ; N/A ; None ; 11.100 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|ad_oer ; pci_ad[4] ; pci_clk ; ; N/A ; None ; 11.100 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|ad_oer ; pci_ad[3] ; pci_clk ; ; N/A ; None ; 11.000 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|ad_oer ; pci_ad[0] ; pci_clk ; ; N/A ; None ; 11.000 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|ad_oer ; pci_ad[1] ; pci_clk ; ; N/A ; None ; 11.000 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|ad_oer ; pci_ad[2] ; pci_clk ; ; N/A ; None ; 10.800 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|ad_oer ; pci_ad[16] ; pci_clk ; ; N/A ; None ; 10.700 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|ad_oer ; pci_ad[20] ; pci_clk ; ; N/A ; None ; 10.700 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|ad_oer ; pci_ad[21] ; pci_clk ; ; N/A ; None ; 10.700 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|ad_oer ; pci_ad[22] ; pci_clk ; ; N/A ; None ; 10.700 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|ad_oer ; pci_ad[23] ; pci_clk ; ; N/A ; None ; 10.700 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|ad_oer ; pci_ad[19] ; pci_clk ; ; N/A ; None ; 10.700 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|ad_oer ; pci_ad[18] ; pci_clk ; ; N/A ; None ; 10.700 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|ad_oer ; pci_ad[17] ; pci_clk ; ; N/A ; None ; 10.600 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|perr_oe_r ; pci_perrn ; pci_clk ; ; N/A ; None ; 10.600 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|ad_oer ; pci_ad[24] ; pci_clk ; ; N/A ; None ; 10.600 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|ad_oer ; pci_ad[25] ; pci_clk ; ; N/A ; None ; 10.500 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|ad_oer ; pci_ad[26] ; pci_clk ; ; N/A ; None ; 10.500 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|ad_oer ; pci_ad[27] ; pci_clk ; ; N/A ; None ; 10.400 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|ad_oer ; pci_ad[28] ; pci_clk ; ; N/A ; None ; 10.400 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|ad_oer ; pci_ad[29] ; pci_clk ; ; N/A ; None ; 10.400 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|ad_oer ; pci_ad[30] ; pci_clk ; ; N/A ; None ; 10.300 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|ad_oer ; pci_ad[31] ; pci_clk ; ; N/A ; None ; 10.000 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|cbe_oer_not ; pci_cben[1] ; pci_clk ; ; N/A ; None ; 10.000 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|cbe_oer_not ; pci_cben[0] ; pci_clk ; ; N/A ; None ; 10.000 ns ; sg_reg_mx_q ; R7S_mux ; pci_clk ; ; N/A ; None ; 9.700 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|cbe_oer_not ; pci_cben[2] ; pci_clk ; ; N/A ; None ; 9.600 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|cbe_oer_not ; pci_cben[3] ; pci_clk ; ; N/A ; None ; 9.500 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|adoe ; pci_ad[15] ; pci_clk ; ; N/A ; None ; 9.500 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|adoe ; pci_ad[14] ; pci_clk ; ; N/A ; None ; 9.500 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|adoe ; pci_ad[13] ; pci_clk ; ; N/A ; None ; 9.500 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|adoe ; pci_ad[12] ; pci_clk ; ; N/A ; None ; 9.400 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|adoe ; pci_ad[11] ; pci_clk ; ; N/A ; None ; 9.400 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|adoe ; pci_ad[10] ; pci_clk ; ; N/A ; None ; 9.400 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|adoe ; pci_ad[9] ; pci_clk ; ; N/A ; None ; 9.400 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|adoe ; pci_ad[8] ; pci_clk ; ; N/A ; None ; 9.400 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|adoe ; pci_ad[7] ; pci_clk ; ; N/A ; None ; 9.300 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|stop_OR_NOT ; pci_stopn ; pci_clk ; ; N/A ; None ; 9.300 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|adoe ; pci_ad[6] ; pci_clk ; ; N/A ; None ; 9.300 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|adoe ; pci_ad[5] ; pci_clk ; ; N/A ; None ; 9.300 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|adoe ; pci_ad[4] ; pci_clk ; ; N/A ; None ; 9.300 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|adoe ; pci_ad[3] ; pci_clk ; ; N/A ; None ; 9.200 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|adoe ; pci_ad[0] ; pci_clk ; ; N/A ; None ; 9.200 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|adoe ; pci_ad[1] ; pci_clk ; ; N/A ; None ; 9.200 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|adoe ; pci_ad[2] ; pci_clk ; ; N/A ; None ; 9.000 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[29] ; pci_ad[29] ; pci_clk ; ; N/A ; None ; 9.000 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|adoe ; pci_ad[16] ; pci_clk ; ; N/A ; None ; 8.900 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|adoe ; pci_ad[20] ; pci_clk ; ; N/A ; None ; 8.900 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|adoe ; pci_ad[21] ; pci_clk ; ; N/A ; None ; 8.900 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|adoe ; pci_ad[22] ; pci_clk ; ; N/A ; None ; 8.900 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|adoe ; pci_ad[23] ; pci_clk ; ; N/A ; None ; 8.900 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[30] ; pci_ad[30] ; pci_clk ; ; N/A ; None ; 8.900 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|adoe ; pci_ad[19] ; pci_clk ; ; N/A ; None ; 8.900 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|adoe ; pci_ad[18] ; pci_clk ; ; N/A ; None ; 8.900 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|adoe ; pci_ad[17] ; pci_clk ; ; N/A ; None ; 8.800 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|adoe ; pci_ad[24] ; pci_clk ; ; N/A ; None ; 8.800 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|adoe ; pci_ad[25] ; pci_clk ; ; N/A ; None ; 8.800 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|cbe_oer_not ; pci_framen ; pci_clk ; ; N/A ; None ; 8.800 ns ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|frame_or_not ; pci_framen ; pci_clk ; ; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; +-----------------------------------------+-----------------------------------------------------+------------+------------------------------------------------------------------+-------------+------------+ +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; th ; +-----------------------------------------+-----------------------------------------------------+-----------+--------------+-----------------------------------------------------------------------------------------------------------------+----------+ ; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ; +-----------------------------------------+-----------------------------------------------------+-----------+--------------+-----------------------------------------------------------------------------------------------------------------+----------+ ; -5.400 ns ; 0.100 ns ; 5.500 ns ; DES_ER ; dpm_ni2f_reg_des_er_r ; DES_CLK ; ; -4.500 ns ; 0.100 ns ; 4.600 ns ; DES_DATA[1] ; dpm_ni2f_reg_des_data_r_1 ; DES_CLK ; ; -4.400 ns ; 0.100 ns ; 4.500 ns ; DES_DATA[2] ; dpm_ni2f_reg_des_data_r_2 ; DES_CLK ; ; -4.300 ns ; 0.100 ns ; 4.400 ns ; DES_EN ; dpm_ni2f_reg_des_en_r ; DES_CLK ; ; -4.200 ns ; 0.100 ns ; 4.300 ns ; DES_DATA[3] ; dpm_ni2f_reg_des_data_r_3 ; DES_CLK ; ; -4.100 ns ; 0.100 ns ; 4.200 ns ; DES_DATA[4] ; dpm_ni2f_reg_des_data_r_4 ; DES_CLK ; ; -4.100 ns ; 0.100 ns ; 4.200 ns ; DES_DATA[5] ; dpm_ni2f_reg_des_data_r_5 ; DES_CLK ; ; -4.100 ns ; 0.100 ns ; 4.200 ns ; DES_DATA[6] ; dpm_ni2f_reg_des_data_r_6 ; DES_CLK ; ; -4.000 ns ; 0.100 ns ; 4.100 ns ; DES_DATA[15] ; dpm_ni2f_reg_des_data_r_15 ; DES_CLK ; ; -3.900 ns ; 0.100 ns ; 4.000 ns ; DES_DATA[7] ; dpm_ni2f_reg_des_data_r_7 ; DES_CLK ; ; -3.900 ns ; 0.100 ns ; 4.000 ns ; DES_DATA[14] ; dpm_ni2f_reg_des_data_r_14 ; DES_CLK ; ; -3.800 ns ; 0.100 ns ; 3.900 ns ; DES_DATA[8] ; dpm_ni2f_reg_des_data_r_8 ; DES_CLK ; ; -3.800 ns ; 0.100 ns ; 3.900 ns ; DES_DATA[12] ; dpm_ni2f_reg_des_data_r_12 ; DES_CLK ; ; -3.800 ns ; 0.100 ns ; 3.900 ns ; DES_DATA[13] ; dpm_ni2f_reg_des_data_r_13 ; DES_CLK ; ; -3.700 ns ; 0.100 ns ; 3.800 ns ; DES_DATA[0] ; dpm_ni2f_reg_des_data_r_0 ; DES_CLK ; ; -3.700 ns ; 0.100 ns ; 3.800 ns ; DES_DATA[9] ; dpm_ni2f_reg_des_data_r_9 ; DES_CLK ; ; -3.700 ns ; 0.100 ns ; 3.800 ns ; DES_DATA[10] ; dpm_ni2f_reg_des_data_r_10 ; DES_CLK ; ; -3.700 ns ; 0.100 ns ; 3.800 ns ; DES_DATA[11] ; dpm_ni2f_reg_des_data_r_11 ; DES_CLK ; ; N/A ; None ; 4.200 ns ; SRAM_IO[5] ; dpm_ni2f_reg_sram_qL_5 ; DES_CLK ; ; N/A ; None ; 4.200 ns ; SRAM_IO[5] ; dpm_ni2f_reg_sram_qH_5 ; DES_CLK ; ; N/A ; None ; 4.100 ns ; SRAM_IO[4] ; dpm_ni2f_reg_sram_qL_4 ; DES_CLK ; ; N/A ; None ; 3.700 ns ; SRAM_IO[11] ; dpm_ni2f_reg_sram_qL_11 ; DES_CLK ; ; N/A ; None ; 3.500 ns ; SRAM_IO[14] ; dpm_ni2f_reg_sram_qL_14 ; DES_CLK ; ; N/A ; None ; 3.500 ns ; SRAM_IO[10] ; dpm_ni2f_reg_sram_qL_10 ; DES_CLK ; ; N/A ; None ; 3.500 ns ; SRAM_IO[2] ; dpm_ni2f_reg_sram_qL_2 ; DES_CLK ; ; N/A ; None ; 3.500 ns ; SRAM_IO[0] ; dpm_ni2f_reg_sram_qH_0 ; DES_CLK ; ; N/A ; None ; 3.000 ns ; SRAM_IO[3] ; dpm_ni2f_reg_sram_qL_3 ; DES_CLK ; ; N/A ; None ; 2.900 ns ; SRAM_IO[1] ; dpm_ni2f_reg_sram_qH_1 ; DES_CLK ; ; N/A ; None ; 2.800 ns ; SRAM_IO[15] ; dpm_ni2f_reg_sram_qL_15 ; DES_CLK ; ; N/A ; None ; 2.700 ns ; SRAM_IO[1] ; dpm_ni2f_reg_sram_qL_1 ; DES_CLK ; ; N/A ; None ; 2.600 ns ; SRAM_IO[9] ; dpm_ni2f_reg_sram_qL_9 ; DES_CLK ; ; N/A ; None ; 2.600 ns ; SRAM_IO[4] ; dpm_ni2f_reg_sram_qH_4 ; DES_CLK ; ; N/A ; None ; 2.500 ns ; SRAM_IO[11] ; dpm_ni2f_reg_sram_qH_11 ; DES_CLK ; ; N/A ; None ; 2.500 ns ; SRAM_IO[10] ; dpm_ni2f_reg_sram_qH_10 ; DES_CLK ; ; N/A ; None ; 2.400 ns ; SRAM_IO[2] ; dpm_ni2f_reg_sram_qH_2 ; DES_CLK ; ; N/A ; None ; 2.300 ns ; SRAM_IO[14] ; dpm_ni2f_reg_sram_qH_14 ; DES_CLK ; ; N/A ; None ; 2.300 ns ; SRAM_IO[0] ; dpm_ni2f_reg_sram_qL_0 ; DES_CLK ; ; N/A ; None ; 2.000 ns ; SRAM_IO[15] ; dpm_ni2f_reg_sram_qH_15 ; DES_CLK ; ; N/A ; None ; 2.000 ns ; SRAM_IO[13] ; dpm_ni2f_reg_sram_qL_13 ; DES_CLK ; ; N/A ; None ; 2.000 ns ; SRAM_IO[7] ; dpm_ni2f_reg_sram_qL_7 ; DES_CLK ; ; N/A ; None ; 2.000 ns ; SRAM_IO[3] ; dpm_ni2f_reg_sram_qH_3 ; DES_CLK ; ; N/A ; None ; 1.800 ns ; SRAM_IO[6] ; dpm_ni2f_reg_sram_qL_6 ; DES_CLK ; ; N/A ; None ; 1.600 ns ; SRAM_IO[12] ; dpm_ni2f_reg_sram_qH_12 ; DES_CLK ; ; N/A ; None ; 1.600 ns ; SRAM_IO[6] ; dpm_ni2f_reg_sram_qH_6 ; DES_CLK ; ; N/A ; None ; 1.000 ns ; SRAM_IO[9] ; dpm_ni2f_reg_sram_qH_9 ; DES_CLK ; ; N/A ; None ; 0.800 ns ; SRAM_IO[8] ; dpm_ni2f_reg_sram_qH_8 ; DES_CLK ; ; N/A ; None ; 0.800 ns ; SRAM_IO[7] ; dpm_ni2f_reg_sram_qH_7 ; DES_CLK ; ; N/A ; None ; 0.500 ns ; SRAM_IO[13] ; dpm_ni2f_reg_sram_qH_13 ; DES_CLK ; ; N/A ; None ; 0.000 ns ; SRAM_IO[8] ; dpm_ni2f_reg_sram_qL_8 ; DES_CLK ; ; N/A ; None ; -0.100 ns ; SRAM_IO[12] ; dpm_ni2f_reg_sram_qL_12 ; DES_CLK ; ; N/A ; None ; -1.300 ns ; pci_cben[2] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_cben_IR_data[2] ; pci_clk ; ; N/A ; None ; -1.400 ns ; pci_gntn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|frame_or_not ; pci_clk ; ; N/A ; None ; -1.400 ns ; pci_cben[0] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_cben_IR_data[0] ; pci_clk ; ; N/A ; None ; -1.500 ns ; pci_cben[2] ; pci_contr:pci|pci_mt32:pci_mt32_inst|cben_ir_address[2] ; pci_clk ; ; N/A ; None ; -1.500 ns ; pci_gntn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MS_ENA ; pci_clk ; ; N/A ; None ; -1.500 ns ; pci_gntn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|dac_cyc_strobe ; pci_clk ; ; N/A ; None ; -1.600 ns ; pci_gntn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|adr_phase_end ; pci_clk ; ; N/A ; None ; -1.700 ns ; pci_gntn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lm_adr_ack_R ; pci_clk ; ; N/A ; None ; -1.700 ns ; pci_gntn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|adr_phase ; pci_clk ; ; N/A ; None ; -1.800 ns ; pci_cben[2] ; pci_contr:pci|pci_mt32:pci_mt32_inst|par_or ; pci_clk ; ; N/A ; None ; -1.800 ns ; pci_cben[3] ; pci_contr:pci|pci_mt32:pci_mt32_inst|par_or ; pci_clk ; ; N/A ; None ; -1.800 ns ; pci_gntn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MS_PARK ; pci_clk ; ; N/A ; None ; -1.800 ns ; pci_gntn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MS_REQ ; pci_clk ; ; N/A ; None ; -1.900 ns ; pci_gntn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MS_IDLE_not ; pci_clk ; ; N/A ; None ; -2.000 ns ; pci_ad[23] ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[23] ; pci_clk ; ; N/A ; None ; -2.000 ns ; pci_ad[29] ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[29] ; pci_clk ; ; N/A ; None ; -2.000 ns ; pci_ad[9] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[9] ; pci_clk ; ; N/A ; None ; -2.100 ns ; pci_ad[30] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[30] ; pci_clk ; ; N/A ; None ; -2.100 ns ; pci_cben[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_cben_IR_data[1] ; pci_clk ; ; N/A ; None ; -2.100 ns ; pci_ad[9] ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[9] ; pci_clk ; ; N/A ; None ; -2.200 ns ; pci_ad[29] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[29] ; pci_clk ; ; N/A ; None ; -2.200 ns ; pci_gntn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|ad_oer ; pci_clk ; ; N/A ; None ; -2.500 ns ; pci_ad[24] ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[24] ; pci_clk ; ; N/A ; None ; -2.500 ns ; pci_ad[24] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[24] ; pci_clk ; ; N/A ; None ; -2.500 ns ; pci_ad[25] ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[25] ; pci_clk ; ; N/A ; None ; -2.500 ns ; pci_ad[26] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[26] ; pci_clk ; ; N/A ; None ; -2.500 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|tabrt_set ; pci_clk ; ; N/A ; None ; -2.600 ns ; pci_ad[20] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[20] ; pci_clk ; ; N/A ; None ; -2.600 ns ; pci_ad[21] ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[21] ; pci_clk ; ; N/A ; None ; -2.600 ns ; pci_ad[21] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[21] ; pci_clk ; ; N/A ; None ; -2.600 ns ; pci_ad[22] ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[22] ; pci_clk ; ; N/A ; None ; -2.600 ns ; pci_ad[22] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[22] ; pci_clk ; ; N/A ; None ; -2.600 ns ; pci_ad[23] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[23] ; pci_clk ; ; N/A ; None ; -2.600 ns ; pci_ad[25] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[25] ; pci_clk ; ; N/A ; None ; -2.600 ns ; pci_ad[26] ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[26] ; pci_clk ; ; N/A ; None ; -2.600 ns ; pci_ad[27] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[27] ; pci_clk ; ; N/A ; None ; -2.600 ns ; pci_ad[19] ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[19] ; pci_clk ; ; N/A ; None ; -2.600 ns ; pci_ad[19] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[19] ; pci_clk ; ; N/A ; None ; -2.600 ns ; pci_ad[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[1] ; pci_clk ; ; N/A ; None ; -2.600 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MS_DXFR ; pci_clk ; ; N/A ; None ; -2.600 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LLXFR_r1 ; pci_clk ; ; N/A ; None ; -2.600 ns ; pci_ad[18] ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[18] ; pci_clk ; ; N/A ; None ; -2.600 ns ; pci_ad[18] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[18] ; pci_clk ; ; N/A ; None ; -2.600 ns ; pci_ad[17] ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[17] ; pci_clk ; ; N/A ; None ; -2.600 ns ; pci_ad[17] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[17] ; pci_clk ; ; N/A ; None ; -2.600 ns ; pci_ad[16] ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[16] ; pci_clk ; ; N/A ; None ; -2.600 ns ; pci_ad[16] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[16] ; pci_clk ; ; N/A ; None ; -2.600 ns ; pci_ad[11] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[11] ; pci_clk ; ; N/A ; None ; -2.600 ns ; pci_ad[10] ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[10] ; pci_clk ; ; N/A ; None ; -2.600 ns ; pci_ad[10] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[10] ; pci_clk ; ; N/A ; None ; -2.600 ns ; pci_ad[6] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[6] ; pci_clk ; ; N/A ; None ; -2.600 ns ; pci_ad[5] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[5] ; pci_clk ; ; N/A ; None ; -2.600 ns ; pci_ad[3] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[3] ; pci_clk ; ; N/A ; None ; -2.700 ns ; pci_ad[20] ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[20] ; pci_clk ; ; N/A ; None ; -2.700 ns ; pci_ad[27] ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[27] ; pci_clk ; ; N/A ; None ; -2.700 ns ; pci_ad[28] ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[28] ; pci_clk ; ; N/A ; None ; -2.700 ns ; pci_gntn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_LXFR_r[2] ; pci_clk ; ; N/A ; None ; -2.700 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MS_TAR ; pci_clk ; ; N/A ; None ; -2.700 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|perr_vldR ; pci_clk ; ; N/A ; None ; -2.700 ns ; pci_ad[7] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[7] ; pci_clk ; ; N/A ; None ; -2.700 ns ; pci_ad[7] ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[7] ; pci_clk ; ; N/A ; None ; -2.700 ns ; pci_par ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|serr_or ; pci_clk ; ; N/A ; None ; -2.700 ns ; pci_par ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|perr_or_not ; pci_clk ; ; N/A ; None ; -2.700 ns ; pci_par ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|perr_det_setR_r3 ; pci_clk ; ; N/A ; None ; -2.700 ns ; pci_par ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|perr_det_setR_r1 ; pci_clk ; ; N/A ; None ; -2.800 ns ; pci_framen ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|TS_DXFR ; pci_clk ; ; N/A ; None ; -2.800 ns ; pci_gntn ; pci_contr:pci|pci_mt32:pci_mt32_inst|par_oeR ; pci_clk ; ; N/A ; None ; -2.800 ns ; pci_gntn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MS_ADR ; pci_clk ; ; N/A ; None ; -2.800 ns ; pci_gntn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|irdy_oer ; pci_clk ; ; N/A ; None ; -2.800 ns ; pci_stopn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LLWAIT_r1 ; pci_clk ; ; N/A ; None ; -2.800 ns ; pci_stopn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|tabrt_set ; pci_clk ; ; N/A ; None ; -2.800 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LLWAIT_r1 ; pci_clk ; ; N/A ; None ; -2.800 ns ; pci_ad[12] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[12] ; pci_clk ; ; N/A ; None ; -2.900 ns ; pci_idsel ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|idsel_IR ; pci_clk ; ; N/A ; None ; -2.900 ns ; pci_ad[28] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[28] ; pci_clk ; ; N/A ; None ; -2.900 ns ; pci_gntn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|park ; pci_clk ; ; N/A ; None ; -2.900 ns ; pci_gntn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_IDLE_not ; pci_clk ; ; N/A ; None ; -2.900 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|ad_oer ; pci_clk ; ; N/A ; None ; -2.900 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LLWAIT_r2 ; pci_clk ; ; N/A ; None ; -2.900 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LLXFR_r2 ; pci_clk ; ; N/A ; None ; -2.900 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LPXFR_r1 ; pci_clk ; ; N/A ; None ; -2.900 ns ; pci_ad[15] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[15] ; pci_clk ; ; N/A ; None ; -2.900 ns ; pci_ad[14] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[14] ; pci_clk ; ; N/A ; None ; -2.900 ns ; pci_ad[13] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[13] ; pci_clk ; ; N/A ; None ; -2.900 ns ; pci_ad[4] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[4] ; pci_clk ; ; N/A ; None ; -3.000 ns ; pci_ad[30] ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[30] ; pci_clk ; ; N/A ; None ; -3.000 ns ; pci_framen ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|TS_DISC ; pci_clk ; ; N/A ; None ; -3.000 ns ; pci_devseln ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:devsel_cntr|alt_counter_f10ke:wysi_counter|q[0] ; pci_clk ; ; N/A ; None ; -3.000 ns ; pci_devseln ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|devselR ; pci_clk ; ; N/A ; None ; -3.000 ns ; pci_devseln ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:devsel_cntr|alt_counter_f10ke:wysi_counter|q[2] ; pci_clk ; ; N/A ; None ; -3.000 ns ; pci_devseln ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:devsel_cntr|alt_counter_f10ke:wysi_counter|q[1] ; pci_clk ; ; N/A ; None ; -3.000 ns ; pci_gntn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|cbe_oer_not ; pci_clk ; ; N/A ; None ; -3.000 ns ; pci_stopn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LPXFR_r1 ; pci_clk ; ; N/A ; None ; -3.000 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|cbe_oer_not ; pci_clk ; ; N/A ; None ; -3.000 ns ; pci_ad[3] ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[3] ; pci_clk ; ; N/A ; None ; -3.100 ns ; pci_devseln ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|tabrt_set ; pci_clk ; ; N/A ; None ; -3.100 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LWAIT ; pci_clk ; ; N/A ; None ; -3.200 ns ; pci_framen ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|WAIT_wait32 ; pci_clk ; ; N/A ; None ; -3.200 ns ; pci_framen ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|idle_reg ; pci_clk ; ; N/A ; None ; -3.200 ns ; pci_devseln ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|devsel_toR ; pci_clk ; ; N/A ; None ; -3.200 ns ; pci_stopn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_HOLD ; pci_clk ; ; N/A ; None ; -3.200 ns ; pci_stopn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_DXFR_32_r[2] ; pci_clk ; ; N/A ; None ; -3.200 ns ; pci_stopn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_END_r[2] ; pci_clk ; ; N/A ; None ; -3.200 ns ; pci_ad[8] ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[8] ; pci_clk ; ; N/A ; None ; -3.200 ns ; pci_ad[8] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[8] ; pci_clk ; ; N/A ; None ; -3.300 ns ; pci_ad[1] ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[1] ; pci_clk ; ; N/A ; None ; -3.300 ns ; pci_framen ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_sr:burst_trans|REG ; pci_clk ; ; N/A ; None ; -3.300 ns ; pci_stopn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LWAIT ; pci_clk ; ; N/A ; None ; -3.300 ns ; pci_stopn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_LXFR_r[1] ; pci_clk ; ; N/A ; None ; -3.300 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|frame_or_not ; pci_clk ; ; N/A ; None ; -3.300 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|DXFR_write ; pci_clk ; ; N/A ; None ; -3.300 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_END ; pci_clk ; ; N/A ; None ; -3.400 ns ; pci_framen ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|stop_OR_NOT ; pci_clk ; ; N/A ; None ; -3.400 ns ; pci_gntn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|latcntr_toR ; pci_clk ; ; N/A ; None ; -3.400 ns ; pci_stopn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MS_DXFR ; pci_clk ; ; N/A ; None ; -3.400 ns ; pci_stopn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LLXFR_r1 ; pci_clk ; ; N/A ; None ; -3.400 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_PXFR_r2 ; pci_clk ; ; N/A ; None ; -3.500 ns ; pci_framen ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|trdy_OR_NOT ; pci_clk ; ; N/A ; None ; -3.500 ns ; pci_framen ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|park ; pci_clk ; ; N/A ; None ; -3.500 ns ; pci_framen ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_DONE ; pci_clk ; ; N/A ; None ; -3.500 ns ; pci_stopn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_DXFR_32_r[1] ; pci_clk ; ; N/A ; None ; -3.600 ns ; pci_framen ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_ack_R_r3 ; pci_clk ; ; N/A ; None ; -3.600 ns ; pci_framen ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_ack_R_r1 ; pci_clk ; ; N/A ; None ; -3.600 ns ; pci_stopn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MS_TAR ; pci_clk ; ; N/A ; None ; -3.600 ns ; pci_stopn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_END ; pci_clk ; ; N/A ; None ; -3.600 ns ; pci_stopn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_PXFR_r2 ; pci_clk ; ; N/A ; None ; -3.700 ns ; pci_perrn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|perr_rep_setR ; pci_clk ; ; N/A ; None ; -3.700 ns ; pci_framen ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|TS_TURN_AR ; pci_clk ; ; N/A ; None ; -3.700 ns ; pci_framen ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_ack_R_r4 ; pci_clk ; ; N/A ; None ; -3.700 ns ; pci_framen ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_WAIT ; pci_clk ; ; N/A ; None ; -3.700 ns ; pci_framen ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_PXFR_32_r1 ; pci_clk ; ; N/A ; None ; -3.700 ns ; pci_stopn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_PXFR_r1 ; pci_clk ; ; N/A ; None ; -3.700 ns ; pci_ad[12] ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[12] ; pci_clk ; ; N/A ; None ; -3.700 ns ; pci_ad[11] ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[11] ; pci_clk ; ; N/A ; None ; -3.800 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_ack_R_r2 ; pci_clk ; ; N/A ; None ; -3.800 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|perr_vldR ; pci_clk ; ; N/A ; None ; -3.800 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|idle_reg ; pci_clk ; ; N/A ; None ; -3.800 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|park ; pci_clk ; ; N/A ; None ; -3.800 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_LXFR ; pci_clk ; ; N/A ; None ; -3.800 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_PXFR_r1 ; pci_clk ; ; N/A ; None ; -3.800 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_PXFR_32_r1 ; pci_clk ; ; N/A ; None ; -3.800 ns ; pci_framen ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_LXFR ; pci_clk ; ; N/A ; None ; -3.800 ns ; pci_framen ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_PXFR_r1 ; pci_clk ; ; N/A ; None ; -3.800 ns ; pci_stopn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|ad_oer ; pci_clk ; ; N/A ; None ; -3.800 ns ; pci_trdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_LXFR_r[1] ; pci_clk ; ; N/A ; None ; -3.800 ns ; pci_ad[15] ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[15] ; pci_clk ; ; N/A ; None ; -3.800 ns ; pci_ad[13] ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[13] ; pci_clk ; ; N/A ; None ; -3.800 ns ; pci_ad[2] ; pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[2] ; pci_clk ; ; N/A ; None ; -3.800 ns ; pci_ad[2] ; pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[2] ; pci_clk ; ; N/A ; None ; -3.900 ns ; pci_irdyn ; pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_sr:burst_trans|REG ; pci_clk ; ; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; +-----------------------------------------+-----------------------------------------------------+-----------+--------------+-----------------------------------------------------------------------------------------------------------------+----------+ +--------------------------+ ; Timing Analyzer Messages ; +--------------------------+ Info: ******************************************************************* Info: Running Quartus II Timing Analyzer Info: Version 5.0 Build 148 04/26/2005 SJ Full Version Info: Processing started: Thu Sep 28 16:32:53 2006 Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off top_trap_pci -c top_trap_pci Info: Started post-fitting delay annotation Info: Delay annotation completed successfully Warning: Ignored minimum timing requirements(s) -- minimum timing requirements analyzed only when minimum analysis is run Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew Info: Detected ripple clock "lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|q[15]" as buffer Info: Slack time is 0 ps for clock "DES_CLK" between source register "dpm_ni2f_reg_des_valid_data" and destination register "dpm_ni2f_fifo_h_reg_nwords_9" Info: Fmax is 125.0 MHz (period= 8.0 ns) Info: + Largest register to register requirement is 7.000 ns Info: + Setup relationship between source and destination is 8.000 ns Info: + Latch edge is 8.000 ns Info: Clock period of Destination clock "DES_CLK" is 8.000 ns with offset of 0.000 ns and duty cycle of 50 Info: Multicycle Setup factor for Destination register is 1 Info: - Launch edge is 0.000 ns Info: Clock period of Source clock "DES_CLK" is 8.000 ns with offset of 0.000 ns and duty cycle of 50 Info: Multicycle Setup factor for Source register is 1 Info: + Largest clock skew is 0.000 ns Info: + Shortest clock path from clock "DES_CLK" to destination register is 6.800 ns Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_26; Fanout = 1; CLK Node = 'DES_CLK' Info: 2: + IC(1.300 ns) + CELL(0.500 ns) = 3.800 ns; Loc. = LC1_F39; Fanout = 603; COMB Node = 'lcst' Info: 3: + IC(3.000 ns) + CELL(0.000 ns) = 6.800 ns; Loc. = LC8_F8; Fanout = 6; REG Node = 'dpm_ni2f_fifo_h_reg_nwords_9' Info: Total cell delay = 2.500 ns ( 36.76 % ) Info: Total interconnect delay = 4.300 ns ( 63.24 % ) Info: - Longest clock path from clock "DES_CLK" to source register is 6.800 ns Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_26; Fanout = 1; CLK Node = 'DES_CLK' Info: 2: + IC(1.300 ns) + CELL(0.500 ns) = 3.800 ns; Loc. = LC1_F39; Fanout = 603; COMB Node = 'lcst' Info: 3: + IC(3.000 ns) + CELL(0.000 ns) = 6.800 ns; Loc. = LC1_G47; Fanout = 53; REG Node = 'dpm_ni2f_reg_des_valid_data' Info: Total cell delay = 2.500 ns ( 36.76 % ) Info: Total interconnect delay = 4.300 ns ( 63.24 % ) Info: - Micro clock to output delay of source is 0.600 ns Info: - Micro setup delay of destination is 0.400 ns Info: - Longest register to register delay is 7.000 ns Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_G47; Fanout = 53; REG Node = 'dpm_ni2f_reg_des_valid_data' Info: 2: + IC(3.900 ns) + CELL(0.600 ns) = 4.500 ns; Loc. = LC3_F24; Fanout = 11; COMB Node = 'ix2319_lc' Info: 3: + IC(1.000 ns) + CELL(0.500 ns) = 6.000 ns; Loc. = LC8_F19; Fanout = 1; COMB Node = 'ix2290~0' Info: 4: + IC(0.900 ns) + CELL(0.100 ns) = 7.000 ns; Loc. = LC8_F8; Fanout = 6; REG Node = 'dpm_ni2f_fifo_h_reg_nwords_9' Info: Total cell delay = 1.200 ns ( 17.14 % ) Info: Total interconnect delay = 5.800 ns ( 82.86 % ) Info: Slack time is 10.111 ns for clock "pci_clk" between source register "pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1]" and destination register "pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[0]" Info: Fmax is 51.81 MHz (period= 19.3 ns) Info: + Largest register to register requirement is 28.411 ns Info: + Setup relationship between source and destination is 29.411 ns Info: + Latch edge is 29.411 ns Info: Clock period of Destination clock "pci_clk" is 29.411 ns with offset of 0.000 ns and duty cycle of 50 Info: Multicycle Setup factor for Destination register is 1 Info: - Launch edge is 0.000 ns Info: Clock period of Source clock "pci_clk" is 29.411 ns with offset of 0.000 ns and duty cycle of 50 Info: Multicycle Setup factor for Source register is 1 Info: + Largest clock skew is 0.000 ns Info: + Shortest clock path from clock "pci_clk" to destination register is 1.100 ns Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_79; Fanout = 386; CLK Node = 'pci_clk' Info: 2: + IC(0.800 ns) + CELL(0.000 ns) = 1.100 ns; Loc. = LC3_A4; Fanout = 2; REG Node = 'pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[0]' Info: Total cell delay = 0.300 ns ( 27.27 % ) Info: Total interconnect delay = 0.800 ns ( 72.73 % ) Info: - Longest clock path from clock "pci_clk" to source register is 1.100 ns Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_79; Fanout = 386; CLK Node = 'pci_clk' Info: 2: + IC(0.800 ns) + CELL(0.000 ns) = 1.100 ns; Loc. = LC6_H21; Fanout = 21; REG Node = 'pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1]' Info: Total cell delay = 0.300 ns ( 27.27 % ) Info: Total interconnect delay = 0.800 ns ( 72.73 % ) Info: - Micro clock to output delay of source is 0.600 ns Info: - Micro setup delay of destination is 0.400 ns Info: - Longest register to register delay is 18.300 ns Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6_H21; Fanout = 21; REG Node = 'pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1]' Info: 2: + IC(2.000 ns) + CELL(0.600 ns) = 2.600 ns; Loc. = LC4_A21; Fanout = 18; COMB Node = 'pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_adr[5]' Info: 3: + IC(2.500 ns) + CELL(0.600 ns) = 5.700 ns; Loc. = LC2_B50; Fanout = 23; COMB Node = 'ix2311_lc' Info: 4: + IC(4.300 ns) + CELL(0.600 ns) = 10.600 ns; Loc. = LC6_B22; Fanout = 32; COMB Node = 'ix2321_lc' Info: 5: + IC(3.200 ns) + CELL(0.200 ns) = 14.000 ns; Loc. = LC7_B50; Fanout = 1; COMB Node = 'ix2389~3' Info: 6: + IC(0.000 ns) + CELL(1.000 ns) = 15.000 ns; Loc. = LC8_B50; Fanout = 2; COMB Node = 'ix2244~0' Info: 7: + IC(3.100 ns) + CELL(0.200 ns) = 18.300 ns; Loc. = LC3_A4; Fanout = 2; REG Node = 'pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[0]' Info: Total cell delay = 3.200 ns ( 17.49 % ) Info: Total interconnect delay = 15.100 ns ( 82.51 % ) Info: Minimum slack time is 600 ps for clock "DES_CLK" between source register "dpm_ni2f_fifo_h_reg_fifo_empty" and destination register "dpm_ni2f_fifo_h_reg_fifo_empty" Info: + Shortest register to register delay is 0.500 ns Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7_F25; Fanout = 19; REG Node = 'dpm_ni2f_fifo_h_reg_fifo_empty' Info: 2: + IC(0.400 ns) + CELL(0.100 ns) = 0.500 ns; Loc. = LC7_F25; Fanout = 19; REG Node = 'dpm_ni2f_fifo_h_reg_fifo_empty' Info: Total cell delay = 0.100 ns ( 20.00 % ) Info: Total interconnect delay = 0.400 ns ( 80.00 % ) Info: - Smallest register to register requirement is -0.100 ns Info: + Hold relationship between source and destination is 0.000 ns Info: + Latch edge is 0.000 ns Info: Clock period of Destination clock "DES_CLK" is 8.000 ns with offset of 0.000 ns and duty cycle of 50 Info: Multicycle Setup factor for Destination register is 1 Info: Multicycle Hold factor for Destination register is 1 Info: - Launch edge is 0.000 ns Info: Clock period of Source clock "DES_CLK" is 8.000 ns with offset of 0.000 ns and duty cycle of 50 Info: Multicycle Setup factor for Source register is 1 Info: Multicycle Hold factor for Source register is 1 Info: + Smallest clock skew is 0.000 ns Info: + Longest clock path from clock "DES_CLK" to destination register is 6.800 ns Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_26; Fanout = 1; CLK Node = 'DES_CLK' Info: 2: + IC(1.300 ns) + CELL(0.500 ns) = 3.800 ns; Loc. = LC1_F39; Fanout = 603; COMB Node = 'lcst' Info: 3: + IC(3.000 ns) + CELL(0.000 ns) = 6.800 ns; Loc. = LC7_F25; Fanout = 19; REG Node = 'dpm_ni2f_fifo_h_reg_fifo_empty' Info: Total cell delay = 2.500 ns ( 36.76 % ) Info: Total interconnect delay = 4.300 ns ( 63.24 % ) Info: - Shortest clock path from clock "DES_CLK" to source register is 6.800 ns Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_26; Fanout = 1; CLK Node = 'DES_CLK' Info: 2: + IC(1.300 ns) + CELL(0.500 ns) = 3.800 ns; Loc. = LC1_F39; Fanout = 603; COMB Node = 'lcst' Info: 3: + IC(3.000 ns) + CELL(0.000 ns) = 6.800 ns; Loc. = LC7_F25; Fanout = 19; REG Node = 'dpm_ni2f_fifo_h_reg_fifo_empty' Info: Total cell delay = 2.500 ns ( 36.76 % ) Info: Total interconnect delay = 4.300 ns ( 63.24 % ) Info: - Micro clock to output delay of source is 0.600 ns Info: + Micro hold delay of destination is 0.500 ns Info: Minimum slack time is 600 ps for clock "pci_clk" between source register "sg_reg_mx_q" and destination register "sg_reg_mx_q" Info: + Shortest register to register delay is 0.500 ns Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_H25; Fanout = 18; REG Node = 'sg_reg_mx_q' Info: 2: + IC(0.400 ns) + CELL(0.100 ns) = 0.500 ns; Loc. = LC5_H25; Fanout = 18; REG Node = 'sg_reg_mx_q' Info: Total cell delay = 0.100 ns ( 20.00 % ) Info: Total interconnect delay = 0.400 ns ( 80.00 % ) Info: - Smallest register to register requirement is -0.100 ns Info: + Hold relationship between source and destination is 0.000 ns Info: + Latch edge is 0.000 ns Info: Clock period of Destination clock "pci_clk" is 29.411 ns with offset of 0.000 ns and duty cycle of 50 Info: Multicycle Setup factor for Destination register is 1 Info: Multicycle Hold factor for Destination register is 1 Info: - Launch edge is 0.000 ns Info: Clock period of Source clock "pci_clk" is 29.411 ns with offset of 0.000 ns and duty cycle of 50 Info: Multicycle Setup factor for Source register is 1 Info: Multicycle Hold factor for Source register is 1 Info: + Smallest clock skew is 0.000 ns Info: + Longest clock path from clock "pci_clk" to destination register is 3.200 ns Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_79; Fanout = 386; CLK Node = 'pci_clk' Info: 2: + IC(0.800 ns) + CELL(0.600 ns) = 1.700 ns; Loc. = LC8_H11; Fanout = 2; REG Node = 'lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|q[15]' Info: 3: + IC(1.500 ns) + CELL(0.000 ns) = 3.200 ns; Loc. = LC5_H25; Fanout = 18; REG Node = 'sg_reg_mx_q' Info: Total cell delay = 0.900 ns ( 28.13 % ) Info: Total interconnect delay = 2.300 ns ( 71.88 % ) Info: - Shortest clock path from clock "pci_clk" to source register is 3.200 ns Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_79; Fanout = 386; CLK Node = 'pci_clk' Info: 2: + IC(0.800 ns) + CELL(0.600 ns) = 1.700 ns; Loc. = LC8_H11; Fanout = 2; REG Node = 'lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|q[15]' Info: 3: + IC(1.500 ns) + CELL(0.000 ns) = 3.200 ns; Loc. = LC5_H25; Fanout = 18; REG Node = 'sg_reg_mx_q' Info: Total cell delay = 0.900 ns ( 28.13 % ) Info: Total interconnect delay = 2.300 ns ( 71.88 % ) Info: - Micro clock to output delay of source is 0.600 ns Info: + Micro hold delay of destination is 0.500 ns Info: Slack time is 3.8 ns for clock "DES_CLK" between source pin "DES_DATA[0]" and destination register "dpm_ni2f_reg_des_data_r_0" Info: + tsu requirement for source pin and destination register is 1.500 ns Info: - tsu from clock to input pin is -2.300 ns Info: + Longest pin to register delay is 2.000 ns Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_27; Fanout = 1; PIN Node = 'DES_DATA[0]' Info: 2: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = IOC_27; Fanout = 1; REG Node = 'dpm_ni2f_reg_des_data_r_0' Info: Total cell delay = 2.000 ns ( 100.00 % ) Info: + Micro setup delay of destination is 0.800 ns Info: - Shortest clock path from clock "DES_CLK" to destination register is 5.100 ns Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_26; Fanout = 1; CLK Node = 'DES_CLK' Info: 2: + IC(1.300 ns) + CELL(0.500 ns) = 3.800 ns; Loc. = LC1_F39; Fanout = 603; COMB Node = 'lcst' Info: 3: + IC(1.300 ns) + CELL(0.000 ns) = 5.100 ns; Loc. = IOC_27; Fanout = 1; REG Node = 'dpm_ni2f_reg_des_data_r_0' Info: Total cell delay = 2.500 ns ( 49.02 % ) Info: Total interconnect delay = 2.600 ns ( 50.98 % ) Info: tco from clock "pci_clk" to destination pin "R7S[1]" through register "sg_reg_mx_q" is 19.400 ns Info: + Longest clock path from clock "pci_clk" to source register is 3.200 ns Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_79; Fanout = 386; CLK Node = 'pci_clk' Info: 2: + IC(0.800 ns) + CELL(0.600 ns) = 1.700 ns; Loc. = LC8_H11; Fanout = 2; REG Node = 'lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|q[15]' Info: 3: + IC(1.500 ns) + CELL(0.000 ns) = 3.200 ns; Loc. = LC5_H25; Fanout = 18; REG Node = 'sg_reg_mx_q' Info: Total cell delay = 0.900 ns ( 28.13 % ) Info: Total interconnect delay = 2.300 ns ( 71.88 % ) Info: + Micro clock to output delay of source is 0.600 ns Info: + Longest register to pin delay is 15.600 ns Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_H25; Fanout = 18; REG Node = 'sg_reg_mx_q' Info: 2: + IC(1.900 ns) + CELL(0.500 ns) = 2.400 ns; Loc. = LC3_H50; Fanout = 4; COMB Node = 'ix2530' Info: 3: + IC(1.400 ns) + CELL(0.500 ns) = 4.300 ns; Loc. = LC5_H43; Fanout = 6; COMB Node = 'ix2308_lc' Info: 4: + IC(1.400 ns) + CELL(0.600 ns) = 6.300 ns; Loc. = LC6_H36; Fanout = 1; COMB Node = 'ix2532' Info: 5: + IC(0.400 ns) + CELL(0.500 ns) = 7.200 ns; Loc. = LC4_H36; Fanout = 3; COMB Node = 'ix2248_lc' Info: 6: + IC(1.400 ns) + CELL(0.800 ns) = 9.400 ns; Loc. = LC1_H37; Fanout = 1; COMB Node = 'ix2692_lc' Info: 7: + IC(0.800 ns) + CELL(5.400 ns) = 15.600 ns; Loc. = PIN_192; Fanout = 0; PIN Node = 'R7S[1]' Info: Total cell delay = 8.300 ns ( 53.21 % ) Info: Total interconnect delay = 7.300 ns ( 46.79 % ) Warning: Can't achieve timing requirement th along 18 path(s). See Report window for details. Info: Minimum slack time is -5.4 ns for clock "DES_CLK" between source pin "DES_ER" and destination register "dpm_ni2f_reg_des_er_r" Info: + th requirement for source pin and destination register is 0.100 ns Info: - th from clock to input pin is 5.500 ns Info: + Longest clock path from clock "DES_CLK" to destination register is 6.800 ns Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_26; Fanout = 1; CLK Node = 'DES_CLK' Info: 2: + IC(1.300 ns) + CELL(0.500 ns) = 3.800 ns; Loc. = LC1_F39; Fanout = 603; COMB Node = 'lcst' Info: 3: + IC(3.000 ns) + CELL(0.000 ns) = 6.800 ns; Loc. = IOC_202; Fanout = 2; REG Node = 'dpm_ni2f_reg_des_er_r' Info: Total cell delay = 2.500 ns ( 36.76 % ) Info: Total interconnect delay = 4.300 ns ( 63.24 % ) Info: + Micro hold delay of destination is 0.700 ns Info: - Shortest pin to register delay is 2.000 ns Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_202; Fanout = 1; PIN Node = 'DES_ER' Info: 2: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = IOC_202; Fanout = 2; REG Node = 'dpm_ni2f_reg_des_er_r' Info: Total cell delay = 2.000 ns ( 100.00 % ) Critical Warning: Timing requirements were not met. See Report window for details. Info: Quartus II Timing Analyzer was successful. 0 errors, 4 warnings Info: Processing ended: Thu Sep 28 16:32:59 2006 Info: Elapsed time: 00:00:07