Simulator report for top_trap_pci Mon Nov 28 18:36:51 2005 Version 5.0 Build 148 04/26/2005 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. Simulator Summary 3. Simulator Settings 4. Simulation Waveforms 5. |top_trap_pci|nififo8:dpm_ni2f_fifo_l|dcfifo:dcfifo_component|dcfifo_njr:auto_generated|altdpram:fiforam|content 6. |top_trap_pci|nififo8:dpm_ni2f_fifo_h|dcfifo:dcfifo_component|dcfifo_njr:auto_generated|altdpram:fiforam|content 7. Simulator INI Usage 8. Simulator Messages ---------------- ; Legal Notice ; ---------------- Copyright (C) 1991-2005 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. +--------------------------------------------+ ; Simulator Summary ; +-----------------------------+--------------+ ; Type ; Value ; +-----------------------------+--------------+ ; Simulation Start Time ; 0 ps ; ; Simulation End Time ; 1.0 us ; ; Simulation Netlist Size ; 2970 nodes ; ; Simulation Coverage ; 12.34 % ; ; Total Number of Transitions ; 6701 ; +-----------------------------+--------------+ +--------------------------------------------------------------------+ ; Simulator Settings ; +-------------------------------------------------------+------------+ ; Option ; Setting ; +-------------------------------------------------------+------------+ ; Simulation mode ; Functional ; ; Start time ; 0ns ; ; Add pins automatically to simulation output waveforms ; On ; ; Check outputs ; Off ; ; Report simulation coverage ; On ; ; Detect setup and hold time violations ; Off ; ; Detect glitches ; Off ; ; Automatically save/load simulation netlist ; Off ; ; Disable timing delays in Timing Simulation ; Off ; ; Generate Signal Activity File ; Off ; +-------------------------------------------------------+------------+ +----------------------+ ; Simulation Waveforms ; +----------------------+ Waveform report data cannot be output to ASCII. Please use Quartus II to view the waveform report data. +------------------------------------------------------------------------------------------------------------------+ ; |top_trap_pci|nififo8:dpm_ni2f_fifo_l|dcfifo:dcfifo_component|dcfifo_njr:auto_generated|altdpram:fiforam|content ; +------------------------------------------------------------------------------------------------------------------+ Memory report data cannot be output to ASCII. Please use Quartus II to view the memory report data. +------------------------------------------------------------------------------------------------------------------+ ; |top_trap_pci|nififo8:dpm_ni2f_fifo_h|dcfifo:dcfifo_component|dcfifo_njr:auto_generated|altdpram:fiforam|content ; +------------------------------------------------------------------------------------------------------------------+ Memory report data cannot be output to ASCII. Please use Quartus II to view the memory report data. +---------------------+ ; Simulator INI Usage ; +--------+------------+ ; Option ; Usage ; +--------+------------+ +--------------------+ ; Simulator Messages ; +--------------------+ Info: ******************************************************************* Info: Running Quartus II Simulator Info: Version 5.0 Build 148 04/26/2005 SJ Full Version Info: Processing started: Mon Nov 28 18:36:48 2005 Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off top_trap_pci -c top_trap_pci Info: Overwriting simulation input file with simulation results Warning: Can't find signal in vector source file for input pin "|top_trap_pci|LVDS_in[0]" Warning: Can't find signal in vector source file for input pin "|top_trap_pci|LVDS_in[1]" Warning: Can't find signal in vector source file for input pin "|top_trap_pci|LVDS_in[2]" Warning: Can't find signal in vector source file for input pin "|top_trap_pci|LVDS_in[3]" Warning: Can't find signal in vector source file for input pin "|top_trap_pci|pci_ad[0]" Warning: Can't find signal in vector source file for input pin "|top_trap_pci|pci_ad[1]" Warning: Can't find signal in vector source file for input pin "|top_trap_pci|pci_ad[2]" Warning: Can't find signal in vector source file for input pin "|top_trap_pci|pci_ad[3]" Warning: Can't find signal in vector source file for input pin "|top_trap_pci|pci_ad[4]" Warning: Can't find signal in vector source file for input pin "|top_trap_pci|pci_ad[5]" Warning: Can't find signal in vector source file for input pin "|top_trap_pci|pci_ad[6]" Warning: Can't find signal in vector source file for input pin "|top_trap_pci|pci_ad[7]" Warning: Can't find signal in vector source file for input pin "|top_trap_pci|pci_ad[8]" Warning: Can't find signal in vector source file for input pin "|top_trap_pci|pci_ad[9]" Warning: Can't find signal in vector source file for input pin "|top_trap_pci|pci_ad[10]" Warning: Can't find signal in vector source file for input pin "|top_trap_pci|pci_ad[11]" Warning: Can't find signal in vector source file for input pin "|top_trap_pci|pci_ad[12]" Warning: Can't find signal in vector source file for input pin "|top_trap_pci|pci_ad[13]" Warning: Can't find signal in vector source file for input pin "|top_trap_pci|pci_ad[14]" Warning: Can't find signal in vector source file for input pin "|top_trap_pci|pci_ad[15]" Warning: Can't find signal in vector source file for input pin "|top_trap_pci|pci_ad[16]" Warning: Can't find signal in vector source file for input pin "|top_trap_pci|pci_ad[17]" Warning: Can't find signal in vector source file for input pin "|top_trap_pci|pci_ad[18]" Warning: Can't find signal in vector source file for input pin "|top_trap_pci|pci_ad[19]" Warning: Can't find signal in vector source file for input pin "|top_trap_pci|pci_ad[20]" Warning: Can't find signal in vector source file for input pin "|top_trap_pci|pci_ad[21]" Warning: Can't find signal in vector source file for input pin "|top_trap_pci|pci_ad[22]" Warning: Can't find signal in vector source file for input pin "|top_trap_pci|pci_ad[23]" Warning: Can't find signal in vector source file for input pin "|top_trap_pci|pci_ad[24]" Warning: Can't find signal in vector source file for input pin "|top_trap_pci|pci_ad[25]" Warning: Can't find signal in vector source file for input pin "|top_trap_pci|pci_ad[26]" Warning: Can't find signal in vector source file for input pin "|top_trap_pci|pci_ad[27]" Warning: Can't find signal in vector source file for input pin "|top_trap_pci|pci_ad[28]" Warning: Can't find signal in vector source file for input pin "|top_trap_pci|pci_ad[29]" Warning: Can't find signal in vector source file for input pin "|top_trap_pci|pci_ad[30]" Warning: Can't find signal in vector source file for input pin "|top_trap_pci|pci_ad[31]" Warning: Can't find signal in vector source file for input pin "|top_trap_pci|pci_cben[0]" Warning: Can't find signal in vector source file for input pin "|top_trap_pci|pci_cben[1]" Warning: Can't find signal in vector source file for input pin "|top_trap_pci|pci_cben[2]" Warning: Can't find signal in vector source file for input pin "|top_trap_pci|pci_cben[3]" Warning: Can't find signal in vector source file for input pin "|top_trap_pci|pci_devseln" Warning: Can't find signal in vector source file for input pin "|top_trap_pci|pci_framen" Warning: Can't find signal in vector source file for input pin "|top_trap_pci|pci_gntn" Warning: Can't find signal in vector source file for input pin "|top_trap_pci|pci_idsel" Warning: Can't find signal in vector source file for input pin "|top_trap_pci|pci_irdyn" Warning: Can't find signal in vector source file for input pin "|top_trap_pci|pci_lockn" Warning: Can't find signal in vector source file for input pin "|top_trap_pci|pci_par" Warning: Can't find signal in vector source file for input pin "|top_trap_pci|pci_perrn" Warning: Can't find signal in vector source file for input pin "|top_trap_pci|pci_stopn" Warning: Can't find signal in vector source file for input pin "|top_trap_pci|pci_trdyn" Warning: Found clock-sensitive change during active clock edge at time 905.0 ns on register "|top_trap_pci|dpm_ni2f_reg_des_en_r" Info: Simulation coverage is 12.34 % Info: Number of transitions in simulation is 6701 Info: Quartus II Simulator was successful. 0 errors, 51 warnings Info: Processing ended: Mon Nov 28 18:36:50 2005 Info: Elapsed time: 00:00:03