-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--dpm_ni2f_reg_we_n is dpm_ni2f_reg_we_n
--operation mode is normal

dpm_ni2f_reg_we_n_lut_out = dpm_ni2f_reg_sm_1 & (dpm_ni2f_fifo_h_reg_fifo_empty) # !dpm_ni2f_reg_sm_1 & dpm_ni2f_reg_rdreq_fifo;
dpm_ni2f_reg_we_n = DFFEA(dpm_ni2f_reg_we_n_lut_out, lcst, !ix2254, , , , );

--A1L215Q is dpm_ni2f_reg_we_n~0
--operation mode is normal

A1L215Q = dpm_ni2f_reg_we_n;


--dpm_ni2f_reg_not_empty is dpm_ni2f_reg_not_empty
--operation mode is normal

dpm_ni2f_reg_not_empty_lut_out = dpm_ni2f_reg_sm_0 # dpm_dec_reg_soft_rst_n & dpm_ni2f_reg_not_empty;
dpm_ni2f_reg_not_empty = DFFEA(dpm_ni2f_reg_not_empty_lut_out, lcst, !ix2254, , , , );

--A1L514Q is dpm_ni2f_reg_not_empty~0
--operation mode is normal

A1L514Q = dpm_ni2f_reg_not_empty;


--dpm_ni2f_reg_ds_en_reg is dpm_ni2f_reg_ds_en_reg
--operation mode is normal

dpm_ni2f_reg_ds_en_reg_lut_out = dpm_ni2f_reg_des_en_r;
dpm_ni2f_reg_ds_en_reg = DFFEA(dpm_ni2f_reg_ds_en_reg_lut_out, lcst, , , , , );

--A1L114Q is dpm_ni2f_reg_ds_en_reg~1
--operation mode is normal

A1L114Q = dpm_ni2f_reg_ds_en_reg;


--sg_reg_mx_q is sg_reg_mx_q
--operation mode is normal

sg_reg_mx_q_lut_out = !sg_reg_mx_q;
sg_reg_mx_q = DFFEA(sg_reg_mx_q_lut_out, E1_q[15], , , , , );

--A1L8521Q is sg_reg_mx_q~1
--operation mode is normal

A1L8521Q = sg_reg_mx_q;


--dpm_ni2f_reg_addr_0 is dpm_ni2f_reg_addr_0
--operation mode is normal

dpm_ni2f_reg_addr_0_lut_out = A1L456 & (dpm_ni2f_reg_addr_0) # !A1L456 & (dpm_ni2f_reg_sm_5 # ix2381_lc);
dpm_ni2f_reg_addr_0 = DFFEA(dpm_ni2f_reg_addr_0_lut_out, lcst, !ix2254, , , , );

--A1L992Q is dpm_ni2f_reg_addr_0~0
--operation mode is normal

A1L992Q = dpm_ni2f_reg_addr_0;


--dpm_ni2f_reg_addr_1 is dpm_ni2f_reg_addr_1
--operation mode is normal

dpm_ni2f_reg_addr_1_lut_out = A1L456 & (dpm_ni2f_reg_addr_1) # !A1L456 & ix2271_lc;
dpm_ni2f_reg_addr_1 = DFFEA(dpm_ni2f_reg_addr_1_lut_out, lcst, !ix2254, , , , );

--A1L103Q is dpm_ni2f_reg_addr_1~0
--operation mode is normal

A1L103Q = dpm_ni2f_reg_addr_1;


--dpm_ni2f_reg_addr_2 is dpm_ni2f_reg_addr_2
--operation mode is normal

dpm_ni2f_reg_addr_2_lut_out = A1L456 & (dpm_ni2f_reg_addr_2) # !A1L456 & ix2270_lc;
dpm_ni2f_reg_addr_2 = DFFEA(dpm_ni2f_reg_addr_2_lut_out, lcst, !ix2254, , , , );

--A1L303Q is dpm_ni2f_reg_addr_2~0
--operation mode is normal

A1L303Q = dpm_ni2f_reg_addr_2;


--dpm_ni2f_reg_addr_3 is dpm_ni2f_reg_addr_3
--operation mode is normal

dpm_ni2f_reg_addr_3_lut_out = A1L456 & (dpm_ni2f_reg_addr_3) # !A1L456 & ix2269_lc;
dpm_ni2f_reg_addr_3 = DFFEA(dpm_ni2f_reg_addr_3_lut_out, lcst, !ix2254, , , , );

--A1L503Q is dpm_ni2f_reg_addr_3~0
--operation mode is normal

A1L503Q = dpm_ni2f_reg_addr_3;


--dpm_ni2f_reg_addr_4 is dpm_ni2f_reg_addr_4
--operation mode is normal

dpm_ni2f_reg_addr_4_lut_out = A1L456 & (dpm_ni2f_reg_addr_4) # !A1L456 & ix2268_lc;
dpm_ni2f_reg_addr_4 = DFFEA(dpm_ni2f_reg_addr_4_lut_out, lcst, !ix2254, , , , );

--A1L703Q is dpm_ni2f_reg_addr_4~0
--operation mode is normal

A1L703Q = dpm_ni2f_reg_addr_4;


--dpm_ni2f_reg_addr_5 is dpm_ni2f_reg_addr_5
--operation mode is normal

dpm_ni2f_reg_addr_5_lut_out = A1L456 & (dpm_ni2f_reg_addr_5) # !A1L456 & ix2267_lc;
dpm_ni2f_reg_addr_5 = DFFEA(dpm_ni2f_reg_addr_5_lut_out, lcst, !ix2254, , , , );

--A1L903Q is dpm_ni2f_reg_addr_5~0
--operation mode is normal

A1L903Q = dpm_ni2f_reg_addr_5;


--dpm_ni2f_reg_addr_6 is dpm_ni2f_reg_addr_6
--operation mode is normal

dpm_ni2f_reg_addr_6_lut_out = A1L456 & (dpm_ni2f_reg_addr_6) # !A1L456 & ix2266_lc;
dpm_ni2f_reg_addr_6 = DFFEA(dpm_ni2f_reg_addr_6_lut_out, lcst, !ix2254, , , , );

--A1L113Q is dpm_ni2f_reg_addr_6~0
--operation mode is normal

A1L113Q = dpm_ni2f_reg_addr_6;


--dpm_ni2f_reg_addr_7 is dpm_ni2f_reg_addr_7
--operation mode is normal

dpm_ni2f_reg_addr_7_lut_out = A1L456 & (dpm_ni2f_reg_addr_7) # !A1L456 & ix2265_lc;
dpm_ni2f_reg_addr_7 = DFFEA(dpm_ni2f_reg_addr_7_lut_out, lcst, !ix2254, , , , );

--A1L313Q is dpm_ni2f_reg_addr_7~0
--operation mode is normal

A1L313Q = dpm_ni2f_reg_addr_7;


--dpm_ni2f_reg_addr_8 is dpm_ni2f_reg_addr_8
--operation mode is normal

dpm_ni2f_reg_addr_8_lut_out = A1L456 & (dpm_ni2f_reg_addr_8) # !A1L456 & ix2264_lc;
dpm_ni2f_reg_addr_8 = DFFEA(dpm_ni2f_reg_addr_8_lut_out, lcst, !ix2254, , , , );

--A1L513Q is dpm_ni2f_reg_addr_8~0
--operation mode is normal

A1L513Q = dpm_ni2f_reg_addr_8;


--dpm_ni2f_reg_addr_9 is dpm_ni2f_reg_addr_9
--operation mode is normal

dpm_ni2f_reg_addr_9_lut_out = A1L456 & (dpm_ni2f_reg_addr_9) # !A1L456 & ix2263_lc;
dpm_ni2f_reg_addr_9 = DFFEA(dpm_ni2f_reg_addr_9_lut_out, lcst, !ix2254, , , , );

--A1L713Q is dpm_ni2f_reg_addr_9~0
--operation mode is normal

A1L713Q = dpm_ni2f_reg_addr_9;


--dpm_ni2f_reg_addr_10 is dpm_ni2f_reg_addr_10
--operation mode is normal

dpm_ni2f_reg_addr_10_lut_out = A1L456 & (dpm_ni2f_reg_addr_10) # !A1L456 & ix2262_lc;
dpm_ni2f_reg_addr_10 = DFFEA(dpm_ni2f_reg_addr_10_lut_out, lcst, !ix2254, , , , );

--A1L913Q is dpm_ni2f_reg_addr_10~0
--operation mode is normal

A1L913Q = dpm_ni2f_reg_addr_10;


--dpm_ni2f_reg_addr_11 is dpm_ni2f_reg_addr_11
--operation mode is normal

dpm_ni2f_reg_addr_11_lut_out = A1L456 & (dpm_ni2f_reg_addr_11) # !A1L456 & ix2261_lc;
dpm_ni2f_reg_addr_11 = DFFEA(dpm_ni2f_reg_addr_11_lut_out, lcst, !ix2254, , , , );

--A1L123Q is dpm_ni2f_reg_addr_11~0
--operation mode is normal

A1L123Q = dpm_ni2f_reg_addr_11;


--dpm_ni2f_reg_addr_12 is dpm_ni2f_reg_addr_12
--operation mode is normal

dpm_ni2f_reg_addr_12_lut_out = A1L456 & (dpm_ni2f_reg_addr_12) # !A1L456 & ix2260_lc;
dpm_ni2f_reg_addr_12 = DFFEA(dpm_ni2f_reg_addr_12_lut_out, lcst, !ix2254, , , , );

--A1L323Q is dpm_ni2f_reg_addr_12~0
--operation mode is normal

A1L323Q = dpm_ni2f_reg_addr_12;


--dpm_ni2f_reg_addr_13 is dpm_ni2f_reg_addr_13
--operation mode is normal

dpm_ni2f_reg_addr_13_lut_out = A1L456 & (dpm_ni2f_reg_addr_13) # !A1L456 & ix2259_lc;
dpm_ni2f_reg_addr_13 = DFFEA(dpm_ni2f_reg_addr_13_lut_out, lcst, !ix2254, , , , );

--A1L523Q is dpm_ni2f_reg_addr_13~0
--operation mode is normal

A1L523Q = dpm_ni2f_reg_addr_13;


--dpm_ni2f_reg_addr_14 is dpm_ni2f_reg_addr_14
--operation mode is normal

dpm_ni2f_reg_addr_14_lut_out = A1L456 & (dpm_ni2f_reg_addr_14) # !A1L456 & ix2258_lc;
dpm_ni2f_reg_addr_14 = DFFEA(dpm_ni2f_reg_addr_14_lut_out, lcst, !ix2254, , , , );

--A1L723Q is dpm_ni2f_reg_addr_14~0
--operation mode is normal

A1L723Q = dpm_ni2f_reg_addr_14;


--dpm_ni2f_reg_addr_15 is dpm_ni2f_reg_addr_15
--operation mode is normal

dpm_ni2f_reg_addr_15_lut_out = A1L456 & (dpm_ni2f_reg_addr_15) # !A1L456 & ix2257_lc;
dpm_ni2f_reg_addr_15 = DFFEA(dpm_ni2f_reg_addr_15_lut_out, lcst, !ix2254, , , , );

--A1L923Q is dpm_ni2f_reg_addr_15~0
--operation mode is normal

A1L923Q = dpm_ni2f_reg_addr_15;


--dpm_ni2f_reg_addr_16 is dpm_ni2f_reg_addr_16
--operation mode is normal

dpm_ni2f_reg_addr_16_lut_out = A1L456 & (dpm_ni2f_reg_addr_16) # !A1L456 & ix2256_lc;
dpm_ni2f_reg_addr_16 = DFFEA(dpm_ni2f_reg_addr_16_lut_out, lcst, !ix2254, , , , );

--A1L133Q is dpm_ni2f_reg_addr_16~0
--operation mode is normal

A1L133Q = dpm_ni2f_reg_addr_16;


--dpm_ni2f_reg_addr_17 is dpm_ni2f_reg_addr_17
--operation mode is normal

dpm_ni2f_reg_addr_17_lut_out = A1L456 & (dpm_ni2f_reg_addr_17) # !A1L456 & ix2255_lc;
dpm_ni2f_reg_addr_17 = DFFEA(dpm_ni2f_reg_addr_17_lut_out, lcst, !ix2254, , , , );

--A1L333Q is dpm_ni2f_reg_addr_17~0
--operation mode is normal

A1L333Q = dpm_ni2f_reg_addr_17;


--dpm_ni2f_reg_ce_n is dpm_ni2f_reg_ce_n
--operation mode is normal

dpm_ni2f_reg_ce_n_lut_out = !dpm_ni2f_reg_sm_11 & dpm_ni2f_reg_sm_0 & (dpm_ni2f_fifo_h_reg_fifo_empty # !dpm_ni2f_reg_sm_1);
dpm_ni2f_reg_ce_n = DFFEA(dpm_ni2f_reg_ce_n_lut_out, lcst, !ix2254, , , , );

--A1L533Q is dpm_ni2f_reg_ce_n~0
--operation mode is normal

A1L533Q = dpm_ni2f_reg_ce_n;


--dpm_ni2f_reg_clk_sram_i is dpm_ni2f_reg_clk_sram_i
--operation mode is normal

dpm_ni2f_reg_clk_sram_i_lut_out = !A1L867;
dpm_ni2f_reg_clk_sram_i = DFFEA(dpm_ni2f_reg_clk_sram_i_lut_out, lcst, !ix2254, , , , );

--A1L733Q is dpm_ni2f_reg_clk_sram_i~1
--operation mode is normal

A1L733Q = dpm_ni2f_reg_clk_sram_i;


--dpm_ni2f_reg_re_n is dpm_ni2f_reg_re_n
--operation mode is normal

dpm_ni2f_reg_re_n_lut_out = (!dpm_ni2f_reg_sm_4 & !dpm_ni2f_reg_sm_3 & !dpm_ni2f_reg_sm_1 & !dpm_ni2f_reg_rdreq_fifo) & CASCADE(A1L497);
dpm_ni2f_reg_re_n = DFFEA(dpm_ni2f_reg_re_n_lut_out, lcst, !ix2254, , , , );

--A1L124Q is dpm_ni2f_reg_re_n~0
--operation mode is normal

A1L124Q = dpm_ni2f_reg_re_n;


--dpm_ni2f_reg_sm_1 is dpm_ni2f_reg_sm_1
--operation mode is normal

dpm_ni2f_reg_sm_1_lut_out = dpm_ni2f_reg_rdreq_fifo # !dpm_ni2f_reg_sm_0 & dpm_ni2f_fifo_h_reg_fifo_empty;
dpm_ni2f_reg_sm_1 = DFFEA(dpm_ni2f_reg_sm_1_lut_out, lcst, !ix2254, , , , );

--A1L524Q is dpm_ni2f_reg_sm_1~0
--operation mode is normal

A1L524Q = dpm_ni2f_reg_sm_1;


--dpm_ni2f_reg_rdreq_fifo is dpm_ni2f_reg_rdreq_fifo
--operation mode is normal

dpm_ni2f_reg_rdreq_fifo_lut_out = !ix2326_lc;
dpm_ni2f_reg_rdreq_fifo = DFFEA(dpm_ni2f_reg_rdreq_fifo_lut_out, lcst, !ix2254, , , , );

--A1L914Q is dpm_ni2f_reg_rdreq_fifo~1
--operation mode is normal

A1L914Q = dpm_ni2f_reg_rdreq_fifo;


--dpm_ni2f_fifo_h_reg_fifo_empty is dpm_ni2f_fifo_h_reg_fifo_empty
--operation mode is normal

dpm_ni2f_fifo_h_reg_fifo_empty_lut_out = ix2300_lc & (dpm_ni2f_reg_des_valid_data # !A1L48) # !ix2300_lc & (dpm_ni2f_fifo_h_reg_fifo_empty);
dpm_ni2f_fifo_h_reg_fifo_empty = DFFEA(dpm_ni2f_fifo_h_reg_fifo_empty_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--A1L78Q is dpm_ni2f_fifo_h_reg_fifo_empty~0
--operation mode is normal

A1L78Q = dpm_ni2f_fifo_h_reg_fifo_empty;


--dpm_dec_reg_soft_rst_n is dpm_dec_reg_soft_rst_n
--operation mode is normal

dpm_dec_reg_soft_rst_n_lut_out = !A1L395;
dpm_dec_reg_soft_rst_n = DFFEA(dpm_dec_reg_soft_rst_n_lut_out, GLOBAL(pci_clk), pci_rstn, , , , );

--A1L16Q is dpm_dec_reg_soft_rst_n~1
--operation mode is normal

A1L16Q = dpm_dec_reg_soft_rst_n;


--ix2254 is ix2254
--operation mode is normal

ix2254 = !dpm_dec_reg_soft_rst_n # !pci_rstn;

--A1L206 is ix2254~0
--operation mode is normal

A1L206 = !dpm_dec_reg_soft_rst_n # !pci_rstn;


--dpm_ni2f_reg_sm_0 is dpm_ni2f_reg_sm_0
--operation mode is normal

dpm_ni2f_reg_sm_0_lut_out = !A1L077;
dpm_ni2f_reg_sm_0 = DFFEA(dpm_ni2f_reg_sm_0_lut_out, lcst, !ix2254, , , , );

--A1L324Q is dpm_ni2f_reg_sm_0~1
--operation mode is normal

A1L324Q = dpm_ni2f_reg_sm_0;


--dpm_ni2f_reg_des_en_r is dpm_ni2f_reg_des_en_r
--operation mode is normal

dpm_ni2f_reg_des_en_r_lut_out = DES_EN;
dpm_ni2f_reg_des_en_r = DFFEA(dpm_ni2f_reg_des_en_r_lut_out, lcst, , , , , );

--A1L504Q is dpm_ni2f_reg_des_en_r~1
--operation mode is normal

A1L504Q = dpm_ni2f_reg_des_en_r;


--K1_serr_or is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|serr_or
--operation mode is normal

K1_serr_or = AMPP_FUNCTION(K1_serr_or_lc, A1L8321, K1_xxlad[11], pci_rstn, GLOBAL(pci_clk));

--K1L41Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|serr_or~37
--operation mode is normal

K1L41Q = AMPP_FUNCTION(K1_serr_or_lc, A1L8321, K1_xxlad[11], pci_rstn, GLOBAL(pci_clk));


--ix2698_lc is ix2698_lc
--operation mode is normal

ix2698_lc = A1L359 # A1L169 # ix2308_lc & A1L569;

--A1L2311 is ix2698_lc~0
--operation mode is normal

A1L2311 = A1L359 # A1L169 # ix2308_lc & A1L569;


--ix2697_lc is ix2697_lc
--operation mode is normal

ix2697_lc = ix2349_lc # ix2245_lc & ix2246_lc & ix2305_lc;

--A1L9211 is ix2697_lc~0
--operation mode is normal

A1L9211 = ix2349_lc # ix2245_lc & ix2246_lc & ix2305_lc;


--ix2696_lc is ix2696_lc
--operation mode is normal

ix2696_lc = ix2248_lc # ix2249_lc # ix2384_lc;

--A1L6211 is ix2696_lc~0
--operation mode is normal

A1L6211 = ix2248_lc # ix2249_lc # ix2384_lc;


--ix2695_lc is ix2695_lc
--operation mode is normal

ix2695_lc = ix2248_lc # ix2385_lc # ix2305_lc & A1L569;

--A1L3211 is ix2695_lc~0
--operation mode is normal

A1L3211 = ix2248_lc # ix2385_lc # ix2305_lc & A1L569;


--ix2694_lc is ix2694_lc
--operation mode is normal

ix2694_lc = ix2245_lc & !ix2246_lc & ix2305_lc # !ix2245_lc & (ix2305_lc # !ix2246_lc & ix2310_lc);

--A1L0211 is ix2694_lc~0
--operation mode is normal

A1L0211 = ix2245_lc & !ix2246_lc & ix2305_lc # !ix2245_lc & (ix2305_lc # !ix2246_lc & ix2310_lc);


--ix2693_lc is ix2693_lc
--operation mode is normal

ix2693_lc = A1L585 # ix2306_lc # A1L169 # A1L369;

--A1L7111 is ix2693_lc~0
--operation mode is normal

A1L7111 = A1L585 # ix2306_lc # A1L169 # A1L369;


--ix2692_lc is ix2692_lc
--operation mode is normal

ix2692_lc = ix2248_lc # ix2306_lc # ix2305_lc & A1L447;

--A1L4111 is ix2692_lc~0
--operation mode is normal

A1L4111 = ix2248_lc # ix2306_lc # ix2305_lc & A1L447;


--E1_q[15] is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|q[15]
--operation mode is up_dn_cntr

E1_q[15]_lut_out = E1_q[15] $ E1L64;
E1_q[15] = DFFEA(E1_q[15]_lut_out, GLOBAL(pci_clk), , , , , );

--E1L05Q is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|q[15]~0
--operation mode is up_dn_cntr

E1L05Q = E1_q[15];


--dpm_ni2f_reg_sm_5 is dpm_ni2f_reg_sm_5
--operation mode is normal

dpm_ni2f_reg_sm_5_lut_out = dpm_ni2f_reg_sm_4;
dpm_ni2f_reg_sm_5 = DFFEA(dpm_ni2f_reg_sm_5_lut_out, lcst, !ix2254, , , , );

--A1L134Q is dpm_ni2f_reg_sm_5~1
--operation mode is normal

A1L134Q = dpm_ni2f_reg_sm_5;


--dpm_ni2f_reg_sm_11 is dpm_ni2f_reg_sm_11
--operation mode is normal

dpm_ni2f_reg_sm_11_lut_out = dpm_ni2f_reg_sm_10 # dpm_ni2f_reg_sm_11 & dpm_ni2f_reg_pci_rd_req_s;
dpm_ni2f_reg_sm_11 = DFFEA(dpm_ni2f_reg_sm_11_lut_out, lcst, !ix2254, , , , );

--A1L344Q is dpm_ni2f_reg_sm_11~0
--operation mode is normal

A1L344Q = dpm_ni2f_reg_sm_11;


--dpm_ni2f_reg_des_valid_data is dpm_ni2f_reg_des_valid_data
--operation mode is normal

dpm_ni2f_reg_des_valid_data_lut_out = dpm_ni2f_reg_des_en_r & !dpm_ni2f_reg_des_er_r;
dpm_ni2f_reg_des_valid_data = DFFEA(dpm_ni2f_reg_des_valid_data_lut_out, lcst, , , , , );

--A1L904Q is dpm_ni2f_reg_des_valid_data~0
--operation mode is normal

A1L904Q = dpm_ni2f_reg_des_valid_data;


--dpm_ni2f_reg_sreset120 is dpm_ni2f_reg_sreset120
--operation mode is normal

dpm_ni2f_reg_sreset120_lut_out = !dpm_dec_reg_soft_rst_n;
dpm_ni2f_reg_sreset120 = DFFEA(dpm_ni2f_reg_sreset120_lut_out, lcst, , , , , );

--A1L015Q is dpm_ni2f_reg_sreset120~2
--operation mode is normal

A1L015Q = dpm_ni2f_reg_sreset120;


--dpm_dec_reg_rdata_LED_7 is dpm_dec_reg_rdata_LED_7
--operation mode is normal

dpm_dec_reg_rdata_LED_7_lut_out = A1L868 & G1_low_ad_IR_data[7] # !A1L868 & (dpm_dec_reg_rdata_LED_7);
dpm_dec_reg_rdata_LED_7 = DFFEA(dpm_dec_reg_rdata_LED_7_lut_out, GLOBAL(pci_clk), pci_rstn, , , , );

--A1L55Q is dpm_dec_reg_rdata_LED_7~0
--operation mode is normal

A1L55Q = dpm_dec_reg_rdata_LED_7;


--dpm_dec_reg_rdata_LED_3 is dpm_dec_reg_rdata_LED_3
--operation mode is normal

dpm_dec_reg_rdata_LED_3_lut_out = A1L868 & G1_low_ad_IR_data[3] # !A1L868 & (dpm_dec_reg_rdata_LED_3);
dpm_dec_reg_rdata_LED_3 = DFFEA(dpm_dec_reg_rdata_LED_3_lut_out, GLOBAL(pci_clk), pci_rstn, , , , );

--A1L74Q is dpm_dec_reg_rdata_LED_3~0
--operation mode is normal

A1L74Q = dpm_dec_reg_rdata_LED_3;


--ix2579 is ix2579
--operation mode is normal

ix2579 = sg_reg_mx_q & (dpm_dec_reg_rdata_LED_3) # !sg_reg_mx_q & dpm_dec_reg_rdata_LED_7;

--A1L1111 is ix2579~1
--operation mode is normal

A1L1111 = sg_reg_mx_q & (dpm_dec_reg_rdata_LED_3) # !sg_reg_mx_q & dpm_dec_reg_rdata_LED_7;

--A1L0111 is ix2579~0
--operation mode is normal

A1L0111 = sg_reg_mx_q & (dpm_dec_reg_rdata_LED_3) # !sg_reg_mx_q & dpm_dec_reg_rdata_LED_7;


--ix2308_lc is ix2308_lc
--operation mode is normal

ix2308_lc = !ix2579 & ix2530;

--A1L247 is ix2308_lc~0
--operation mode is normal

A1L247 = !ix2579 & ix2530;

--A1L347 is ix2308~0
--operation mode is normal

A1L347 = !ix2579 & ix2530;


--dpm_dec_reg_rdata_LED_5 is dpm_dec_reg_rdata_LED_5
--operation mode is normal

dpm_dec_reg_rdata_LED_5_lut_out = A1L868 & G1_low_ad_IR_data[5] # !A1L868 & (dpm_dec_reg_rdata_LED_5);
dpm_dec_reg_rdata_LED_5 = DFFEA(dpm_dec_reg_rdata_LED_5_lut_out, GLOBAL(pci_clk), pci_rstn, , , , );

--A1L15Q is dpm_dec_reg_rdata_LED_5~0
--operation mode is normal

A1L15Q = dpm_dec_reg_rdata_LED_5;


--dpm_dec_reg_rdata_LED_1 is dpm_dec_reg_rdata_LED_1
--operation mode is normal

dpm_dec_reg_rdata_LED_1_lut_out = A1L868 & G1_low_ad_IR_data[1] # !A1L868 & (dpm_dec_reg_rdata_LED_1);
dpm_dec_reg_rdata_LED_1 = DFFEA(dpm_dec_reg_rdata_LED_1_lut_out, GLOBAL(pci_clk), pci_rstn, , , , );

--A1L34Q is dpm_dec_reg_rdata_LED_1~0
--operation mode is normal

A1L34Q = dpm_dec_reg_rdata_LED_1;


--ix2245_lc is ix2245_lc
--operation mode is normal

ix2245_lc = sg_reg_mx_q & (!dpm_dec_reg_rdata_LED_1) # !sg_reg_mx_q & !dpm_dec_reg_rdata_LED_5;

--A1L975 is ix2245_lc~2
--operation mode is normal

A1L975 = sg_reg_mx_q & (!dpm_dec_reg_rdata_LED_1) # !sg_reg_mx_q & !dpm_dec_reg_rdata_LED_5;

--A1L085 is ix2245~2
--operation mode is normal

A1L085 = sg_reg_mx_q & (!dpm_dec_reg_rdata_LED_1) # !sg_reg_mx_q & !dpm_dec_reg_rdata_LED_5;


--ix2305_lc is ix2305_lc
--operation mode is normal

ix2305_lc = ix2579 & ix2530;

--A1L237 is ix2305_lc~0
--operation mode is normal

A1L237 = ix2579 & ix2530;

--A1L337 is ix2305~0
--operation mode is normal

A1L337 = ix2579 & ix2530;


--ix2349_lc is ix2349_lc
--operation mode is normal

ix2349_lc = ix2245_lc & ix2246_lc & (ix2310_lc) # !ix2245_lc & (ix2310_lc # ix2246_lc & ix2308_lc);

--A1L768 is ix2349_lc~0
--operation mode is normal

A1L768 = ix2245_lc & ix2246_lc & (ix2310_lc) # !ix2245_lc & (ix2310_lc # ix2246_lc & ix2308_lc);


--ix2532 is ix2532
--operation mode is normal

ix2532 = ix2246_lc & (ix2310_lc) # !ix2246_lc & ix2308_lc;

--A1L3011 is ix2532~0
--operation mode is normal

A1L3011 = ix2246_lc & (ix2310_lc) # !ix2246_lc & ix2308_lc;


--ix2248_lc is ix2248_lc
--operation mode is normal

ix2248_lc = ix2245_lc & ix2532;

--A1L985 is ix2248_lc~0
--operation mode is normal

A1L985 = ix2245_lc & ix2532;


--ix2249_lc is ix2249_lc
--operation mode is normal

ix2249_lc = ix2246_lc & (ix2245_lc & ix2307_lc # !ix2245_lc & (ix2308_lc));

--A1L295 is ix2249_lc~0
--operation mode is normal

A1L295 = ix2246_lc & (ix2245_lc & ix2307_lc # !ix2245_lc & (ix2308_lc));


--ix2384_lc is ix2384_lc
--operation mode is normal

ix2384_lc = ix2246_lc & (ix2245_lc & ix2308_lc # !ix2245_lc & (ix2310_lc));

--A1L759 is ix2384_lc~0
--operation mode is normal

A1L759 = ix2246_lc & (ix2245_lc & ix2308_lc # !ix2245_lc & (ix2310_lc));


--ix2385_lc is ix2385_lc
--operation mode is normal

ix2385_lc = ix2245_lc & ix2246_lc & ix2307_lc # !ix2245_lc & (ix2246_lc & (ix2308_lc) # !ix2246_lc & ix2307_lc);

--A1L069 is ix2385_lc~0
--operation mode is normal

A1L069 = ix2245_lc & ix2246_lc & ix2307_lc # !ix2245_lc & (ix2246_lc & (ix2308_lc) # !ix2246_lc & ix2307_lc);


--dpm_dec_reg_rdata_LED_6 is dpm_dec_reg_rdata_LED_6
--operation mode is normal

dpm_dec_reg_rdata_LED_6_lut_out = A1L868 & G1_low_ad_IR_data[6] # !A1L868 & (dpm_dec_reg_rdata_LED_6);
dpm_dec_reg_rdata_LED_6 = DFFEA(dpm_dec_reg_rdata_LED_6_lut_out, GLOBAL(pci_clk), pci_rstn, , , , );

--A1L35Q is dpm_dec_reg_rdata_LED_6~0
--operation mode is normal

A1L35Q = dpm_dec_reg_rdata_LED_6;


--dpm_dec_reg_rdata_LED_2 is dpm_dec_reg_rdata_LED_2
--operation mode is normal

dpm_dec_reg_rdata_LED_2_lut_out = A1L868 & G1_low_ad_IR_data[2] # !A1L868 & (dpm_dec_reg_rdata_LED_2);
dpm_dec_reg_rdata_LED_2 = DFFEA(dpm_dec_reg_rdata_LED_2_lut_out, GLOBAL(pci_clk), pci_rstn, , , , );

--A1L54Q is dpm_dec_reg_rdata_LED_2~0
--operation mode is normal

A1L54Q = dpm_dec_reg_rdata_LED_2;


--ix2531 is ix2531
--operation mode is normal

ix2531 = sg_reg_mx_q & (!dpm_dec_reg_rdata_LED_2) # !sg_reg_mx_q & !dpm_dec_reg_rdata_LED_6;

--A1L1011 is ix2531~0
--operation mode is normal

A1L1011 = sg_reg_mx_q & (!dpm_dec_reg_rdata_LED_2) # !sg_reg_mx_q & !dpm_dec_reg_rdata_LED_6;


--ix2310_lc is ix2310_lc
--operation mode is normal

ix2310_lc = !ix2579 & ix2531;

--A1L847 is ix2310_lc~0
--operation mode is normal

A1L847 = !ix2579 & ix2531;

--A1L947 is ix2310~0
--operation mode is normal

A1L947 = !ix2579 & ix2531;


--ix2535 is ix2535
--operation mode is normal

ix2535 = A1L569 & (sg_reg_mx_q & (!dpm_dec_reg_rdata_LED_2) # !sg_reg_mx_q & !dpm_dec_reg_rdata_LED_6);

--A1L5011 is ix2535~0
--operation mode is normal

A1L5011 = A1L569 & (sg_reg_mx_q & (!dpm_dec_reg_rdata_LED_2) # !sg_reg_mx_q & !dpm_dec_reg_rdata_LED_6);


--ix2306_lc is ix2306_lc
--operation mode is normal

ix2306_lc = ix2579 & ix2535;

--A1L637 is ix2306_lc~0
--operation mode is normal

A1L637 = ix2579 & ix2535;


--E1_counter_cell[14] is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[14]
--operation mode is up_dn_cntr

E1_counter_cell[14]_lut_out = E1_counter_cell[14] $ E1L34;
E1_counter_cell[14] = DFFEA(E1_counter_cell[14]_lut_out, GLOBAL(pci_clk), , , , , );

--E1L54Q is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[14]~0
--operation mode is up_dn_cntr

E1L54Q = E1_counter_cell[14];

--E1L64 is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[14]~COUT
--operation mode is up_dn_cntr

E1L64 = CARRY(E1_counter_cell[14] & (E1L34));


--dpm_ni2f_reg_sm_4 is dpm_ni2f_reg_sm_4
--operation mode is normal

dpm_ni2f_reg_sm_4_lut_out = dpm_ni2f_reg_sm_3;
dpm_ni2f_reg_sm_4 = DFFEA(dpm_ni2f_reg_sm_4_lut_out, lcst, !ix2254, , , , );

--A1L924Q is dpm_ni2f_reg_sm_4~1
--operation mode is normal

A1L924Q = dpm_ni2f_reg_sm_4;


--E9_q[0] is lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[0]
--operation mode is clrb_cntr

E9_q[0]_lut_out = (dpm_ni2f_reg_rdreq_fifo $ E9_q[0]) & A1L905;
E9_q[0] = DFFEA(E9_q[0]_lut_out, lcst, , , , , );

--E9L93Q is lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[0]~0
--operation mode is clrb_cntr

E9L93Q = E9_q[0];

--E9L3 is lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT
--operation mode is clrb_cntr

E9L3 = CARRY(E9_q[0]);


--ix2381_lc is ix2381_lc
--operation mode is normal

ix2381_lc = dpm_ni2f_reg_sm_1 & E9_q[0];

--A1L949 is ix2381_lc~0
--operation mode is normal

A1L949 = dpm_ni2f_reg_sm_1 & E9_q[0];


--G1_ad_ir_address[2] is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[2]
--operation mode is normal

G1_ad_ir_address[2] = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_2, pci_rstn, GLOBAL(pci_clk));

--G1L601Q is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[2]~64
--operation mode is normal

G1L601Q = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_2, pci_rstn, GLOBAL(pci_clk));


--M1_no_op_reg[1] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1]
--operation mode is normal

M1_no_op_reg[1] = AMPP_FUNCTION(pci_rstn, GLOBAL(pci_clk));

--M1L124Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[1]~8
--operation mode is normal

M1L124Q = AMPP_FUNCTION(pci_rstn, GLOBAL(pci_clk));


--M1_lt_adr[2] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_adr[2]
--operation mode is normal

M1_lt_adr[2] = AMPP_FUNCTION(G1_ad_ir_address[2], M1_no_op_reg[1]);

--M1L533 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_adr[2]~126
--operation mode is normal

M1L533 = AMPP_FUNCTION(G1_ad_ir_address[2], M1_no_op_reg[1]);


--E9_q[1] is lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[1]
--operation mode is clrb_cntr

E9_q[1]_lut_out = (E9_q[1] $ (dpm_ni2f_reg_rdreq_fifo & E9L3)) & A1L905;
E9_q[1] = DFFEA(E9_q[1]_lut_out, lcst, , , , , );

--E9L14Q is lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[1]~1
--operation mode is clrb_cntr

E9L14Q = E9_q[1];

--E9L5 is lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT
--operation mode is clrb_cntr

E9L5 = CARRY(E9_q[1] & (E9L3));


--ix2271_lc is ix2271_lc
--operation mode is normal

ix2271_lc = dpm_ni2f_reg_sm_1 & (E9_q[1]) # !dpm_ni2f_reg_sm_1 & M1_lt_adr[2];

--A1L356 is ix2271_lc~0
--operation mode is normal

A1L356 = dpm_ni2f_reg_sm_1 & (E9_q[1]) # !dpm_ni2f_reg_sm_1 & M1_lt_adr[2];


--G1_ad_ir_address[3] is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[3]
--operation mode is normal

G1_ad_ir_address[3] = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_3, pci_rstn, GLOBAL(pci_clk));

--G1L801Q is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[3]~65
--operation mode is normal

G1L801Q = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_3, pci_rstn, GLOBAL(pci_clk));


--M1_lt_adr[3] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_adr[3]
--operation mode is normal

M1_lt_adr[3] = AMPP_FUNCTION(M1_no_op_reg[1], G1_ad_ir_address[3]);

--M1L733 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_adr[3]~127
--operation mode is normal

M1L733 = AMPP_FUNCTION(M1_no_op_reg[1], G1_ad_ir_address[3]);


--E9_q[2] is lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[2]
--operation mode is clrb_cntr

E9_q[2]_lut_out = (E9_q[2] $ (dpm_ni2f_reg_rdreq_fifo & E9L5)) & A1L905;
E9_q[2] = DFFEA(E9_q[2]_lut_out, lcst, , , , , );

--E9L34Q is lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[2]~2
--operation mode is clrb_cntr

E9L34Q = E9_q[2];

--E9L7 is lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT
--operation mode is clrb_cntr

E9L7 = CARRY(E9_q[2] & (E9L5));


--ix2270_lc is ix2270_lc
--operation mode is normal

ix2270_lc = dpm_ni2f_reg_sm_1 & (E9_q[2]) # !dpm_ni2f_reg_sm_1 & M1_lt_adr[3];

--A1L056 is ix2270_lc~0
--operation mode is normal

A1L056 = dpm_ni2f_reg_sm_1 & (E9_q[2]) # !dpm_ni2f_reg_sm_1 & M1_lt_adr[3];


--G1_ad_ir_address[4] is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[4]
--operation mode is normal

G1_ad_ir_address[4] = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_4, pci_rstn, GLOBAL(pci_clk));

--G1L011Q is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[4]~66
--operation mode is normal

G1L011Q = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_4, pci_rstn, GLOBAL(pci_clk));


--M1_lt_adr[4] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_adr[4]
--operation mode is normal

M1_lt_adr[4] = AMPP_FUNCTION(M1_no_op_reg[1], G1_ad_ir_address[4]);

--M1L933 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_adr[4]~128
--operation mode is normal

M1L933 = AMPP_FUNCTION(M1_no_op_reg[1], G1_ad_ir_address[4]);


--E9_q[3] is lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[3]
--operation mode is clrb_cntr

E9_q[3]_lut_out = (E9_q[3] $ (dpm_ni2f_reg_rdreq_fifo & E9L7)) & A1L905;
E9_q[3] = DFFEA(E9_q[3]_lut_out, lcst, , , , , );

--E9L54Q is lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[3]~3
--operation mode is clrb_cntr

E9L54Q = E9_q[3];

--E9L9 is lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT
--operation mode is clrb_cntr

E9L9 = CARRY(E9_q[3] & (E9L7));


--ix2269_lc is ix2269_lc
--operation mode is normal

ix2269_lc = dpm_ni2f_reg_sm_1 & (E9_q[3]) # !dpm_ni2f_reg_sm_1 & M1_lt_adr[4];

--A1L746 is ix2269_lc~0
--operation mode is normal

A1L746 = dpm_ni2f_reg_sm_1 & (E9_q[3]) # !dpm_ni2f_reg_sm_1 & M1_lt_adr[4];


--G1_ad_ir_address[5] is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[5]
--operation mode is normal

G1_ad_ir_address[5] = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_5, pci_rstn, GLOBAL(pci_clk));

--G1L211Q is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[5]~67
--operation mode is normal

G1L211Q = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_5, pci_rstn, GLOBAL(pci_clk));


--M1_lt_adr[5] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_adr[5]
--operation mode is normal

M1_lt_adr[5] = AMPP_FUNCTION(M1_no_op_reg[1], G1_ad_ir_address[5]);

--M1L143 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_adr[5]~129
--operation mode is normal

M1L143 = AMPP_FUNCTION(M1_no_op_reg[1], G1_ad_ir_address[5]);


--E9_q[4] is lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[4]
--operation mode is clrb_cntr

E9_q[4]_lut_out = (E9_q[4] $ (dpm_ni2f_reg_rdreq_fifo & E9L9)) & A1L905;
E9_q[4] = DFFEA(E9_q[4]_lut_out, lcst, , , , , );

--E9L74Q is lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[4]~4
--operation mode is clrb_cntr

E9L74Q = E9_q[4];

--E9L11 is lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|counter_cell[4]~COUT
--operation mode is clrb_cntr

E9L11 = CARRY(E9_q[4] & (E9L9));


--ix2268_lc is ix2268_lc
--operation mode is normal

ix2268_lc = dpm_ni2f_reg_sm_1 & (E9_q[4]) # !dpm_ni2f_reg_sm_1 & M1_lt_adr[5];

--A1L446 is ix2268_lc~0
--operation mode is normal

A1L446 = dpm_ni2f_reg_sm_1 & (E9_q[4]) # !dpm_ni2f_reg_sm_1 & M1_lt_adr[5];


--G1_ad_ir_address[6] is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[6]
--operation mode is normal

G1_ad_ir_address[6] = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_6, pci_rstn, GLOBAL(pci_clk));

--G1L411Q is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[6]~68
--operation mode is normal

G1L411Q = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_6, pci_rstn, GLOBAL(pci_clk));


--M1_lt_adr[6] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_adr[6]
--operation mode is normal

M1_lt_adr[6] = AMPP_FUNCTION(M1_no_op_reg[1], G1_ad_ir_address[6]);

--M1L343 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_adr[6]~130
--operation mode is normal

M1L343 = AMPP_FUNCTION(M1_no_op_reg[1], G1_ad_ir_address[6]);


--E9_q[5] is lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[5]
--operation mode is clrb_cntr

E9_q[5]_lut_out = (E9_q[5] $ (dpm_ni2f_reg_rdreq_fifo & E9L11)) & A1L905;
E9_q[5] = DFFEA(E9_q[5]_lut_out, lcst, , , , , );

--E9L94Q is lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[5]~5
--operation mode is clrb_cntr

E9L94Q = E9_q[5];

--E9L31 is lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|counter_cell[5]~COUT
--operation mode is clrb_cntr

E9L31 = CARRY(E9_q[5] & (E9L11));


--ix2267_lc is ix2267_lc
--operation mode is normal

ix2267_lc = dpm_ni2f_reg_sm_1 & (E9_q[5]) # !dpm_ni2f_reg_sm_1 & M1_lt_adr[6];

--A1L146 is ix2267_lc~0
--operation mode is normal

A1L146 = dpm_ni2f_reg_sm_1 & (E9_q[5]) # !dpm_ni2f_reg_sm_1 & M1_lt_adr[6];


--G1_ad_ir_address[7] is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[7]
--operation mode is normal

G1_ad_ir_address[7] = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_7, pci_rstn, GLOBAL(pci_clk));

--G1L611Q is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[7]~69
--operation mode is normal

G1L611Q = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_7, pci_rstn, GLOBAL(pci_clk));


--M1_lt_adr[7] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_adr[7]
--operation mode is normal

M1_lt_adr[7] = AMPP_FUNCTION(M1_no_op_reg[1], G1_ad_ir_address[7]);

--M1L543 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_adr[7]~131
--operation mode is normal

M1L543 = AMPP_FUNCTION(M1_no_op_reg[1], G1_ad_ir_address[7]);


--E9_q[6] is lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[6]
--operation mode is clrb_cntr

E9_q[6]_lut_out = (E9_q[6] $ (dpm_ni2f_reg_rdreq_fifo & E9L31)) & A1L905;
E9_q[6] = DFFEA(E9_q[6]_lut_out, lcst, , , , , );

--E9L15Q is lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[6]~6
--operation mode is clrb_cntr

E9L15Q = E9_q[6];

--E9L51 is lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|counter_cell[6]~COUT
--operation mode is clrb_cntr

E9L51 = CARRY(E9_q[6] & (E9L31));


--ix2266_lc is ix2266_lc
--operation mode is normal

ix2266_lc = dpm_ni2f_reg_sm_1 & (E9_q[6]) # !dpm_ni2f_reg_sm_1 & M1_lt_adr[7];

--A1L836 is ix2266_lc~0
--operation mode is normal

A1L836 = dpm_ni2f_reg_sm_1 & (E9_q[6]) # !dpm_ni2f_reg_sm_1 & M1_lt_adr[7];


--G1_ad_ir_address[8] is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[8]
--operation mode is normal

G1_ad_ir_address[8] = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_8, pci_rstn, GLOBAL(pci_clk));

--G1L811Q is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[8]~70
--operation mode is normal

G1L811Q = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_8, pci_rstn, GLOBAL(pci_clk));


--M1_lt_adr[8] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_adr[8]
--operation mode is normal

M1_lt_adr[8] = AMPP_FUNCTION(M1_no_op_reg[1], G1_ad_ir_address[8]);

--M1L743 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_adr[8]~132
--operation mode is normal

M1L743 = AMPP_FUNCTION(M1_no_op_reg[1], G1_ad_ir_address[8]);


--E9_q[7] is lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[7]
--operation mode is clrb_cntr

E9_q[7]_lut_out = (E9_q[7] $ (dpm_ni2f_reg_rdreq_fifo & E9L51)) & A1L905;
E9_q[7] = DFFEA(E9_q[7]_lut_out, lcst, , , , , );

--E9L35Q is lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[7]~7
--operation mode is clrb_cntr

E9L35Q = E9_q[7];

--E9L71 is lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|counter_cell[7]~COUT
--operation mode is clrb_cntr

E9L71 = CARRY(E9_q[7] & (E9L51));


--ix2265_lc is ix2265_lc
--operation mode is normal

ix2265_lc = dpm_ni2f_reg_sm_1 & (E9_q[7]) # !dpm_ni2f_reg_sm_1 & M1_lt_adr[8];

--A1L536 is ix2265_lc~0
--operation mode is normal

A1L536 = dpm_ni2f_reg_sm_1 & (E9_q[7]) # !dpm_ni2f_reg_sm_1 & M1_lt_adr[8];


--G1_ad_ir_address[9] is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[9]
--operation mode is normal

G1_ad_ir_address[9] = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_9, pci_rstn, GLOBAL(pci_clk));

--G1L021Q is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[9]~71
--operation mode is normal

G1L021Q = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_9, pci_rstn, GLOBAL(pci_clk));


--M1_lt_adr[9] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_adr[9]
--operation mode is normal

M1_lt_adr[9] = AMPP_FUNCTION(M1_no_op_reg[1], G1_ad_ir_address[9]);

--M1L943 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_adr[9]~133
--operation mode is normal

M1L943 = AMPP_FUNCTION(M1_no_op_reg[1], G1_ad_ir_address[9]);


--E9_q[8] is lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[8]
--operation mode is clrb_cntr

E9_q[8]_lut_out = (E9_q[8] $ (dpm_ni2f_reg_rdreq_fifo & E9L71)) & A1L905;
E9_q[8] = DFFEA(E9_q[8]_lut_out, lcst, , , , , );

--E9L55Q is lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[8]~8
--operation mode is clrb_cntr

E9L55Q = E9_q[8];

--E9L91 is lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|counter_cell[8]~COUT
--operation mode is clrb_cntr

E9L91 = CARRY(E9_q[8] & (E9L71));


--ix2264_lc is ix2264_lc
--operation mode is normal

ix2264_lc = dpm_ni2f_reg_sm_1 & (E9_q[8]) # !dpm_ni2f_reg_sm_1 & M1_lt_adr[9];

--A1L236 is ix2264_lc~0
--operation mode is normal

A1L236 = dpm_ni2f_reg_sm_1 & (E9_q[8]) # !dpm_ni2f_reg_sm_1 & M1_lt_adr[9];


--G1_ad_ir_address[10] is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[10]
--operation mode is normal

G1_ad_ir_address[10] = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_10, pci_rstn, GLOBAL(pci_clk));

--G1L221Q is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[10]~72
--operation mode is normal

G1L221Q = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_10, pci_rstn, GLOBAL(pci_clk));


--M1_lt_adr[10] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_adr[10]
--operation mode is normal

M1_lt_adr[10] = AMPP_FUNCTION(M1_no_op_reg[1], G1_ad_ir_address[10]);

--M1L153 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_adr[10]~134
--operation mode is normal

M1L153 = AMPP_FUNCTION(M1_no_op_reg[1], G1_ad_ir_address[10]);


--E9_q[9] is lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[9]
--operation mode is clrb_cntr

E9_q[9]_lut_out = (E9_q[9] $ (dpm_ni2f_reg_rdreq_fifo & E9L91)) & A1L905;
E9_q[9] = DFFEA(E9_q[9]_lut_out, lcst, , , , , );

--E9L75Q is lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[9]~9
--operation mode is clrb_cntr

E9L75Q = E9_q[9];

--E9L12 is lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|counter_cell[9]~COUT
--operation mode is clrb_cntr

E9L12 = CARRY(E9_q[9] & (E9L91));


--ix2263_lc is ix2263_lc
--operation mode is normal

ix2263_lc = dpm_ni2f_reg_sm_1 & (E9_q[9]) # !dpm_ni2f_reg_sm_1 & M1_lt_adr[10];

--A1L926 is ix2263_lc~0
--operation mode is normal

A1L926 = dpm_ni2f_reg_sm_1 & (E9_q[9]) # !dpm_ni2f_reg_sm_1 & M1_lt_adr[10];


--G1_ad_ir_address[11] is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[11]
--operation mode is normal

G1_ad_ir_address[11] = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_11, pci_rstn, GLOBAL(pci_clk));

--G1L421Q is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[11]~73
--operation mode is normal

G1L421Q = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_11, pci_rstn, GLOBAL(pci_clk));


--M1_lt_adr[11] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_adr[11]
--operation mode is normal

M1_lt_adr[11] = AMPP_FUNCTION(M1_no_op_reg[1], G1_ad_ir_address[11]);

--M1L353 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_adr[11]~135
--operation mode is normal

M1L353 = AMPP_FUNCTION(M1_no_op_reg[1], G1_ad_ir_address[11]);


--E9_q[10] is lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[10]
--operation mode is clrb_cntr

E9_q[10]_lut_out = (E9_q[10] $ (dpm_ni2f_reg_rdreq_fifo & E9L12)) & A1L905;
E9_q[10] = DFFEA(E9_q[10]_lut_out, lcst, , , , , );

--E9L95Q is lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[10]~10
--operation mode is clrb_cntr

E9L95Q = E9_q[10];

--E9L32 is lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|counter_cell[10]~COUT
--operation mode is clrb_cntr

E9L32 = CARRY(E9_q[10] & (E9L12));


--ix2262_lc is ix2262_lc
--operation mode is normal

ix2262_lc = dpm_ni2f_reg_sm_1 & (E9_q[10]) # !dpm_ni2f_reg_sm_1 & M1_lt_adr[11];

--A1L626 is ix2262_lc~0
--operation mode is normal

A1L626 = dpm_ni2f_reg_sm_1 & (E9_q[10]) # !dpm_ni2f_reg_sm_1 & M1_lt_adr[11];


--G1_ad_ir_address[12] is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[12]
--operation mode is normal

G1_ad_ir_address[12] = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_12, pci_rstn, GLOBAL(pci_clk));

--G1L621Q is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[12]~74
--operation mode is normal

G1L621Q = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_12, pci_rstn, GLOBAL(pci_clk));


--M1_lt_adr[12] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_adr[12]
--operation mode is normal

M1_lt_adr[12] = AMPP_FUNCTION(M1_no_op_reg[1], G1_ad_ir_address[12]);

--M1L553 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_adr[12]~136
--operation mode is normal

M1L553 = AMPP_FUNCTION(M1_no_op_reg[1], G1_ad_ir_address[12]);


--E9_q[11] is lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[11]
--operation mode is clrb_cntr

E9_q[11]_lut_out = (E9_q[11] $ (dpm_ni2f_reg_rdreq_fifo & E9L32)) & A1L905;
E9_q[11] = DFFEA(E9_q[11]_lut_out, lcst, , , , , );

--E9L16Q is lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[11]~11
--operation mode is clrb_cntr

E9L16Q = E9_q[11];

--E9L52 is lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|counter_cell[11]~COUT
--operation mode is clrb_cntr

E9L52 = CARRY(E9_q[11] & (E9L32));


--ix2261_lc is ix2261_lc
--operation mode is normal

ix2261_lc = dpm_ni2f_reg_sm_1 & (E9_q[11]) # !dpm_ni2f_reg_sm_1 & M1_lt_adr[12];

--A1L326 is ix2261_lc~0
--operation mode is normal

A1L326 = dpm_ni2f_reg_sm_1 & (E9_q[11]) # !dpm_ni2f_reg_sm_1 & M1_lt_adr[12];


--G1_ad_ir_address[13] is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[13]
--operation mode is normal

G1_ad_ir_address[13] = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_13, pci_rstn, GLOBAL(pci_clk));

--G1L821Q is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[13]~75
--operation mode is normal

G1L821Q = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_13, pci_rstn, GLOBAL(pci_clk));


--M1_lt_adr[13] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_adr[13]
--operation mode is normal

M1_lt_adr[13] = AMPP_FUNCTION(M1_no_op_reg[1], G1_ad_ir_address[13]);

--M1L753 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_adr[13]~137
--operation mode is normal

M1L753 = AMPP_FUNCTION(M1_no_op_reg[1], G1_ad_ir_address[13]);


--E9_q[12] is lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[12]
--operation mode is clrb_cntr

E9_q[12]_lut_out = (E9_q[12] $ (dpm_ni2f_reg_rdreq_fifo & E9L52)) & A1L905;
E9_q[12] = DFFEA(E9_q[12]_lut_out, lcst, , , , , );

--E9L36Q is lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[12]~12
--operation mode is clrb_cntr

E9L36Q = E9_q[12];

--E9L72 is lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|counter_cell[12]~COUT
--operation mode is clrb_cntr

E9L72 = CARRY(E9_q[12] & (E9L52));


--ix2260_lc is ix2260_lc
--operation mode is normal

ix2260_lc = dpm_ni2f_reg_sm_1 & (E9_q[12]) # !dpm_ni2f_reg_sm_1 & M1_lt_adr[13];

--A1L026 is ix2260_lc~0
--operation mode is normal

A1L026 = dpm_ni2f_reg_sm_1 & (E9_q[12]) # !dpm_ni2f_reg_sm_1 & M1_lt_adr[13];


--G1_ad_ir_address[14] is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[14]
--operation mode is normal

G1_ad_ir_address[14] = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_14, pci_rstn, GLOBAL(pci_clk));

--G1L031Q is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[14]~76
--operation mode is normal

G1L031Q = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_14, pci_rstn, GLOBAL(pci_clk));


--M1_lt_adr[14] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_adr[14]
--operation mode is normal

M1_lt_adr[14] = AMPP_FUNCTION(M1_no_op_reg[1], G1_ad_ir_address[14]);

--M1L953 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_adr[14]~138
--operation mode is normal

M1L953 = AMPP_FUNCTION(M1_no_op_reg[1], G1_ad_ir_address[14]);


--E9_q[13] is lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[13]
--operation mode is clrb_cntr

E9_q[13]_lut_out = (E9_q[13] $ (dpm_ni2f_reg_rdreq_fifo & E9L72)) & A1L905;
E9_q[13] = DFFEA(E9_q[13]_lut_out, lcst, , , , , );

--E9L56Q is lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[13]~13
--operation mode is clrb_cntr

E9L56Q = E9_q[13];

--E9L92 is lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|counter_cell[13]~COUT
--operation mode is clrb_cntr

E9L92 = CARRY(E9_q[13] & (E9L72));


--ix2259_lc is ix2259_lc
--operation mode is normal

ix2259_lc = dpm_ni2f_reg_sm_1 & (E9_q[13]) # !dpm_ni2f_reg_sm_1 & M1_lt_adr[14];

--A1L716 is ix2259_lc~0
--operation mode is normal

A1L716 = dpm_ni2f_reg_sm_1 & (E9_q[13]) # !dpm_ni2f_reg_sm_1 & M1_lt_adr[14];


--G1_ad_ir_address[15] is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[15]
--operation mode is normal

G1_ad_ir_address[15] = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_15, pci_rstn, GLOBAL(pci_clk));

--G1L231Q is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[15]~77
--operation mode is normal

G1L231Q = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_15, pci_rstn, GLOBAL(pci_clk));


--M1_lt_adr[15] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_adr[15]
--operation mode is normal

M1_lt_adr[15] = AMPP_FUNCTION(M1_no_op_reg[1], G1_ad_ir_address[15]);

--M1L163 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_adr[15]~139
--operation mode is normal

M1L163 = AMPP_FUNCTION(M1_no_op_reg[1], G1_ad_ir_address[15]);


--E9_q[14] is lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[14]
--operation mode is clrb_cntr

E9_q[14]_lut_out = (E9_q[14] $ (dpm_ni2f_reg_rdreq_fifo & E9L92)) & A1L905;
E9_q[14] = DFFEA(E9_q[14]_lut_out, lcst, , , , , );

--E9L76Q is lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[14]~14
--operation mode is clrb_cntr

E9L76Q = E9_q[14];

--E9L13 is lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|counter_cell[14]~COUT
--operation mode is clrb_cntr

E9L13 = CARRY(E9_q[14] & (E9L92));


--ix2258_lc is ix2258_lc
--operation mode is normal

ix2258_lc = dpm_ni2f_reg_sm_1 & (E9_q[14]) # !dpm_ni2f_reg_sm_1 & M1_lt_adr[15];

--A1L416 is ix2258_lc~0
--operation mode is normal

A1L416 = dpm_ni2f_reg_sm_1 & (E9_q[14]) # !dpm_ni2f_reg_sm_1 & M1_lt_adr[15];


--G1_ad_ir_address[16] is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[16]
--operation mode is normal

G1_ad_ir_address[16] = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_16, pci_rstn, GLOBAL(pci_clk));

--G1L431Q is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[16]~78
--operation mode is normal

G1L431Q = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_16, pci_rstn, GLOBAL(pci_clk));


--M1_lt_adr[16] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_adr[16]
--operation mode is normal

M1_lt_adr[16] = AMPP_FUNCTION(M1_no_op_reg[1], G1_ad_ir_address[16]);

--M1L363 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_adr[16]~140
--operation mode is normal

M1L363 = AMPP_FUNCTION(M1_no_op_reg[1], G1_ad_ir_address[16]);


--E9_q[15] is lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[15]
--operation mode is clrb_cntr

E9_q[15]_lut_out = (E9_q[15] $ (dpm_ni2f_reg_rdreq_fifo & E9L13)) & A1L905;
E9_q[15] = DFFEA(E9_q[15]_lut_out, lcst, , , , , );

--E9L96Q is lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[15]~15
--operation mode is clrb_cntr

E9L96Q = E9_q[15];

--E9L33 is lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|counter_cell[15]~COUT
--operation mode is clrb_cntr

E9L33 = CARRY(E9_q[15] & (E9L13));


--ix2257_lc is ix2257_lc
--operation mode is normal

ix2257_lc = dpm_ni2f_reg_sm_1 & (E9_q[15]) # !dpm_ni2f_reg_sm_1 & M1_lt_adr[16];

--A1L116 is ix2257_lc~0
--operation mode is normal

A1L116 = dpm_ni2f_reg_sm_1 & (E9_q[15]) # !dpm_ni2f_reg_sm_1 & M1_lt_adr[16];


--G1_ad_ir_address[17] is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[17]
--operation mode is normal

G1_ad_ir_address[17] = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_17, pci_rstn, GLOBAL(pci_clk));

--G1L631Q is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[17]~79
--operation mode is normal

G1L631Q = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_17, pci_rstn, GLOBAL(pci_clk));


--M1_lt_adr[17] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_adr[17]
--operation mode is normal

M1_lt_adr[17] = AMPP_FUNCTION(M1_no_op_reg[1], G1_ad_ir_address[17]);

--M1L563 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_adr[17]~141
--operation mode is normal

M1L563 = AMPP_FUNCTION(M1_no_op_reg[1], G1_ad_ir_address[17]);


--E9_q[16] is lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[16]
--operation mode is clrb_cntr

E9_q[16]_lut_out = (E9_q[16] $ (dpm_ni2f_reg_rdreq_fifo & E9L33)) & A1L905;
E9_q[16] = DFFEA(E9_q[16]_lut_out, lcst, , , , , );

--E9L17Q is lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[16]~16
--operation mode is clrb_cntr

E9L17Q = E9_q[16];

--E9L53 is lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|counter_cell[16]~COUT
--operation mode is clrb_cntr

E9L53 = CARRY(E9_q[16] & (E9L33));


--ix2256_lc is ix2256_lc
--operation mode is normal

ix2256_lc = dpm_ni2f_reg_sm_1 & (E9_q[16]) # !dpm_ni2f_reg_sm_1 & M1_lt_adr[17];

--A1L806 is ix2256_lc~0
--operation mode is normal

A1L806 = dpm_ni2f_reg_sm_1 & (E9_q[16]) # !dpm_ni2f_reg_sm_1 & M1_lt_adr[17];


--G1_ad_ir_address[18] is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[18]
--operation mode is normal

G1_ad_ir_address[18] = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_18, pci_rstn, GLOBAL(pci_clk));

--G1L831Q is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[18]~80
--operation mode is normal

G1L831Q = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_18, pci_rstn, GLOBAL(pci_clk));


--M1_lt_adr[18] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_adr[18]
--operation mode is normal

M1_lt_adr[18] = AMPP_FUNCTION(M1_no_op_reg[1], G1_ad_ir_address[18]);

--M1L763 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_adr[18]~142
--operation mode is normal

M1L763 = AMPP_FUNCTION(M1_no_op_reg[1], G1_ad_ir_address[18]);


--E9_q[17] is lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[17]
--operation mode is clrb_cntr

E9_q[17]_lut_out = (E9_q[17] $ (dpm_ni2f_reg_rdreq_fifo & E9L53)) & A1L905;
E9_q[17] = DFFEA(E9_q[17]_lut_out, lcst, , , , , );

--E9L37Q is lpm_counter:dpm_ni2f_wcounter_ix7|alt_counter_f10ke:wysi_counter|q[17]~17
--operation mode is clrb_cntr

E9L37Q = E9_q[17];


--ix2255_lc is ix2255_lc
--operation mode is normal

ix2255_lc = dpm_ni2f_reg_sm_1 & (E9_q[17]) # !dpm_ni2f_reg_sm_1 & M1_lt_adr[18];

--A1L506 is ix2255_lc~0
--operation mode is normal

A1L506 = dpm_ni2f_reg_sm_1 & (E9_q[17]) # !dpm_ni2f_reg_sm_1 & M1_lt_adr[18];


--dpm_ni2f_reg_sm_10 is dpm_ni2f_reg_sm_10
--operation mode is normal

dpm_ni2f_reg_sm_10_lut_out = dpm_ni2f_reg_sm_9;
dpm_ni2f_reg_sm_10 = DFFEA(dpm_ni2f_reg_sm_10_lut_out, lcst, !ix2254, , , , );

--A1L144Q is dpm_ni2f_reg_sm_10~1
--operation mode is normal

A1L144Q = dpm_ni2f_reg_sm_10;


--dpm_ni2f_reg_pci_rd_req_s is dpm_ni2f_reg_pci_rd_req_s
--operation mode is normal

dpm_ni2f_reg_pci_rd_req_s_lut_out = (M1_lt_adr[19] & !G1_cben_ir_address[0] & M1L133 & M1_lt_tsr[0]) & CASCADE(A1L887);
dpm_ni2f_reg_pci_rd_req_s = DFFEA(dpm_ni2f_reg_pci_rd_req_s_lut_out, lcst, , , , , );

--A1L714Q is dpm_ni2f_reg_pci_rd_req_s~0
--operation mode is normal

A1L714Q = dpm_ni2f_reg_pci_rd_req_s;


--ix2325 is ix2325
--operation mode is normal

ix2325 = !dpm_ni2f_reg_sm_11 & dpm_ni2f_reg_sm_0;

--A1L397 is ix2325~1
--operation mode is normal

A1L397 = !dpm_ni2f_reg_sm_11 & dpm_ni2f_reg_sm_0;

--A1L497 is ix2325~2
--operation mode is normal

A1L497 = !dpm_ni2f_reg_sm_11 & dpm_ni2f_reg_sm_0;


--dpm_ni2f_reg_sm_3 is dpm_ni2f_reg_sm_3
--operation mode is normal

dpm_ni2f_reg_sm_3_lut_out = !ix2315_lc;
dpm_ni2f_reg_sm_3 = DFFEA(dpm_ni2f_reg_sm_3_lut_out, lcst, !ix2254, , , , );

--A1L724Q is dpm_ni2f_reg_sm_3~1
--operation mode is normal

A1L724Q = dpm_ni2f_reg_sm_3;


--G1_low_ad_or[0] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[0]
--operation mode is normal

G1_low_ad_or[0] = AMPP_FUNCTION(H1_ad_ce[0], G1_mstr_trg_low, A1L575, G1L053, pci_rstn, GLOBAL(pci_clk));

--G1L782Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[0]~96
--operation mode is normal

G1L782Q = AMPP_FUNCTION(H1_ad_ce[0], G1_mstr_trg_low, A1L575, G1L053, pci_rstn, GLOBAL(pci_clk));


--M1_adoe is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|adoe
--operation mode is normal

M1_adoe = AMPP_FUNCTION(M1_TS_IDLE_NOT, M1_TS_TURN_AR, N3_REG, pci_rstn, GLOBAL(pci_clk), M1L6);

--M1L631Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|adoe~17
--operation mode is normal

M1L631Q = AMPP_FUNCTION(M1_TS_IDLE_NOT, M1_TS_TURN_AR, N3_REG, pci_rstn, GLOBAL(pci_clk), M1L6);


--J1_ad_oer is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|ad_oer
--operation mode is normal

J1_ad_oer = AMPP_FUNCTION(A1L5421, A1L7421, GND, J1_ad_oer_lc3, !pci_rstn, GLOBAL(pci_clk), J1L78);

--J1L021Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|ad_oer~17
--operation mode is normal

J1L021Q = AMPP_FUNCTION(A1L5421, A1L7421, GND, J1_ad_oer_lc3, !pci_rstn, GLOBAL(pci_clk), J1L78);


--G1_ad_tri_oe is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_tri_oe
--operation mode is normal

G1_ad_tri_oe = AMPP_FUNCTION(M1_adoe, J1_ad_oer);

--G1L271 is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_tri_oe~0
--operation mode is normal

G1L271 = AMPP_FUNCTION(M1_adoe, J1_ad_oer);


--G1_low_ad_or[1] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[1]
--operation mode is normal

G1_low_ad_or[1] = AMPP_FUNCTION(H1_ad_ce[1], G1_mstr_trg_low, A1L375, G1L253, pci_rstn, GLOBAL(pci_clk));

--G1L982Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[1]~97
--operation mode is normal

G1L982Q = AMPP_FUNCTION(H1_ad_ce[1], G1_mstr_trg_low, A1L375, G1L253, pci_rstn, GLOBAL(pci_clk));


--G1_low_ad_or[2] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[2]
--operation mode is normal

G1_low_ad_or[2] = AMPP_FUNCTION(H1_ad_ce[2], G1_mstr_trg_low, A1L175, G1L453, pci_rstn, GLOBAL(pci_clk));

--G1L192Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[2]~98
--operation mode is normal

G1L192Q = AMPP_FUNCTION(H1_ad_ce[2], G1_mstr_trg_low, A1L175, G1L453, pci_rstn, GLOBAL(pci_clk));


--G1_low_ad_or[3] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[3]
--operation mode is normal

G1_low_ad_or[3] = AMPP_FUNCTION(H1_ad_ce[3], G1_mstr_trg_low, A1L965, G1L653, pci_rstn, GLOBAL(pci_clk));

--G1L392Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[3]~99
--operation mode is normal

G1L392Q = AMPP_FUNCTION(H1_ad_ce[3], G1_mstr_trg_low, A1L965, G1L653, pci_rstn, GLOBAL(pci_clk));


--G1_low_ad_or[4] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[4]
--operation mode is normal

G1_low_ad_or[4] = AMPP_FUNCTION(H1_ad_ce[4], G1_mstr_trg_low, A1L765, G1L853, pci_rstn, GLOBAL(pci_clk));

--G1L592Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[4]~100
--operation mode is normal

G1L592Q = AMPP_FUNCTION(H1_ad_ce[4], G1_mstr_trg_low, A1L765, G1L853, pci_rstn, GLOBAL(pci_clk));


--G1_low_ad_or[5] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[5]
--operation mode is normal

G1_low_ad_or[5] = AMPP_FUNCTION(H1_ad_ce[5], G1_mstr_trg_low, A1L565, G1L063, pci_rstn, GLOBAL(pci_clk));

--G1L792Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[5]~101
--operation mode is normal

G1L792Q = AMPP_FUNCTION(H1_ad_ce[5], G1_mstr_trg_low, A1L565, G1L063, pci_rstn, GLOBAL(pci_clk));


--G1_low_ad_or[6] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[6]
--operation mode is normal

G1_low_ad_or[6] = AMPP_FUNCTION(H1_ad_ce[6], G1_mstr_trg_low, A1L365, G1L263, pci_rstn, GLOBAL(pci_clk));

--G1L992Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[6]~102
--operation mode is normal

G1L992Q = AMPP_FUNCTION(H1_ad_ce[6], G1_mstr_trg_low, A1L365, G1L263, pci_rstn, GLOBAL(pci_clk));


--G1_low_ad_or[7] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[7]
--operation mode is normal

G1_low_ad_or[7] = AMPP_FUNCTION(H1_ad_ce[7], G1_mstr_trg_low, A1L165, G1L463, pci_rstn, GLOBAL(pci_clk));

--G1L103Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[7]~103
--operation mode is normal

G1L103Q = AMPP_FUNCTION(H1_ad_ce[7], G1_mstr_trg_low, A1L165, G1L463, pci_rstn, GLOBAL(pci_clk));


--G1_low_ad_or[8] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[8]
--operation mode is normal

G1_low_ad_or[8] = AMPP_FUNCTION(H1_ad_ce[8], G1_mstr_trg_low, A1L955, G1L663, pci_rstn, GLOBAL(pci_clk));

--G1L303Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[8]~104
--operation mode is normal

G1L303Q = AMPP_FUNCTION(H1_ad_ce[8], G1_mstr_trg_low, A1L955, G1L663, pci_rstn, GLOBAL(pci_clk));


--G1_low_ad_or[9] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[9]
--operation mode is normal

G1_low_ad_or[9] = AMPP_FUNCTION(H1_ad_ce[9], G1_mstr_trg_low, A1L755, G1L863, pci_rstn, GLOBAL(pci_clk));

--G1L503Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[9]~105
--operation mode is normal

G1L503Q = AMPP_FUNCTION(H1_ad_ce[9], G1_mstr_trg_low, A1L755, G1L863, pci_rstn, GLOBAL(pci_clk));


--G1_low_ad_or[10] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[10]
--operation mode is normal

G1_low_ad_or[10] = AMPP_FUNCTION(H1_ad_ce[10], G1_mstr_trg_low, A1L555, G1L073, pci_rstn, GLOBAL(pci_clk));

--G1L703Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[10]~106
--operation mode is normal

G1L703Q = AMPP_FUNCTION(H1_ad_ce[10], G1_mstr_trg_low, A1L555, G1L073, pci_rstn, GLOBAL(pci_clk));


--G1_low_ad_or[11] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[11]
--operation mode is normal

G1_low_ad_or[11] = AMPP_FUNCTION(H1_ad_ce[11], G1_mstr_trg_low, A1L355, G1L273, pci_rstn, GLOBAL(pci_clk));

--G1L903Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[11]~107
--operation mode is normal

G1L903Q = AMPP_FUNCTION(H1_ad_ce[11], G1_mstr_trg_low, A1L355, G1L273, pci_rstn, GLOBAL(pci_clk));


--G1_low_ad_or[12] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[12]
--operation mode is normal

G1_low_ad_or[12] = AMPP_FUNCTION(H1_ad_ce[12], G1_mstr_trg_low, A1L155, G1L473, pci_rstn, GLOBAL(pci_clk));

--G1L113Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[12]~108
--operation mode is normal

G1L113Q = AMPP_FUNCTION(H1_ad_ce[12], G1_mstr_trg_low, A1L155, G1L473, pci_rstn, GLOBAL(pci_clk));


--G1_low_ad_or[13] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[13]
--operation mode is normal

G1_low_ad_or[13] = AMPP_FUNCTION(H1_ad_ce[13], G1_mstr_trg_low, A1L945, G1L673, pci_rstn, GLOBAL(pci_clk));

--G1L313Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[13]~109
--operation mode is normal

G1L313Q = AMPP_FUNCTION(H1_ad_ce[13], G1_mstr_trg_low, A1L945, G1L673, pci_rstn, GLOBAL(pci_clk));


--G1_low_ad_or[14] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[14]
--operation mode is normal

G1_low_ad_or[14] = AMPP_FUNCTION(H1_ad_ce[14], G1_mstr_trg_low, A1L745, G1L873, pci_rstn, GLOBAL(pci_clk));

--G1L513Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[14]~110
--operation mode is normal

G1L513Q = AMPP_FUNCTION(H1_ad_ce[14], G1_mstr_trg_low, A1L745, G1L873, pci_rstn, GLOBAL(pci_clk));


--G1_low_ad_or[15] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[15]
--operation mode is normal

G1_low_ad_or[15] = AMPP_FUNCTION(H1_ad_ce[15], G1_mstr_trg_low, A1L545, G1L083, pci_rstn, GLOBAL(pci_clk));

--G1L713Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[15]~111
--operation mode is normal

G1L713Q = AMPP_FUNCTION(H1_ad_ce[15], G1_mstr_trg_low, A1L545, G1L083, pci_rstn, GLOBAL(pci_clk));


--G1_low_ad_or[16] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[16]
--operation mode is normal

G1_low_ad_or[16] = AMPP_FUNCTION(H1_ad_ce[16], G1_mstr_trg_low, A1L345, G1L283, pci_rstn, GLOBAL(pci_clk));

--G1L913Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[16]~112
--operation mode is normal

G1L913Q = AMPP_FUNCTION(H1_ad_ce[16], G1_mstr_trg_low, A1L345, G1L283, pci_rstn, GLOBAL(pci_clk));


--G1_low_ad_or[17] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[17]
--operation mode is normal

G1_low_ad_or[17] = AMPP_FUNCTION(H1_ad_ce[17], G1_mstr_trg_low, A1L145, G1L483, pci_rstn, GLOBAL(pci_clk));

--G1L123Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[17]~113
--operation mode is normal

G1L123Q = AMPP_FUNCTION(H1_ad_ce[17], G1_mstr_trg_low, A1L145, G1L483, pci_rstn, GLOBAL(pci_clk));


--G1_low_ad_or[18] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[18]
--operation mode is normal

G1_low_ad_or[18] = AMPP_FUNCTION(H1_ad_ce[18], G1_mstr_trg_low, A1L935, G1L683, pci_rstn, GLOBAL(pci_clk));

--G1L323Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[18]~114
--operation mode is normal

G1L323Q = AMPP_FUNCTION(H1_ad_ce[18], G1_mstr_trg_low, A1L935, G1L683, pci_rstn, GLOBAL(pci_clk));


--G1_low_ad_or[19] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[19]
--operation mode is normal

G1_low_ad_or[19] = AMPP_FUNCTION(H1_ad_ce[19], G1_mstr_trg_low, A1L735, G1L883, pci_rstn, GLOBAL(pci_clk));

--G1L523Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[19]~115
--operation mode is normal

G1L523Q = AMPP_FUNCTION(H1_ad_ce[19], G1_mstr_trg_low, A1L735, G1L883, pci_rstn, GLOBAL(pci_clk));


--G1_low_ad_or[20] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[20]
--operation mode is normal

G1_low_ad_or[20] = AMPP_FUNCTION(H1_ad_ce[20], G1_mstr_trg_low, A1L535, G1L093, pci_rstn, GLOBAL(pci_clk));

--G1L723Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[20]~116
--operation mode is normal

G1L723Q = AMPP_FUNCTION(H1_ad_ce[20], G1_mstr_trg_low, A1L535, G1L093, pci_rstn, GLOBAL(pci_clk));


--G1_low_ad_or[21] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[21]
--operation mode is normal

G1_low_ad_or[21] = AMPP_FUNCTION(H1_ad_ce[21], G1_mstr_trg_low, A1L335, G1L293, pci_rstn, GLOBAL(pci_clk));

--G1L923Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[21]~117
--operation mode is normal

G1L923Q = AMPP_FUNCTION(H1_ad_ce[21], G1_mstr_trg_low, A1L335, G1L293, pci_rstn, GLOBAL(pci_clk));


--G1_low_ad_or[22] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[22]
--operation mode is normal

G1_low_ad_or[22] = AMPP_FUNCTION(H1_ad_ce[22], G1_mstr_trg_low, A1L135, G1L493, pci_rstn, GLOBAL(pci_clk));

--G1L133Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[22]~118
--operation mode is normal

G1L133Q = AMPP_FUNCTION(H1_ad_ce[22], G1_mstr_trg_low, A1L135, G1L493, pci_rstn, GLOBAL(pci_clk));


--G1_low_ad_or[23] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[23]
--operation mode is normal

G1_low_ad_or[23] = AMPP_FUNCTION(H1_ad_ce[23], G1_mstr_trg_low, A1L925, G1L693, pci_rstn, GLOBAL(pci_clk));

--G1L333Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[23]~119
--operation mode is normal

G1L333Q = AMPP_FUNCTION(H1_ad_ce[23], G1_mstr_trg_low, A1L925, G1L693, pci_rstn, GLOBAL(pci_clk));


--G1_low_ad_or[24] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[24]
--operation mode is normal

G1_low_ad_or[24] = AMPP_FUNCTION(H1_ad_ce[24], G1_mstr_trg_low, A1L725, G1L893, pci_rstn, GLOBAL(pci_clk));

--G1L533Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[24]~120
--operation mode is normal

G1L533Q = AMPP_FUNCTION(H1_ad_ce[24], G1_mstr_trg_low, A1L725, G1L893, pci_rstn, GLOBAL(pci_clk));


--G1_low_ad_or[25] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[25]
--operation mode is normal

G1_low_ad_or[25] = AMPP_FUNCTION(H1_ad_ce[25], G1_mstr_trg_low, A1L525, G1L004, pci_rstn, GLOBAL(pci_clk));

--G1L733Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[25]~121
--operation mode is normal

G1L733Q = AMPP_FUNCTION(H1_ad_ce[25], G1_mstr_trg_low, A1L525, G1L004, pci_rstn, GLOBAL(pci_clk));


--G1_low_ad_or[26] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[26]
--operation mode is normal

G1_low_ad_or[26] = AMPP_FUNCTION(H1_ad_ce[26], G1_mstr_trg_low, A1L325, G1L204, pci_rstn, GLOBAL(pci_clk));

--G1L933Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[26]~122
--operation mode is normal

G1L933Q = AMPP_FUNCTION(H1_ad_ce[26], G1_mstr_trg_low, A1L325, G1L204, pci_rstn, GLOBAL(pci_clk));


--G1_low_ad_or[27] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[27]
--operation mode is normal

G1_low_ad_or[27] = AMPP_FUNCTION(H1_ad_ce[27], G1_mstr_trg_low, A1L125, G1L404, pci_rstn, GLOBAL(pci_clk));

--G1L143Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[27]~123
--operation mode is normal

G1L143Q = AMPP_FUNCTION(H1_ad_ce[27], G1_mstr_trg_low, A1L125, G1L404, pci_rstn, GLOBAL(pci_clk));


--G1_low_ad_or[28] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[28]
--operation mode is normal

G1_low_ad_or[28] = AMPP_FUNCTION(H1_ad_ce[28], G1_mstr_trg_low, A1L915, G1L604, pci_rstn, GLOBAL(pci_clk));

--G1L343Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[28]~124
--operation mode is normal

G1L343Q = AMPP_FUNCTION(H1_ad_ce[28], G1_mstr_trg_low, A1L915, G1L604, pci_rstn, GLOBAL(pci_clk));


--G1_low_ad_or[29] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[29]
--operation mode is normal

G1_low_ad_or[29] = AMPP_FUNCTION(H1_ad_ce[29], G1_mstr_trg_low, A1L715, G1L804, pci_rstn, GLOBAL(pci_clk));

--G1L543Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[29]~125
--operation mode is normal

G1L543Q = AMPP_FUNCTION(H1_ad_ce[29], G1_mstr_trg_low, A1L715, G1L804, pci_rstn, GLOBAL(pci_clk));


--G1_low_ad_or[30] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[30]
--operation mode is normal

G1_low_ad_or[30] = AMPP_FUNCTION(H1_ad_ce[30], G1_mstr_trg_low, A1L515, G1L014, pci_rstn, GLOBAL(pci_clk));

--G1L743Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[30]~126
--operation mode is normal

G1L743Q = AMPP_FUNCTION(H1_ad_ce[30], G1_mstr_trg_low, A1L515, G1L014, pci_rstn, GLOBAL(pci_clk));


--G1_low_ad_or[31] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[31]
--operation mode is normal

G1_low_ad_or[31] = AMPP_FUNCTION(H1_ad_ce[31], G1_mstr_trg_low, A1L315, G1L214, pci_rstn, GLOBAL(pci_clk));

--G1L943Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_or[31]~127
--operation mode is normal

G1L943Q = AMPP_FUNCTION(H1_ad_ce[31], G1_mstr_trg_low, A1L315, G1L214, pci_rstn, GLOBAL(pci_clk));


--G1_low_cben_or[0] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_cben_or[0]
--operation mode is normal

G1_low_cben_or[0] = AMPP_FUNCTION(G1_mstr_cbe_ce, G1_low_mstr_cbe_out_lc1[0], pci_rstn, GLOBAL(pci_clk));

--G1L524Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_cben_or[0]~4
--operation mode is normal

G1L524Q = AMPP_FUNCTION(G1_mstr_cbe_ce, G1_low_mstr_cbe_out_lc1[0], pci_rstn, GLOBAL(pci_clk));


--J1_cbe_oer_not is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|cbe_oer_not
--operation mode is normal

J1_cbe_oer_not = AMPP_FUNCTION(A1L5421, A1L7421, GND, J1_cbe_oer_r3_d, !pci_rstn, GLOBAL(pci_clk), J1L98);

--J1L131Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|cbe_oer_not~10
--operation mode is normal

J1L131Q = AMPP_FUNCTION(A1L5421, A1L7421, GND, J1_cbe_oer_r3_d, !pci_rstn, GLOBAL(pci_clk), J1L98);


--G1_low_cben_or[1] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_cben_or[1]
--operation mode is normal

G1_low_cben_or[1] = AMPP_FUNCTION(G1_mstr_cbe_ce, G1_low_mstr_cbe_out_lc1[1], pci_rstn, GLOBAL(pci_clk));

--G1L724Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_cben_or[1]~5
--operation mode is normal

G1L724Q = AMPP_FUNCTION(G1_mstr_cbe_ce, G1_low_mstr_cbe_out_lc1[1], pci_rstn, GLOBAL(pci_clk));


--G1_low_cben_or[2] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_cben_or[2]
--operation mode is normal

G1_low_cben_or[2] = AMPP_FUNCTION(G1_mstr_cbe_ce, G1_low_mstr_cbe_out_lc1[2], pci_rstn, GLOBAL(pci_clk));

--G1L924Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_cben_or[2]~6
--operation mode is normal

G1L924Q = AMPP_FUNCTION(G1_mstr_cbe_ce, G1_low_mstr_cbe_out_lc1[2], pci_rstn, GLOBAL(pci_clk));


--G1_low_cben_or[3] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_cben_or[3]
--operation mode is normal

G1_low_cben_or[3] = AMPP_FUNCTION(G1_mstr_cbe_ce, G1_low_mstr_cbe_out_lc1[3], pci_rstn, GLOBAL(pci_clk));

--G1L134Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_cben_or[3]~7
--operation mode is normal

G1L134Q = AMPP_FUNCTION(G1_mstr_cbe_ce, G1_low_mstr_cbe_out_lc1[3], pci_rstn, GLOBAL(pci_clk));


--M1_devsel_OR_not is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|devsel_OR_not
--operation mode is normal

M1_devsel_OR_not = AMPP_FUNCTION(M1L58, M1_TS_ADR_VLD, GND, K1_serr_or, !pci_rstn, GLOBAL(pci_clk), M1L09);

--M1L181Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|devsel_OR_not~0
--operation mode is normal

M1L181Q = AMPP_FUNCTION(M1L58, M1_TS_ADR_VLD, GND, K1_serr_or, !pci_rstn, GLOBAL(pci_clk), M1L09);


--M1_targ_oeR_reg is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|targ_oeR_reg
--operation mode is normal

M1_targ_oeR_reg = AMPP_FUNCTION(M1_targ_oeR_reg_lc[4], P1_mbar_hit, M1_TS_IDLE_NOT, pci_rstn, GLOBAL(pci_clk));

--M1L684Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|targ_oeR_reg~1
--operation mode is normal

M1L684Q = AMPP_FUNCTION(M1_targ_oeR_reg_lc[4], P1_mbar_hit, M1_TS_IDLE_NOT, pci_rstn, GLOBAL(pci_clk));


--J1_frame_or_not is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|frame_or_not
--operation mode is normal

J1_frame_or_not = AMPP_FUNCTION(J1_dac_cyc_strobe, J1_MS_ENA, GND, pci_gntn, !pci_rstn, GLOBAL(pci_clk), J1L19);

--J1L412Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|frame_or_not~14
--operation mode is normal

J1L412Q = AMPP_FUNCTION(J1_dac_cyc_strobe, J1_MS_ENA, GND, pci_gntn, !pci_rstn, GLOBAL(pci_clk), J1L19);


--J1_irdy_or_not is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|irdy_or_not
--operation mode is normal

J1_irdy_or_not = AMPP_FUNCTION(J1_irdy_or_lc[5], A1L8221, GND, J1L31, !pci_rstn, GLOBAL(pci_clk), J1L02);

--J1L152Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|irdy_or_not~16
--operation mode is normal

J1L152Q = AMPP_FUNCTION(J1_irdy_or_lc[5], A1L8221, GND, J1L31, !pci_rstn, GLOBAL(pci_clk), J1L02);


--J1_irdy_oer is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|irdy_oer
--operation mode is normal

J1_irdy_oer = AMPP_FUNCTION(J1_irdy_oer_lc1, J1_MS_ENA, pci_gntn, pci_rstn, GLOBAL(pci_clk));

--J1L422Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|irdy_oer~4
--operation mode is normal

J1L422Q = AMPP_FUNCTION(J1_irdy_oer_lc1, J1_MS_ENA, pci_gntn, pci_rstn, GLOBAL(pci_clk));


--G1_par_or is pci_contr:pci|pci_mt32:pci_mt32_inst|par_or
--operation mode is normal

G1_par_or = AMPP_FUNCTION(pci_cben_0, pci_cben_1, pci_rstn, GLOBAL(pci_clk), L1L83);

--G1L045Q is pci_contr:pci|pci_mt32:pci_mt32_inst|par_or~0
--operation mode is normal

G1L045Q = AMPP_FUNCTION(pci_cben_0, pci_cben_1, pci_rstn, GLOBAL(pci_clk), L1L83);


--G1_par_oeR is pci_contr:pci|pci_mt32:pci_mt32_inst|par_oeR
--operation mode is normal

G1_par_oeR = AMPP_FUNCTION(G1_mstr_par_oe_lc2, J1_MS_ENA, pci_gntn, pci_rstn, GLOBAL(pci_clk));

--G1L835Q is pci_contr:pci|pci_mt32:pci_mt32_inst|par_oeR~1
--operation mode is normal

G1L835Q = AMPP_FUNCTION(G1_mstr_par_oe_lc2, J1_MS_ENA, pci_gntn, pci_rstn, GLOBAL(pci_clk));


--K1_perr_or_not is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|perr_or_not
--operation mode is normal

K1_perr_or_not = AMPP_FUNCTION(K1_perr_or_not_lc1, A1L8321, K1_xxl[11], pci_rstn, GLOBAL(pci_clk));

--K1L9Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|perr_or_not~22
--operation mode is normal

K1L9Q = AMPP_FUNCTION(K1_perr_or_not_lc1, A1L8321, K1_xxl[11], pci_rstn, GLOBAL(pci_clk));


--G1_perr_oe_r is pci_contr:pci|pci_mt32:pci_mt32_inst|perr_oe_r
--operation mode is normal

G1_perr_oe_r = AMPP_FUNCTION(J1_perr_oer, N3_REG, M1_TS_IDLE_NOT, M1_TURN_AR_R, pci_rstn, GLOBAL(pci_clk));

--G1L245Q is pci_contr:pci|pci_mt32:pci_mt32_inst|perr_oe_r~11
--operation mode is normal

G1L245Q = AMPP_FUNCTION(J1_perr_oer, N3_REG, M1_TS_IDLE_NOT, M1_TURN_AR_R, pci_rstn, GLOBAL(pci_clk));


--M1_stop_OR_NOT is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|stop_OR_NOT
--operation mode is normal

M1_stop_OR_NOT = AMPP_FUNCTION(M1_stop_or_lc[6], M1_stop_or_lc[5], GND, A1L0321, !pci_rstn, GLOBAL(pci_clk), M1L39);

--M1L864Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|stop_OR_NOT~7
--operation mode is normal

M1L864Q = AMPP_FUNCTION(M1_stop_or_lc[6], M1_stop_or_lc[5], GND, A1L0321, !pci_rstn, GLOBAL(pci_clk), M1L39);


--M1_trdy_OR_NOT is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|trdy_OR_NOT
--operation mode is normal

M1_trdy_OR_NOT = AMPP_FUNCTION(M1L78, GND, A1L0321, !pci_rstn, GLOBAL(pci_clk), M1L59);

--M1L505Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|trdy_OR_NOT~2
--operation mode is normal

M1L505Q = AMPP_FUNCTION(M1L78, GND, A1L0321, !pci_rstn, GLOBAL(pci_clk), M1L59);


--F2_q[0] is dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[0]
F2_q[0]_data_in = dpm_ni2f_reg_des_data_rr_0;
F2_q[0]_write_enable = dpm_ni2f_reg_des_valid_data;
F2_q[0]_clock_0 = lcst;
F2_q[0]_clock_1 = lcst;
F2_q[0]_write_address = WR_ADDR(E7_q[0], E7_q[1], E7_q[2], E7_q[3], E7_q[4], E7_q[5], E7_q[6], E7_q[7], E7_q[8], E7_q[9], E7_q[10]);
F2_q[0]_read_address = RD_ADDR(E6_q[0], E6_q[1], E6_q[2], E6_q[3], E6_q[4], E6_q[5], E6_q[6], E6_q[7], E6_q[8], E6_q[9], E6_q[10]);
F2_q[0] = MEMORY_SEGMENT(F2_q[0]_data_in, F2_q[0]_write_enable, F2_q[0]_clock_0, F2_q[0]_clock_1, , , , VCC, F2_q[0]_write_address, F2_q[0]_read_address);


--F2_q[1] is dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[1]
F2_q[1]_data_in = dpm_ni2f_reg_des_data_rr_1;
F2_q[1]_write_enable = dpm_ni2f_reg_des_valid_data;
F2_q[1]_clock_0 = lcst;
F2_q[1]_clock_1 = lcst;
F2_q[1]_write_address = WR_ADDR(E7_q[0], E7_q[1], E7_q[2], E7_q[3], E7_q[4], E7_q[5], E7_q[6], E7_q[7], E7_q[8], E7_q[9], E7_q[10]);
F2_q[1]_read_address = RD_ADDR(E6_q[0], E6_q[1], E6_q[2], E6_q[3], E6_q[4], E6_q[5], E6_q[6], E6_q[7], E6_q[8], E6_q[9], E6_q[10]);
F2_q[1] = MEMORY_SEGMENT(F2_q[1]_data_in, F2_q[1]_write_enable, F2_q[1]_clock_0, F2_q[1]_clock_1, , , , VCC, F2_q[1]_write_address, F2_q[1]_read_address);


--F2_q[2] is dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[2]
F2_q[2]_data_in = dpm_ni2f_reg_des_data_rr_2;
F2_q[2]_write_enable = dpm_ni2f_reg_des_valid_data;
F2_q[2]_clock_0 = lcst;
F2_q[2]_clock_1 = lcst;
F2_q[2]_write_address = WR_ADDR(E7_q[0], E7_q[1], E7_q[2], E7_q[3], E7_q[4], E7_q[5], E7_q[6], E7_q[7], E7_q[8], E7_q[9], E7_q[10]);
F2_q[2]_read_address = RD_ADDR(E6_q[0], E6_q[1], E6_q[2], E6_q[3], E6_q[4], E6_q[5], E6_q[6], E6_q[7], E6_q[8], E6_q[9], E6_q[10]);
F2_q[2] = MEMORY_SEGMENT(F2_q[2]_data_in, F2_q[2]_write_enable, F2_q[2]_clock_0, F2_q[2]_clock_1, , , , VCC, F2_q[2]_write_address, F2_q[2]_read_address);


--F2_q[3] is dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[3]
F2_q[3]_data_in = dpm_ni2f_reg_des_data_rr_3;
F2_q[3]_write_enable = dpm_ni2f_reg_des_valid_data;
F2_q[3]_clock_0 = lcst;
F2_q[3]_clock_1 = lcst;
F2_q[3]_write_address = WR_ADDR(E7_q[0], E7_q[1], E7_q[2], E7_q[3], E7_q[4], E7_q[5], E7_q[6], E7_q[7], E7_q[8], E7_q[9], E7_q[10]);
F2_q[3]_read_address = RD_ADDR(E6_q[0], E6_q[1], E6_q[2], E6_q[3], E6_q[4], E6_q[5], E6_q[6], E6_q[7], E6_q[8], E6_q[9], E6_q[10]);
F2_q[3] = MEMORY_SEGMENT(F2_q[3]_data_in, F2_q[3]_write_enable, F2_q[3]_clock_0, F2_q[3]_clock_1, , , , VCC, F2_q[3]_write_address, F2_q[3]_read_address);


--F2_q[4] is dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[4]
F2_q[4]_data_in = dpm_ni2f_reg_des_data_rr_4;
F2_q[4]_write_enable = dpm_ni2f_reg_des_valid_data;
F2_q[4]_clock_0 = lcst;
F2_q[4]_clock_1 = lcst;
F2_q[4]_write_address = WR_ADDR(E7_q[0], E7_q[1], E7_q[2], E7_q[3], E7_q[4], E7_q[5], E7_q[6], E7_q[7], E7_q[8], E7_q[9], E7_q[10]);
F2_q[4]_read_address = RD_ADDR(E6_q[0], E6_q[1], E6_q[2], E6_q[3], E6_q[4], E6_q[5], E6_q[6], E6_q[7], E6_q[8], E6_q[9], E6_q[10]);
F2_q[4] = MEMORY_SEGMENT(F2_q[4]_data_in, F2_q[4]_write_enable, F2_q[4]_clock_0, F2_q[4]_clock_1, , , , VCC, F2_q[4]_write_address, F2_q[4]_read_address);


--F2_q[5] is dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[5]
F2_q[5]_data_in = dpm_ni2f_reg_des_data_rr_5;
F2_q[5]_write_enable = dpm_ni2f_reg_des_valid_data;
F2_q[5]_clock_0 = lcst;
F2_q[5]_clock_1 = lcst;
F2_q[5]_write_address = WR_ADDR(E7_q[0], E7_q[1], E7_q[2], E7_q[3], E7_q[4], E7_q[5], E7_q[6], E7_q[7], E7_q[8], E7_q[9], E7_q[10]);
F2_q[5]_read_address = RD_ADDR(E6_q[0], E6_q[1], E6_q[2], E6_q[3], E6_q[4], E6_q[5], E6_q[6], E6_q[7], E6_q[8], E6_q[9], E6_q[10]);
F2_q[5] = MEMORY_SEGMENT(F2_q[5]_data_in, F2_q[5]_write_enable, F2_q[5]_clock_0, F2_q[5]_clock_1, , , , VCC, F2_q[5]_write_address, F2_q[5]_read_address);


--F2_q[6] is dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[6]
F2_q[6]_data_in = dpm_ni2f_reg_des_data_rr_6;
F2_q[6]_write_enable = dpm_ni2f_reg_des_valid_data;
F2_q[6]_clock_0 = lcst;
F2_q[6]_clock_1 = lcst;
F2_q[6]_write_address = WR_ADDR(E7_q[0], E7_q[1], E7_q[2], E7_q[3], E7_q[4], E7_q[5], E7_q[6], E7_q[7], E7_q[8], E7_q[9], E7_q[10]);
F2_q[6]_read_address = RD_ADDR(E6_q[0], E6_q[1], E6_q[2], E6_q[3], E6_q[4], E6_q[5], E6_q[6], E6_q[7], E6_q[8], E6_q[9], E6_q[10]);
F2_q[6] = MEMORY_SEGMENT(F2_q[6]_data_in, F2_q[6]_write_enable, F2_q[6]_clock_0, F2_q[6]_clock_1, , , , VCC, F2_q[6]_write_address, F2_q[6]_read_address);


--F2_q[7] is dpram:dpm_ni2f_fifo_l_dpr|altdpram:altdpram_component|q[7]
F2_q[7]_data_in = dpm_ni2f_reg_des_data_rr_7;
F2_q[7]_write_enable = dpm_ni2f_reg_des_valid_data;
F2_q[7]_clock_0 = lcst;
F2_q[7]_clock_1 = lcst;
F2_q[7]_write_address = WR_ADDR(E7_q[0], E7_q[1], E7_q[2], E7_q[3], E7_q[4], E7_q[5], E7_q[6], E7_q[7], E7_q[8], E7_q[9], E7_q[10]);
F2_q[7]_read_address = RD_ADDR(E6_q[0], E6_q[1], E6_q[2], E6_q[3], E6_q[4], E6_q[5], E6_q[6], E6_q[7], E6_q[8], E6_q[9], E6_q[10]);
F2_q[7] = MEMORY_SEGMENT(F2_q[7]_data_in, F2_q[7]_write_enable, F2_q[7]_clock_0, F2_q[7]_clock_1, , , , VCC, F2_q[7]_write_address, F2_q[7]_read_address);


--F1_q[0] is dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[0]
F1_q[0]_data_in = dpm_ni2f_reg_des_data_rr_8;
F1_q[0]_write_enable = dpm_ni2f_reg_des_valid_data;
F1_q[0]_clock_0 = lcst;
F1_q[0]_clock_1 = lcst;
F1_q[0]_write_address = WR_ADDR(E5_q[0], E5_q[1], E5_q[2], E5_q[3], E5_q[4], E5_q[5], E5_q[6], E5_q[7], E5_q[8], E5_q[9], E5_q[10]);
F1_q[0]_read_address = RD_ADDR(E4_q[0], E4_q[1], E4_q[2], E4_q[3], E4_q[4], E4_q[5], E4_q[6], E4_q[7], E4_q[8], E4_q[9], E4_q[10]);
F1_q[0] = MEMORY_SEGMENT(F1_q[0]_data_in, F1_q[0]_write_enable, F1_q[0]_clock_0, F1_q[0]_clock_1, , , , VCC, F1_q[0]_write_address, F1_q[0]_read_address);


--F1_q[1] is dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[1]
F1_q[1]_data_in = dpm_ni2f_reg_des_data_rr_9;
F1_q[1]_write_enable = dpm_ni2f_reg_des_valid_data;
F1_q[1]_clock_0 = lcst;
F1_q[1]_clock_1 = lcst;
F1_q[1]_write_address = WR_ADDR(E5_q[0], E5_q[1], E5_q[2], E5_q[3], E5_q[4], E5_q[5], E5_q[6], E5_q[7], E5_q[8], E5_q[9], E5_q[10]);
F1_q[1]_read_address = RD_ADDR(E4_q[0], E4_q[1], E4_q[2], E4_q[3], E4_q[4], E4_q[5], E4_q[6], E4_q[7], E4_q[8], E4_q[9], E4_q[10]);
F1_q[1] = MEMORY_SEGMENT(F1_q[1]_data_in, F1_q[1]_write_enable, F1_q[1]_clock_0, F1_q[1]_clock_1, , , , VCC, F1_q[1]_write_address, F1_q[1]_read_address);


--F1_q[2] is dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[2]
F1_q[2]_data_in = dpm_ni2f_reg_des_data_rr_10;
F1_q[2]_write_enable = dpm_ni2f_reg_des_valid_data;
F1_q[2]_clock_0 = lcst;
F1_q[2]_clock_1 = lcst;
F1_q[2]_write_address = WR_ADDR(E5_q[0], E5_q[1], E5_q[2], E5_q[3], E5_q[4], E5_q[5], E5_q[6], E5_q[7], E5_q[8], E5_q[9], E5_q[10]);
F1_q[2]_read_address = RD_ADDR(E4_q[0], E4_q[1], E4_q[2], E4_q[3], E4_q[4], E4_q[5], E4_q[6], E4_q[7], E4_q[8], E4_q[9], E4_q[10]);
F1_q[2] = MEMORY_SEGMENT(F1_q[2]_data_in, F1_q[2]_write_enable, F1_q[2]_clock_0, F1_q[2]_clock_1, , , , VCC, F1_q[2]_write_address, F1_q[2]_read_address);


--F1_q[3] is dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[3]
F1_q[3]_data_in = dpm_ni2f_reg_des_data_rr_11;
F1_q[3]_write_enable = dpm_ni2f_reg_des_valid_data;
F1_q[3]_clock_0 = lcst;
F1_q[3]_clock_1 = lcst;
F1_q[3]_write_address = WR_ADDR(E5_q[0], E5_q[1], E5_q[2], E5_q[3], E5_q[4], E5_q[5], E5_q[6], E5_q[7], E5_q[8], E5_q[9], E5_q[10]);
F1_q[3]_read_address = RD_ADDR(E4_q[0], E4_q[1], E4_q[2], E4_q[3], E4_q[4], E4_q[5], E4_q[6], E4_q[7], E4_q[8], E4_q[9], E4_q[10]);
F1_q[3] = MEMORY_SEGMENT(F1_q[3]_data_in, F1_q[3]_write_enable, F1_q[3]_clock_0, F1_q[3]_clock_1, , , , VCC, F1_q[3]_write_address, F1_q[3]_read_address);


--F1_q[4] is dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[4]
F1_q[4]_data_in = dpm_ni2f_reg_des_data_rr_12;
F1_q[4]_write_enable = dpm_ni2f_reg_des_valid_data;
F1_q[4]_clock_0 = lcst;
F1_q[4]_clock_1 = lcst;
F1_q[4]_write_address = WR_ADDR(E5_q[0], E5_q[1], E5_q[2], E5_q[3], E5_q[4], E5_q[5], E5_q[6], E5_q[7], E5_q[8], E5_q[9], E5_q[10]);
F1_q[4]_read_address = RD_ADDR(E4_q[0], E4_q[1], E4_q[2], E4_q[3], E4_q[4], E4_q[5], E4_q[6], E4_q[7], E4_q[8], E4_q[9], E4_q[10]);
F1_q[4] = MEMORY_SEGMENT(F1_q[4]_data_in, F1_q[4]_write_enable, F1_q[4]_clock_0, F1_q[4]_clock_1, , , , VCC, F1_q[4]_write_address, F1_q[4]_read_address);


--F1_q[5] is dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[5]
F1_q[5]_data_in = dpm_ni2f_reg_des_data_rr_13;
F1_q[5]_write_enable = dpm_ni2f_reg_des_valid_data;
F1_q[5]_clock_0 = lcst;
F1_q[5]_clock_1 = lcst;
F1_q[5]_write_address = WR_ADDR(E5_q[0], E5_q[1], E5_q[2], E5_q[3], E5_q[4], E5_q[5], E5_q[6], E5_q[7], E5_q[8], E5_q[9], E5_q[10]);
F1_q[5]_read_address = RD_ADDR(E4_q[0], E4_q[1], E4_q[2], E4_q[3], E4_q[4], E4_q[5], E4_q[6], E4_q[7], E4_q[8], E4_q[9], E4_q[10]);
F1_q[5] = MEMORY_SEGMENT(F1_q[5]_data_in, F1_q[5]_write_enable, F1_q[5]_clock_0, F1_q[5]_clock_1, , , , VCC, F1_q[5]_write_address, F1_q[5]_read_address);


--F1_q[6] is dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[6]
F1_q[6]_data_in = dpm_ni2f_reg_des_data_rr_14;
F1_q[6]_write_enable = dpm_ni2f_reg_des_valid_data;
F1_q[6]_clock_0 = lcst;
F1_q[6]_clock_1 = lcst;
F1_q[6]_write_address = WR_ADDR(E5_q[0], E5_q[1], E5_q[2], E5_q[3], E5_q[4], E5_q[5], E5_q[6], E5_q[7], E5_q[8], E5_q[9], E5_q[10]);
F1_q[6]_read_address = RD_ADDR(E4_q[0], E4_q[1], E4_q[2], E4_q[3], E4_q[4], E4_q[5], E4_q[6], E4_q[7], E4_q[8], E4_q[9], E4_q[10]);
F1_q[6] = MEMORY_SEGMENT(F1_q[6]_data_in, F1_q[6]_write_enable, F1_q[6]_clock_0, F1_q[6]_clock_1, , , , VCC, F1_q[6]_write_address, F1_q[6]_read_address);


--F1_q[7] is dpram:dpm_ni2f_fifo_h_dpr|altdpram:altdpram_component|q[7]
F1_q[7]_data_in = dpm_ni2f_reg_des_data_rr_15;
F1_q[7]_write_enable = dpm_ni2f_reg_des_valid_data;
F1_q[7]_clock_0 = lcst;
F1_q[7]_clock_1 = lcst;
F1_q[7]_write_address = WR_ADDR(E5_q[0], E5_q[1], E5_q[2], E5_q[3], E5_q[4], E5_q[5], E5_q[6], E5_q[7], E5_q[8], E5_q[9], E5_q[10]);
F1_q[7]_read_address = RD_ADDR(E4_q[0], E4_q[1], E4_q[2], E4_q[3], E4_q[4], E4_q[5], E4_q[6], E4_q[7], E4_q[8], E4_q[9], E4_q[10]);
F1_q[7] = MEMORY_SEGMENT(F1_q[7]_data_in, F1_q[7]_write_enable, F1_q[7]_clock_0, F1_q[7]_clock_1, , , , VCC, F1_q[7]_write_address, F1_q[7]_read_address);


--ix2326_lc is ix2326_lc
--operation mode is normal

ix2326_lc = !dpm_ni2f_fifo_h_reg_fifo_empty # !dpm_ni2f_reg_sm_1;

--A1L797 is ix2326_lc~0
--operation mode is normal

A1L797 = !dpm_ni2f_fifo_h_reg_fifo_empty # !dpm_ni2f_reg_sm_1;

--A1L897 is ix2326~0
--operation mode is normal

A1L897 = !dpm_ni2f_fifo_h_reg_fifo_empty # !dpm_ni2f_reg_sm_1;


--dpm_ni2f_reg_des_er_r is dpm_ni2f_reg_des_er_r
--operation mode is normal

dpm_ni2f_reg_des_er_r_lut_out = DES_ER;
dpm_ni2f_reg_des_er_r = DFFEA(dpm_ni2f_reg_des_er_r_lut_out, lcst, , , , , );

--A1L704Q is dpm_ni2f_reg_des_er_r~1
--operation mode is normal

A1L704Q = dpm_ni2f_reg_des_er_r;


--dpm_ni2f_fifo_h_reg_fifo_full is dpm_ni2f_fifo_h_reg_fifo_full
--operation mode is normal

dpm_ni2f_fifo_h_reg_fifo_full_lut_out = ix2301_lc & !dpm_ni2f_reg_rdreq_fifo & (A1L67) # !ix2301_lc & (dpm_ni2f_fifo_h_reg_fifo_full);
dpm_ni2f_fifo_h_reg_fifo_full = DFFEA(dpm_ni2f_fifo_h_reg_fifo_full_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--A1L98Q is dpm_ni2f_fifo_h_reg_fifo_full~0
--operation mode is normal

A1L98Q = dpm_ni2f_fifo_h_reg_fifo_full;


--ix2300_lc is ix2300_lc
--operation mode is normal

ix2300_lc = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_h_reg_fifo_full & (!dpm_ni2f_fifo_h_reg_fifo_empty # !dpm_ni2f_reg_rdreq_fifo) # !dpm_ni2f_reg_des_valid_data & dpm_ni2f_reg_rdreq_fifo & (dpm_ni2f_fifo_h_reg_fifo_empty);

--A1L717 is ix2300_lc~0
--operation mode is normal

A1L717 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_h_reg_fifo_full & (!dpm_ni2f_fifo_h_reg_fifo_empty # !dpm_ni2f_reg_rdreq_fifo) # !dpm_ni2f_reg_des_valid_data & dpm_ni2f_reg_rdreq_fifo & (dpm_ni2f_fifo_h_reg_fifo_empty);


--P1_cmd_reg[6] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|cmd_reg[6]
--operation mode is normal

P1_cmd_reg[6] = AMPP_FUNCTION(P1L771, G1_low_ad_IR_data[6], pci_rstn, GLOBAL(pci_clk));

--P1L831Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|cmd_reg[6]~6
--operation mode is normal

P1L831Q = AMPP_FUNCTION(P1L771, G1_low_ad_IR_data[6], pci_rstn, GLOBAL(pci_clk));


--P1_cmd_reg[8] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|cmd_reg[8]
--operation mode is normal

P1_cmd_reg[8] = AMPP_FUNCTION(P1L971, G1_low_ad_IR_data[8], pci_rstn, GLOBAL(pci_clk));

--P1L041Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|cmd_reg[8]~7
--operation mode is normal

P1L041Q = AMPP_FUNCTION(P1L971, G1_low_ad_IR_data[8], pci_rstn, GLOBAL(pci_clk));


--K1_serr_or_lc is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|serr_or_lc
--operation mode is normal

K1_serr_or_lc = AMPP_FUNCTION(P1_cmd_reg[6], G1_trg_serr_vld, P1_cmd_reg[8]);

--K1L31 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|serr_or_lc~22
--operation mode is normal

K1L31 = AMPP_FUNCTION(P1_cmd_reg[6], G1_trg_serr_vld, P1_cmd_reg[8]);


--K1_xxlad[11] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|xxlad[11]
--operation mode is normal

K1_xxlad[11] = AMPP_FUNCTION(K1_xxlad[10], K1_xxlad[9], K1_xxlad[8]);

--K1L88 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|xxlad[11]~224
--operation mode is normal

K1L88 = AMPP_FUNCTION(K1_xxlad[10], K1_xxlad[9], K1_xxlad[8]);


--G1_low_ad_IR_data[7] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[7]
--operation mode is normal

G1_low_ad_IR_data[7] = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_7, pci_rstn, GLOBAL(pci_clk));

--G1L632Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[7]~32
--operation mode is normal

G1L632Q = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_7, pci_rstn, GLOBAL(pci_clk));


--G1_low_ad_IR_data[3] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[3]
--operation mode is normal

G1_low_ad_IR_data[3] = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_3, pci_rstn, GLOBAL(pci_clk));

--G1L822Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[3]~33
--operation mode is normal

G1L822Q = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_3, pci_rstn, GLOBAL(pci_clk));


--ix2530 is ix2530
--operation mode is normal

ix2530 = sg_reg_mx_q & (dpm_dec_reg_rdata_LED_2) # !sg_reg_mx_q & dpm_dec_reg_rdata_LED_6;

--A1L9901 is ix2530~3
--operation mode is normal

A1L9901 = sg_reg_mx_q & (dpm_dec_reg_rdata_LED_2) # !sg_reg_mx_q & dpm_dec_reg_rdata_LED_6;


--dpm_dec_reg_rdata_LED_4 is dpm_dec_reg_rdata_LED_4
--operation mode is normal

dpm_dec_reg_rdata_LED_4_lut_out = A1L868 & G1_low_ad_IR_data[4] # !A1L868 & (dpm_dec_reg_rdata_LED_4);
dpm_dec_reg_rdata_LED_4 = DFFEA(dpm_dec_reg_rdata_LED_4_lut_out, GLOBAL(pci_clk), pci_rstn, , , , );

--A1L94Q is dpm_dec_reg_rdata_LED_4~0
--operation mode is normal

A1L94Q = dpm_dec_reg_rdata_LED_4;


--dpm_dec_reg_rdata_LED_0 is dpm_dec_reg_rdata_LED_0
--operation mode is normal

dpm_dec_reg_rdata_LED_0_lut_out = A1L868 & G1_low_ad_IR_data[0] # !A1L868 & (dpm_dec_reg_rdata_LED_0);
dpm_dec_reg_rdata_LED_0 = DFFEA(dpm_dec_reg_rdata_LED_0_lut_out, GLOBAL(pci_clk), pci_rstn, , , , );

--A1L14Q is dpm_dec_reg_rdata_LED_0~0
--operation mode is normal

A1L14Q = dpm_dec_reg_rdata_LED_0;


--A1L169 is ix2386~0
--operation mode is normal

A1L169 = (ix2245_lc & (sg_reg_mx_q & (!dpm_dec_reg_rdata_LED_0) # !sg_reg_mx_q & !dpm_dec_reg_rdata_LED_4)) & CASCADE(A1L337);

--A1L269 is ix2386~1
--operation mode is normal

A1L269 = (ix2245_lc & (sg_reg_mx_q & (!dpm_dec_reg_rdata_LED_0) # !sg_reg_mx_q & !dpm_dec_reg_rdata_LED_4)) & CASCADE(A1L337);


--A1L569 is ix2388~0
--operation mode is normal

A1L569 = (sg_reg_mx_q & (dpm_dec_reg_rdata_LED_1) # !sg_reg_mx_q & dpm_dec_reg_rdata_LED_5) & CASCADE(A1L485);

--A1L669 is ix2388~1
--operation mode is normal

A1L669 = (sg_reg_mx_q & (dpm_dec_reg_rdata_LED_1) # !sg_reg_mx_q & dpm_dec_reg_rdata_LED_5) & CASCADE(A1L485);


--G1_low_ad_IR_data[5] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[5]
--operation mode is normal

G1_low_ad_IR_data[5] = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_5, pci_rstn, GLOBAL(pci_clk));

--G1L232Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[5]~34
--operation mode is normal

G1L232Q = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_5, pci_rstn, GLOBAL(pci_clk));


--G1_low_ad_IR_data[1] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[1]
--operation mode is normal

G1_low_ad_IR_data[1] = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_1, pci_rstn, GLOBAL(pci_clk));

--G1L422Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[1]~35
--operation mode is normal

G1L422Q = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_1, pci_rstn, GLOBAL(pci_clk));


--ix2246_lc is ix2246_lc
--operation mode is normal

ix2246_lc = sg_reg_mx_q & (dpm_dec_reg_rdata_LED_0) # !sg_reg_mx_q & dpm_dec_reg_rdata_LED_4;

--A1L385 is ix2246_lc~0
--operation mode is normal

A1L385 = sg_reg_mx_q & (dpm_dec_reg_rdata_LED_0) # !sg_reg_mx_q & dpm_dec_reg_rdata_LED_4;

--A1L485 is ix2246~3
--operation mode is normal

A1L485 = sg_reg_mx_q & (dpm_dec_reg_rdata_LED_0) # !sg_reg_mx_q & dpm_dec_reg_rdata_LED_4;


--ix2307_lc is ix2307_lc
--operation mode is normal

ix2307_lc = ix2579 & ix2531;

--A1L937 is ix2307_lc~0
--operation mode is normal

A1L937 = ix2579 & ix2531;


--G1_low_ad_IR_data[6] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[6]
--operation mode is normal

G1_low_ad_IR_data[6] = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_6, pci_rstn, GLOBAL(pci_clk));

--G1L432Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[6]~36
--operation mode is normal

G1L432Q = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_6, pci_rstn, GLOBAL(pci_clk));


--G1_low_ad_IR_data[2] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[2]
--operation mode is normal

G1_low_ad_IR_data[2] = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_2, pci_rstn, GLOBAL(pci_clk));

--G1L622Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[2]~37
--operation mode is normal

G1L622Q = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_2, pci_rstn, GLOBAL(pci_clk));


--A1L369 is ix2387~0
--operation mode is normal

A1L369 = (ix2245_lc $ (sg_reg_mx_q & (!dpm_dec_reg_rdata_LED_0) # !sg_reg_mx_q & !dpm_dec_reg_rdata_LED_4)) & CASCADE(A1L347);

--A1L469 is ix2387~1
--operation mode is normal

A1L469 = (ix2245_lc $ (sg_reg_mx_q & (!dpm_dec_reg_rdata_LED_0) # !sg_reg_mx_q & !dpm_dec_reg_rdata_LED_4)) & CASCADE(A1L347);


--E1_counter_cell[13] is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[13]
--operation mode is up_dn_cntr

E1_counter_cell[13]_lut_out = E1_counter_cell[13] $ E1L04;
E1_counter_cell[13] = DFFEA(E1_counter_cell[13]_lut_out, GLOBAL(pci_clk), , , , , );

--E1L24Q is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[13]~1
--operation mode is up_dn_cntr

E1L24Q = E1_counter_cell[13];

--E1L34 is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[13]~COUT
--operation mode is up_dn_cntr

E1L34 = CARRY(E1_counter_cell[13] & (E1L04));


--ix2315_lc is ix2315_lc
--operation mode is normal

ix2315_lc = dpm_ni2f_reg_sm_0 # dpm_ni2f_fifo_h_reg_fifo_empty # !dpm_ni2f_reg_pci_rd_req_s;

--A1L667 is ix2315_lc~0
--operation mode is normal

A1L667 = dpm_ni2f_reg_sm_0 # dpm_ni2f_fifo_h_reg_fifo_empty # !dpm_ni2f_reg_pci_rd_req_s;

--A1L767 is ix2315~0
--operation mode is normal

A1L767 = dpm_ni2f_reg_sm_0 # dpm_ni2f_fifo_h_reg_fifo_empty # !dpm_ni2f_reg_pci_rd_req_s;


--A1L456 is ix2272~0
--operation mode is normal

A1L456 = (!dpm_ni2f_reg_sm_5 & !dpm_ni2f_reg_sm_3 & !dpm_ni2f_reg_sm_1 # !dpm_ni2f_reg_sm_0) & CASCADE(A1L767);

--A1L556 is ix2272~1
--operation mode is normal

A1L556 = (!dpm_ni2f_reg_sm_5 & !dpm_ni2f_reg_sm_3 & !dpm_ni2f_reg_sm_1 # !dpm_ni2f_reg_sm_0) & CASCADE(A1L767);


--dpm_ni2f_reg_sm_9 is dpm_ni2f_reg_sm_9
--operation mode is normal

dpm_ni2f_reg_sm_9_lut_out = dpm_ni2f_reg_sm_8;
dpm_ni2f_reg_sm_9 = DFFEA(dpm_ni2f_reg_sm_9_lut_out, lcst, !ix2254, , , , );

--A1L934Q is dpm_ni2f_reg_sm_9~1
--operation mode is normal

A1L934Q = dpm_ni2f_reg_sm_9;


--A1L867 is ix2316~0
--operation mode is normal

A1L867 = (dpm_ni2f_reg_sm_1 # !ix2356_lc) & CASCADE(A1L897);

--A1L967 is ix2316~1
--operation mode is normal

A1L967 = (dpm_ni2f_reg_sm_1 # !ix2356_lc) & CASCADE(A1L897);


--M1_TS_IDLE_NOT is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|TS_IDLE_NOT
--operation mode is normal

M1_TS_IDLE_NOT = AMPP_FUNCTION(M1_TS_IDLE_d_lc, M1_TS_IDLE_d_lc1, P1_mbar_hit, pci_rstn, GLOBAL(pci_clk));

--M1L835Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|TS_IDLE_NOT~55
--operation mode is normal

M1L835Q = AMPP_FUNCTION(M1_TS_IDLE_d_lc, M1_TS_IDLE_d_lc1, P1_mbar_hit, pci_rstn, GLOBAL(pci_clk));


--J1_MS_ENA is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MS_ENA
--operation mode is normal

J1_MS_ENA = AMPP_FUNCTION(J1_MS_ENA_d_lc, J1_MS_PARK, J1_l_req_vld, pci_gntn, pci_rstn, GLOBAL(pci_clk));

--J1L793Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MS_ENA~55
--operation mode is normal

J1L793Q = AMPP_FUNCTION(J1_MS_ENA_d_lc, J1_MS_PARK, J1_l_req_vld, pci_gntn, pci_rstn, GLOBAL(pci_clk));


--L1_parc[11] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pg:parity_gen|parc[11]
--operation mode is arithmetic

L1_parc[11] = AMPP_FUNCTION();

--L1L73 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pg:parity_gen|parc[11]~38
--operation mode is arithmetic

L1L73 = AMPP_FUNCTION();

--L1L83 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pg:parity_gen|parc[11]~COUT
--operation mode is arithmetic

L1L83 = AMPP_FUNCTION(pci_cben_3, pci_cben_2, L1L53);


--J1_perr_oer is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|perr_oer
--operation mode is normal

J1_perr_oer = AMPP_FUNCTION(J1_MS_DXFR, J1_MS_TAR, J1_wr_rdn, pci_rstn, GLOBAL(pci_clk));

--J1L685Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|perr_oer~23
--operation mode is normal

J1L685Q = AMPP_FUNCTION(J1_MS_DXFR, J1_MS_TAR, J1_wr_rdn, pci_rstn, GLOBAL(pci_clk));


--N3_REG is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_sr:wr_rdn_FF|REG
--operation mode is normal

N3_REG = AMPP_FUNCTION(M1L87, N3_REG, M1_TS_IDLE_NOT, M1_LW_IDLE_NOT, pci_rstn, GLOBAL(pci_clk));

--N3L2Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_sr:wr_rdn_FF|REG~54
--operation mode is normal

N3L2Q = AMPP_FUNCTION(M1L87, N3_REG, M1_TS_IDLE_NOT, M1_LW_IDLE_NOT, pci_rstn, GLOBAL(pci_clk));


--M1_TURN_AR_R is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|TURN_AR_R
--operation mode is normal

M1_TURN_AR_R = AMPP_FUNCTION(M1_TS_TURN_AR, pci_rstn, GLOBAL(pci_clk));

--M1L545Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|TURN_AR_R~6
--operation mode is normal

M1L545Q = AMPP_FUNCTION(M1_TS_TURN_AR, pci_rstn, GLOBAL(pci_clk));


--dpm_ni2f_reg_des_data_rr_0 is dpm_ni2f_reg_des_data_rr_0
--operation mode is normal

dpm_ni2f_reg_des_data_rr_0_lut_out = dpm_ni2f_reg_des_data_r_0;
dpm_ni2f_reg_des_data_rr_0 = DFFEA(dpm_ni2f_reg_des_data_rr_0_lut_out, lcst, , , , , );

--A1L173Q is dpm_ni2f_reg_des_data_rr_0~1
--operation mode is normal

A1L173Q = dpm_ni2f_reg_des_data_rr_0;


--E7_q[0] is lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[0]
--operation mode is clrb_cntr

E7_q[0]_lut_out = (ix2288_lc $ E7_q[0]) & VCC;
E7_q[0] = DFFEA(E7_q[0]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E7L52Q is lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[0]~0
--operation mode is clrb_cntr

E7L52Q = E7_q[0];

--E7L3 is lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT
--operation mode is clrb_cntr

E7L3 = CARRY(E7_q[0]);


--E7_q[1] is lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[1]
--operation mode is clrb_cntr

E7_q[1]_lut_out = (E7_q[1] $ (ix2288_lc & E7L3)) & VCC;
E7_q[1] = DFFEA(E7_q[1]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E7L72Q is lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[1]~1
--operation mode is clrb_cntr

E7L72Q = E7_q[1];

--E7L5 is lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT
--operation mode is clrb_cntr

E7L5 = CARRY(E7_q[1] & (E7L3));


--E7_q[2] is lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[2]
--operation mode is clrb_cntr

E7_q[2]_lut_out = (E7_q[2] $ (ix2288_lc & E7L5)) & VCC;
E7_q[2] = DFFEA(E7_q[2]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E7L92Q is lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[2]~2
--operation mode is clrb_cntr

E7L92Q = E7_q[2];

--E7L7 is lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT
--operation mode is clrb_cntr

E7L7 = CARRY(E7_q[2] & (E7L5));


--E7_q[3] is lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[3]
--operation mode is clrb_cntr

E7_q[3]_lut_out = (E7_q[3] $ (ix2288_lc & E7L7)) & VCC;
E7_q[3] = DFFEA(E7_q[3]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E7L13Q is lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[3]~3
--operation mode is clrb_cntr

E7L13Q = E7_q[3];

--E7L9 is lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT
--operation mode is clrb_cntr

E7L9 = CARRY(E7_q[3] & (E7L7));


--E7_q[4] is lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[4]
--operation mode is clrb_cntr

E7_q[4]_lut_out = (E7_q[4] $ (ix2288_lc & E7L9)) & VCC;
E7_q[4] = DFFEA(E7_q[4]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E7L33Q is lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[4]~4
--operation mode is clrb_cntr

E7L33Q = E7_q[4];

--E7L11 is lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|counter_cell[4]~COUT
--operation mode is clrb_cntr

E7L11 = CARRY(E7_q[4] & (E7L9));


--E7_q[5] is lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[5]
--operation mode is clrb_cntr

E7_q[5]_lut_out = (E7_q[5] $ (ix2288_lc & E7L11)) & VCC;
E7_q[5] = DFFEA(E7_q[5]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E7L53Q is lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[5]~5
--operation mode is clrb_cntr

E7L53Q = E7_q[5];

--E7L31 is lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|counter_cell[5]~COUT
--operation mode is clrb_cntr

E7L31 = CARRY(E7_q[5] & (E7L11));


--E7_q[6] is lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[6]
--operation mode is clrb_cntr

E7_q[6]_lut_out = (E7_q[6] $ (ix2288_lc & E7L31)) & VCC;
E7_q[6] = DFFEA(E7_q[6]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E7L73Q is lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[6]~6
--operation mode is clrb_cntr

E7L73Q = E7_q[6];

--E7L51 is lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|counter_cell[6]~COUT
--operation mode is clrb_cntr

E7L51 = CARRY(E7_q[6] & (E7L31));


--E7_q[7] is lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[7]
--operation mode is clrb_cntr

E7_q[7]_lut_out = (E7_q[7] $ (ix2288_lc & E7L51)) & VCC;
E7_q[7] = DFFEA(E7_q[7]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E7L93Q is lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[7]~7
--operation mode is clrb_cntr

E7L93Q = E7_q[7];

--E7L71 is lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|counter_cell[7]~COUT
--operation mode is clrb_cntr

E7L71 = CARRY(E7_q[7] & (E7L51));


--E7_q[8] is lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[8]
--operation mode is clrb_cntr

E7_q[8]_lut_out = (E7_q[8] $ (ix2288_lc & E7L71)) & VCC;
E7_q[8] = DFFEA(E7_q[8]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E7L14Q is lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[8]~8
--operation mode is clrb_cntr

E7L14Q = E7_q[8];

--E7L91 is lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|counter_cell[8]~COUT
--operation mode is clrb_cntr

E7L91 = CARRY(E7_q[8] & (E7L71));


--E7_q[9] is lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[9]
--operation mode is clrb_cntr

E7_q[9]_lut_out = (E7_q[9] $ (ix2288_lc & E7L91)) & VCC;
E7_q[9] = DFFEA(E7_q[9]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E7L34Q is lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[9]~9
--operation mode is clrb_cntr

E7L34Q = E7_q[9];

--E7L12 is lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|counter_cell[9]~COUT
--operation mode is clrb_cntr

E7L12 = CARRY(E7_q[9] & (E7L91));


--E7_q[10] is lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[10]
--operation mode is clrb_cntr

E7_q[10]_lut_out = (E7_q[10] $ (ix2288_lc & E7L12)) & VCC;
E7_q[10] = DFFEA(E7_q[10]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E7L54Q is lpm_counter:dpm_ni2f_fifo_l_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[10]~10
--operation mode is clrb_cntr

E7L54Q = E7_q[10];


--E6_q[0] is lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[0]
--operation mode is clrb_cntr

E6_q[0]_lut_out = (ix2287_lc $ E6_q[0]) & VCC;
E6_q[0] = DFFEA(E6_q[0]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E6L52Q is lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[0]~0
--operation mode is clrb_cntr

E6L52Q = E6_q[0];

--E6L3 is lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT
--operation mode is clrb_cntr

E6L3 = CARRY(E6_q[0]);


--E6_q[1] is lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[1]
--operation mode is clrb_cntr

E6_q[1]_lut_out = (E6_q[1] $ (ix2287_lc & E6L3)) & VCC;
E6_q[1] = DFFEA(E6_q[1]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E6L72Q is lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[1]~1
--operation mode is clrb_cntr

E6L72Q = E6_q[1];

--E6L5 is lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT
--operation mode is clrb_cntr

E6L5 = CARRY(E6_q[1] & (E6L3));


--E6_q[2] is lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[2]
--operation mode is clrb_cntr

E6_q[2]_lut_out = (E6_q[2] $ (ix2287_lc & E6L5)) & VCC;
E6_q[2] = DFFEA(E6_q[2]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E6L92Q is lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[2]~2
--operation mode is clrb_cntr

E6L92Q = E6_q[2];

--E6L7 is lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT
--operation mode is clrb_cntr

E6L7 = CARRY(E6_q[2] & (E6L5));


--E6_q[3] is lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[3]
--operation mode is clrb_cntr

E6_q[3]_lut_out = (E6_q[3] $ (ix2287_lc & E6L7)) & VCC;
E6_q[3] = DFFEA(E6_q[3]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E6L13Q is lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[3]~3
--operation mode is clrb_cntr

E6L13Q = E6_q[3];

--E6L9 is lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT
--operation mode is clrb_cntr

E6L9 = CARRY(E6_q[3] & (E6L7));


--E6_q[4] is lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[4]
--operation mode is clrb_cntr

E6_q[4]_lut_out = (E6_q[4] $ (ix2287_lc & E6L9)) & VCC;
E6_q[4] = DFFEA(E6_q[4]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E6L33Q is lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[4]~4
--operation mode is clrb_cntr

E6L33Q = E6_q[4];

--E6L11 is lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|counter_cell[4]~COUT
--operation mode is clrb_cntr

E6L11 = CARRY(E6_q[4] & (E6L9));


--E6_q[5] is lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[5]
--operation mode is clrb_cntr

E6_q[5]_lut_out = (E6_q[5] $ (ix2287_lc & E6L11)) & VCC;
E6_q[5] = DFFEA(E6_q[5]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E6L53Q is lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[5]~5
--operation mode is clrb_cntr

E6L53Q = E6_q[5];

--E6L31 is lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|counter_cell[5]~COUT
--operation mode is clrb_cntr

E6L31 = CARRY(E6_q[5] & (E6L11));


--E6_q[6] is lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[6]
--operation mode is clrb_cntr

E6_q[6]_lut_out = (E6_q[6] $ (ix2287_lc & E6L31)) & VCC;
E6_q[6] = DFFEA(E6_q[6]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E6L73Q is lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[6]~6
--operation mode is clrb_cntr

E6L73Q = E6_q[6];

--E6L51 is lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|counter_cell[6]~COUT
--operation mode is clrb_cntr

E6L51 = CARRY(E6_q[6] & (E6L31));


--E6_q[7] is lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[7]
--operation mode is clrb_cntr

E6_q[7]_lut_out = (E6_q[7] $ (ix2287_lc & E6L51)) & VCC;
E6_q[7] = DFFEA(E6_q[7]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E6L93Q is lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[7]~7
--operation mode is clrb_cntr

E6L93Q = E6_q[7];

--E6L71 is lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|counter_cell[7]~COUT
--operation mode is clrb_cntr

E6L71 = CARRY(E6_q[7] & (E6L51));


--E6_q[8] is lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[8]
--operation mode is clrb_cntr

E6_q[8]_lut_out = (E6_q[8] $ (ix2287_lc & E6L71)) & VCC;
E6_q[8] = DFFEA(E6_q[8]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E6L14Q is lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[8]~8
--operation mode is clrb_cntr

E6L14Q = E6_q[8];

--E6L91 is lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|counter_cell[8]~COUT
--operation mode is clrb_cntr

E6L91 = CARRY(E6_q[8] & (E6L71));


--E6_q[9] is lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[9]
--operation mode is clrb_cntr

E6_q[9]_lut_out = (E6_q[9] $ (ix2287_lc & E6L91)) & VCC;
E6_q[9] = DFFEA(E6_q[9]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E6L34Q is lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[9]~9
--operation mode is clrb_cntr

E6L34Q = E6_q[9];

--E6L12 is lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|counter_cell[9]~COUT
--operation mode is clrb_cntr

E6L12 = CARRY(E6_q[9] & (E6L91));


--E6_q[10] is lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[10]
--operation mode is clrb_cntr

E6_q[10]_lut_out = (E6_q[10] $ (ix2287_lc & E6L12)) & VCC;
E6_q[10] = DFFEA(E6_q[10]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E6L54Q is lpm_counter:dpm_ni2f_fifo_l_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[10]~10
--operation mode is clrb_cntr

E6L54Q = E6_q[10];


--dpm_ni2f_reg_des_data_rr_1 is dpm_ni2f_reg_des_data_rr_1
--operation mode is normal

dpm_ni2f_reg_des_data_rr_1_lut_out = dpm_ni2f_reg_des_data_r_1;
dpm_ni2f_reg_des_data_rr_1 = DFFEA(dpm_ni2f_reg_des_data_rr_1_lut_out, lcst, , , , , );

--A1L373Q is dpm_ni2f_reg_des_data_rr_1~1
--operation mode is normal

A1L373Q = dpm_ni2f_reg_des_data_rr_1;


--dpm_ni2f_reg_des_data_rr_2 is dpm_ni2f_reg_des_data_rr_2
--operation mode is normal

dpm_ni2f_reg_des_data_rr_2_lut_out = dpm_ni2f_reg_des_data_r_2;
dpm_ni2f_reg_des_data_rr_2 = DFFEA(dpm_ni2f_reg_des_data_rr_2_lut_out, lcst, , , , , );

--A1L573Q is dpm_ni2f_reg_des_data_rr_2~1
--operation mode is normal

A1L573Q = dpm_ni2f_reg_des_data_rr_2;


--dpm_ni2f_reg_des_data_rr_3 is dpm_ni2f_reg_des_data_rr_3
--operation mode is normal

dpm_ni2f_reg_des_data_rr_3_lut_out = dpm_ni2f_reg_des_data_r_3;
dpm_ni2f_reg_des_data_rr_3 = DFFEA(dpm_ni2f_reg_des_data_rr_3_lut_out, lcst, , , , , );

--A1L773Q is dpm_ni2f_reg_des_data_rr_3~1
--operation mode is normal

A1L773Q = dpm_ni2f_reg_des_data_rr_3;


--dpm_ni2f_reg_des_data_rr_4 is dpm_ni2f_reg_des_data_rr_4
--operation mode is normal

dpm_ni2f_reg_des_data_rr_4_lut_out = dpm_ni2f_reg_des_data_r_4;
dpm_ni2f_reg_des_data_rr_4 = DFFEA(dpm_ni2f_reg_des_data_rr_4_lut_out, lcst, , , , , );

--A1L973Q is dpm_ni2f_reg_des_data_rr_4~1
--operation mode is normal

A1L973Q = dpm_ni2f_reg_des_data_rr_4;


--dpm_ni2f_reg_des_data_rr_5 is dpm_ni2f_reg_des_data_rr_5
--operation mode is normal

dpm_ni2f_reg_des_data_rr_5_lut_out = dpm_ni2f_reg_des_data_r_5;
dpm_ni2f_reg_des_data_rr_5 = DFFEA(dpm_ni2f_reg_des_data_rr_5_lut_out, lcst, , , , , );

--A1L183Q is dpm_ni2f_reg_des_data_rr_5~1
--operation mode is normal

A1L183Q = dpm_ni2f_reg_des_data_rr_5;


--dpm_ni2f_reg_des_data_rr_6 is dpm_ni2f_reg_des_data_rr_6
--operation mode is normal

dpm_ni2f_reg_des_data_rr_6_lut_out = dpm_ni2f_reg_des_data_r_6;
dpm_ni2f_reg_des_data_rr_6 = DFFEA(dpm_ni2f_reg_des_data_rr_6_lut_out, lcst, , , , , );

--A1L383Q is dpm_ni2f_reg_des_data_rr_6~1
--operation mode is normal

A1L383Q = dpm_ni2f_reg_des_data_rr_6;


--dpm_ni2f_reg_des_data_rr_7 is dpm_ni2f_reg_des_data_rr_7
--operation mode is normal

dpm_ni2f_reg_des_data_rr_7_lut_out = dpm_ni2f_reg_des_data_r_7;
dpm_ni2f_reg_des_data_rr_7 = DFFEA(dpm_ni2f_reg_des_data_rr_7_lut_out, lcst, , , , , );

--A1L583Q is dpm_ni2f_reg_des_data_rr_7~1
--operation mode is normal

A1L583Q = dpm_ni2f_reg_des_data_rr_7;


--dpm_ni2f_reg_des_data_rr_8 is dpm_ni2f_reg_des_data_rr_8
--operation mode is normal

dpm_ni2f_reg_des_data_rr_8_lut_out = dpm_ni2f_reg_des_data_r_8;
dpm_ni2f_reg_des_data_rr_8 = DFFEA(dpm_ni2f_reg_des_data_rr_8_lut_out, lcst, , , , , );

--A1L783Q is dpm_ni2f_reg_des_data_rr_8~1
--operation mode is normal

A1L783Q = dpm_ni2f_reg_des_data_rr_8;


--E5_q[0] is lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[0]
--operation mode is clrb_cntr

E5_q[0]_lut_out = (ix2304_lc $ E5_q[0]) & VCC;
E5_q[0] = DFFEA(E5_q[0]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E5L52Q is lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[0]~0
--operation mode is clrb_cntr

E5L52Q = E5_q[0];

--E5L3 is lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT
--operation mode is clrb_cntr

E5L3 = CARRY(E5_q[0]);


--E5_q[1] is lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[1]
--operation mode is clrb_cntr

E5_q[1]_lut_out = (E5_q[1] $ (ix2304_lc & E5L3)) & VCC;
E5_q[1] = DFFEA(E5_q[1]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E5L72Q is lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[1]~1
--operation mode is clrb_cntr

E5L72Q = E5_q[1];

--E5L5 is lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT
--operation mode is clrb_cntr

E5L5 = CARRY(E5_q[1] & (E5L3));


--E5_q[2] is lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[2]
--operation mode is clrb_cntr

E5_q[2]_lut_out = (E5_q[2] $ (ix2304_lc & E5L5)) & VCC;
E5_q[2] = DFFEA(E5_q[2]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E5L92Q is lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[2]~2
--operation mode is clrb_cntr

E5L92Q = E5_q[2];

--E5L7 is lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT
--operation mode is clrb_cntr

E5L7 = CARRY(E5_q[2] & (E5L5));


--E5_q[3] is lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[3]
--operation mode is clrb_cntr

E5_q[3]_lut_out = (E5_q[3] $ (ix2304_lc & E5L7)) & VCC;
E5_q[3] = DFFEA(E5_q[3]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E5L13Q is lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[3]~3
--operation mode is clrb_cntr

E5L13Q = E5_q[3];

--E5L9 is lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT
--operation mode is clrb_cntr

E5L9 = CARRY(E5_q[3] & (E5L7));


--E5_q[4] is lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[4]
--operation mode is clrb_cntr

E5_q[4]_lut_out = (E5_q[4] $ (ix2304_lc & E5L9)) & VCC;
E5_q[4] = DFFEA(E5_q[4]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E5L33Q is lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[4]~4
--operation mode is clrb_cntr

E5L33Q = E5_q[4];

--E5L11 is lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|counter_cell[4]~COUT
--operation mode is clrb_cntr

E5L11 = CARRY(E5_q[4] & (E5L9));


--E5_q[5] is lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[5]
--operation mode is clrb_cntr

E5_q[5]_lut_out = (E5_q[5] $ (ix2304_lc & E5L11)) & VCC;
E5_q[5] = DFFEA(E5_q[5]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E5L53Q is lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[5]~5
--operation mode is clrb_cntr

E5L53Q = E5_q[5];

--E5L31 is lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|counter_cell[5]~COUT
--operation mode is clrb_cntr

E5L31 = CARRY(E5_q[5] & (E5L11));


--E5_q[6] is lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[6]
--operation mode is clrb_cntr

E5_q[6]_lut_out = (E5_q[6] $ (ix2304_lc & E5L31)) & VCC;
E5_q[6] = DFFEA(E5_q[6]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E5L73Q is lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[6]~6
--operation mode is clrb_cntr

E5L73Q = E5_q[6];

--E5L51 is lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|counter_cell[6]~COUT
--operation mode is clrb_cntr

E5L51 = CARRY(E5_q[6] & (E5L31));


--E5_q[7] is lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[7]
--operation mode is clrb_cntr

E5_q[7]_lut_out = (E5_q[7] $ (ix2304_lc & E5L51)) & VCC;
E5_q[7] = DFFEA(E5_q[7]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E5L93Q is lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[7]~7
--operation mode is clrb_cntr

E5L93Q = E5_q[7];

--E5L71 is lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|counter_cell[7]~COUT
--operation mode is clrb_cntr

E5L71 = CARRY(E5_q[7] & (E5L51));


--E5_q[8] is lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[8]
--operation mode is clrb_cntr

E5_q[8]_lut_out = (E5_q[8] $ (ix2304_lc & E5L71)) & VCC;
E5_q[8] = DFFEA(E5_q[8]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E5L14Q is lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[8]~8
--operation mode is clrb_cntr

E5L14Q = E5_q[8];

--E5L91 is lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|counter_cell[8]~COUT
--operation mode is clrb_cntr

E5L91 = CARRY(E5_q[8] & (E5L71));


--E5_q[9] is lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[9]
--operation mode is clrb_cntr

E5_q[9]_lut_out = (E5_q[9] $ (ix2304_lc & E5L91)) & VCC;
E5_q[9] = DFFEA(E5_q[9]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E5L34Q is lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[9]~9
--operation mode is clrb_cntr

E5L34Q = E5_q[9];

--E5L12 is lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|counter_cell[9]~COUT
--operation mode is clrb_cntr

E5L12 = CARRY(E5_q[9] & (E5L91));


--E5_q[10] is lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[10]
--operation mode is clrb_cntr

E5_q[10]_lut_out = (E5_q[10] $ (ix2304_lc & E5L12)) & VCC;
E5_q[10] = DFFEA(E5_q[10]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E5L54Q is lpm_counter:dpm_ni2f_fifo_h_wpointer_ix9|alt_counter_f10ke:wysi_counter|q[10]~10
--operation mode is clrb_cntr

E5L54Q = E5_q[10];


--E4_q[0] is lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[0]
--operation mode is clrb_cntr

E4_q[0]_lut_out = (ix2303_lc $ E4_q[0]) & VCC;
E4_q[0] = DFFEA(E4_q[0]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E4L52Q is lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[0]~0
--operation mode is clrb_cntr

E4L52Q = E4_q[0];

--E4L3 is lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT
--operation mode is clrb_cntr

E4L3 = CARRY(E4_q[0]);


--E4_q[1] is lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[1]
--operation mode is clrb_cntr

E4_q[1]_lut_out = (E4_q[1] $ (ix2303_lc & E4L3)) & VCC;
E4_q[1] = DFFEA(E4_q[1]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E4L72Q is lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[1]~1
--operation mode is clrb_cntr

E4L72Q = E4_q[1];

--E4L5 is lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT
--operation mode is clrb_cntr

E4L5 = CARRY(E4_q[1] & (E4L3));


--E4_q[2] is lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[2]
--operation mode is clrb_cntr

E4_q[2]_lut_out = (E4_q[2] $ (ix2303_lc & E4L5)) & VCC;
E4_q[2] = DFFEA(E4_q[2]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E4L92Q is lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[2]~2
--operation mode is clrb_cntr

E4L92Q = E4_q[2];

--E4L7 is lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT
--operation mode is clrb_cntr

E4L7 = CARRY(E4_q[2] & (E4L5));


--E4_q[3] is lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[3]
--operation mode is clrb_cntr

E4_q[3]_lut_out = (E4_q[3] $ (ix2303_lc & E4L7)) & VCC;
E4_q[3] = DFFEA(E4_q[3]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E4L13Q is lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[3]~3
--operation mode is clrb_cntr

E4L13Q = E4_q[3];

--E4L9 is lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT
--operation mode is clrb_cntr

E4L9 = CARRY(E4_q[3] & (E4L7));


--E4_q[4] is lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[4]
--operation mode is clrb_cntr

E4_q[4]_lut_out = (E4_q[4] $ (ix2303_lc & E4L9)) & VCC;
E4_q[4] = DFFEA(E4_q[4]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E4L33Q is lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[4]~4
--operation mode is clrb_cntr

E4L33Q = E4_q[4];

--E4L11 is lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|counter_cell[4]~COUT
--operation mode is clrb_cntr

E4L11 = CARRY(E4_q[4] & (E4L9));


--E4_q[5] is lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[5]
--operation mode is clrb_cntr

E4_q[5]_lut_out = (E4_q[5] $ (ix2303_lc & E4L11)) & VCC;
E4_q[5] = DFFEA(E4_q[5]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E4L53Q is lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[5]~5
--operation mode is clrb_cntr

E4L53Q = E4_q[5];

--E4L31 is lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|counter_cell[5]~COUT
--operation mode is clrb_cntr

E4L31 = CARRY(E4_q[5] & (E4L11));


--E4_q[6] is lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[6]
--operation mode is clrb_cntr

E4_q[6]_lut_out = (E4_q[6] $ (ix2303_lc & E4L31)) & VCC;
E4_q[6] = DFFEA(E4_q[6]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E4L73Q is lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[6]~6
--operation mode is clrb_cntr

E4L73Q = E4_q[6];

--E4L51 is lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|counter_cell[6]~COUT
--operation mode is clrb_cntr

E4L51 = CARRY(E4_q[6] & (E4L31));


--E4_q[7] is lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[7]
--operation mode is clrb_cntr

E4_q[7]_lut_out = (E4_q[7] $ (ix2303_lc & E4L51)) & VCC;
E4_q[7] = DFFEA(E4_q[7]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E4L93Q is lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[7]~7
--operation mode is clrb_cntr

E4L93Q = E4_q[7];

--E4L71 is lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|counter_cell[7]~COUT
--operation mode is clrb_cntr

E4L71 = CARRY(E4_q[7] & (E4L51));


--E4_q[8] is lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[8]
--operation mode is clrb_cntr

E4_q[8]_lut_out = (E4_q[8] $ (ix2303_lc & E4L71)) & VCC;
E4_q[8] = DFFEA(E4_q[8]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E4L14Q is lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[8]~8
--operation mode is clrb_cntr

E4L14Q = E4_q[8];

--E4L91 is lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|counter_cell[8]~COUT
--operation mode is clrb_cntr

E4L91 = CARRY(E4_q[8] & (E4L71));


--E4_q[9] is lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[9]
--operation mode is clrb_cntr

E4_q[9]_lut_out = (E4_q[9] $ (ix2303_lc & E4L91)) & VCC;
E4_q[9] = DFFEA(E4_q[9]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E4L34Q is lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[9]~9
--operation mode is clrb_cntr

E4L34Q = E4_q[9];

--E4L12 is lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|counter_cell[9]~COUT
--operation mode is clrb_cntr

E4L12 = CARRY(E4_q[9] & (E4L91));


--E4_q[10] is lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[10]
--operation mode is clrb_cntr

E4_q[10]_lut_out = (E4_q[10] $ (ix2303_lc & E4L12)) & VCC;
E4_q[10] = DFFEA(E4_q[10]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E4L54Q is lpm_counter:dpm_ni2f_fifo_h_rpointer_ix9|alt_counter_f10ke:wysi_counter|q[10]~10
--operation mode is clrb_cntr

E4L54Q = E4_q[10];


--dpm_ni2f_reg_des_data_rr_9 is dpm_ni2f_reg_des_data_rr_9
--operation mode is normal

dpm_ni2f_reg_des_data_rr_9_lut_out = dpm_ni2f_reg_des_data_r_9;
dpm_ni2f_reg_des_data_rr_9 = DFFEA(dpm_ni2f_reg_des_data_rr_9_lut_out, lcst, , , , , );

--A1L983Q is dpm_ni2f_reg_des_data_rr_9~1
--operation mode is normal

A1L983Q = dpm_ni2f_reg_des_data_rr_9;


--dpm_ni2f_reg_des_data_rr_10 is dpm_ni2f_reg_des_data_rr_10
--operation mode is normal

dpm_ni2f_reg_des_data_rr_10_lut_out = dpm_ni2f_reg_des_data_r_10;
dpm_ni2f_reg_des_data_rr_10 = DFFEA(dpm_ni2f_reg_des_data_rr_10_lut_out, lcst, , , , , );

--A1L193Q is dpm_ni2f_reg_des_data_rr_10~1
--operation mode is normal

A1L193Q = dpm_ni2f_reg_des_data_rr_10;


--dpm_ni2f_reg_des_data_rr_11 is dpm_ni2f_reg_des_data_rr_11
--operation mode is normal

dpm_ni2f_reg_des_data_rr_11_lut_out = dpm_ni2f_reg_des_data_r_11;
dpm_ni2f_reg_des_data_rr_11 = DFFEA(dpm_ni2f_reg_des_data_rr_11_lut_out, lcst, , , , , );

--A1L393Q is dpm_ni2f_reg_des_data_rr_11~1
--operation mode is normal

A1L393Q = dpm_ni2f_reg_des_data_rr_11;


--dpm_ni2f_reg_des_data_rr_12 is dpm_ni2f_reg_des_data_rr_12
--operation mode is normal

dpm_ni2f_reg_des_data_rr_12_lut_out = dpm_ni2f_reg_des_data_r_12;
dpm_ni2f_reg_des_data_rr_12 = DFFEA(dpm_ni2f_reg_des_data_rr_12_lut_out, lcst, , , , , );

--A1L593Q is dpm_ni2f_reg_des_data_rr_12~1
--operation mode is normal

A1L593Q = dpm_ni2f_reg_des_data_rr_12;


--dpm_ni2f_reg_des_data_rr_13 is dpm_ni2f_reg_des_data_rr_13
--operation mode is normal

dpm_ni2f_reg_des_data_rr_13_lut_out = dpm_ni2f_reg_des_data_r_13;
dpm_ni2f_reg_des_data_rr_13 = DFFEA(dpm_ni2f_reg_des_data_rr_13_lut_out, lcst, , , , , );

--A1L793Q is dpm_ni2f_reg_des_data_rr_13~1
--operation mode is normal

A1L793Q = dpm_ni2f_reg_des_data_rr_13;


--dpm_ni2f_reg_des_data_rr_14 is dpm_ni2f_reg_des_data_rr_14
--operation mode is normal

dpm_ni2f_reg_des_data_rr_14_lut_out = dpm_ni2f_reg_des_data_r_14;
dpm_ni2f_reg_des_data_rr_14 = DFFEA(dpm_ni2f_reg_des_data_rr_14_lut_out, lcst, , , , , );

--A1L993Q is dpm_ni2f_reg_des_data_rr_14~1
--operation mode is normal

A1L993Q = dpm_ni2f_reg_des_data_rr_14;


--dpm_ni2f_reg_des_data_rr_15 is dpm_ni2f_reg_des_data_rr_15
--operation mode is normal

dpm_ni2f_reg_des_data_rr_15_lut_out = dpm_ni2f_reg_des_data_r_15;
dpm_ni2f_reg_des_data_rr_15 = DFFEA(dpm_ni2f_reg_des_data_rr_15_lut_out, lcst, , , , , );

--A1L104Q is dpm_ni2f_reg_des_data_rr_15~1
--operation mode is normal

A1L104Q = dpm_ni2f_reg_des_data_rr_15;


--dpm_ni2f_fifo_h_reg_nwords_2 is dpm_ni2f_fifo_h_reg_nwords_2
--operation mode is normal

dpm_ni2f_fifo_h_reg_nwords_2_lut_out = !A1L907;
dpm_ni2f_fifo_h_reg_nwords_2 = DFFEA(dpm_ni2f_fifo_h_reg_nwords_2_lut_out, lcst, !dpm_ni2f_reg_sreset120, , ix2302_lc, , );

--A1L59Q is dpm_ni2f_fifo_h_reg_nwords_2~1
--operation mode is normal

A1L59Q = dpm_ni2f_fifo_h_reg_nwords_2;


--dpm_ni2f_fifo_h_reg_nwords_1 is dpm_ni2f_fifo_h_reg_nwords_1
--operation mode is normal

dpm_ni2f_fifo_h_reg_nwords_1_lut_out = !A1L117;
dpm_ni2f_fifo_h_reg_nwords_1 = DFFEA(dpm_ni2f_fifo_h_reg_nwords_1_lut_out, lcst, !dpm_ni2f_reg_sreset120, , ix2302_lc, , );

--A1L39Q is dpm_ni2f_fifo_h_reg_nwords_1~1
--operation mode is normal

A1L39Q = dpm_ni2f_fifo_h_reg_nwords_1;


--dpm_ni2f_fifo_h_reg_nwords_0 is dpm_ni2f_fifo_h_reg_nwords_0
--operation mode is normal

dpm_ni2f_fifo_h_reg_nwords_0_lut_out = !A1L317;
dpm_ni2f_fifo_h_reg_nwords_0 = DFFEA(dpm_ni2f_fifo_h_reg_nwords_0_lut_out, lcst, !dpm_ni2f_reg_sreset120, , ix2302_lc, , );

--A1L19Q is dpm_ni2f_fifo_h_reg_nwords_0~1
--operation mode is normal

A1L19Q = dpm_ni2f_fifo_h_reg_nwords_0;


--A1L48 is dpm_ni2f_fifo_h_modgen_eq_73_ix25~0
--operation mode is normal

A1L48 = (!dpm_ni2f_fifo_h_reg_nwords_2 & !dpm_ni2f_fifo_h_reg_nwords_1 & dpm_ni2f_fifo_h_reg_nwords_0) & CASCADE(A1L38);

--A1L58 is dpm_ni2f_fifo_h_modgen_eq_73_ix25~1
--operation mode is normal

A1L58 = (!dpm_ni2f_fifo_h_reg_nwords_2 & !dpm_ni2f_fifo_h_reg_nwords_1 & dpm_ni2f_fifo_h_reg_nwords_0) & CASCADE(A1L38);


--G1_ad_ir_address[19] is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[19]
--operation mode is normal

G1_ad_ir_address[19] = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_19, pci_rstn, GLOBAL(pci_clk));

--G1L041Q is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[19]~81
--operation mode is normal

G1L041Q = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_19, pci_rstn, GLOBAL(pci_clk));


--M1_lt_adr[19] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_adr[19]
--operation mode is normal

M1_lt_adr[19] = AMPP_FUNCTION(M1_no_op_reg[1], G1_ad_ir_address[19]);

--M1L963 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_adr[19]~143
--operation mode is normal

M1L963 = AMPP_FUNCTION(M1_no_op_reg[1], G1_ad_ir_address[19]);


--A1L395 is ix2251~0
--operation mode is normal

A1L395 = (!M1_lt_adr[19] & !M1_lt_adr[5] & !M1_lt_adr[4]) & CASCADE(A1L197);

--A1L495 is ix2251~1
--operation mode is normal

A1L495 = (!M1_lt_adr[19] & !M1_lt_adr[5] & !M1_lt_adr[4]) & CASCADE(A1L197);


--ix2379 is ix2379
--operation mode is normal

ix2379 = dpm_ni2f_reg_sm_1 & !dpm_ni2f_fifo_h_reg_fifo_empty # !dpm_ni2f_reg_pci_rd_req_s;

--A1L249 is ix2379~1
--operation mode is normal

A1L249 = dpm_ni2f_reg_sm_1 & !dpm_ni2f_fifo_h_reg_fifo_empty # !dpm_ni2f_reg_pci_rd_req_s;

--A1L349 is ix2379~2
--operation mode is normal

A1L349 = dpm_ni2f_reg_sm_1 & !dpm_ni2f_fifo_h_reg_fifo_empty # !dpm_ni2f_reg_pci_rd_req_s;


--A1L077 is ix2317~0
--operation mode is normal

A1L077 = (!ix2380_lc & (dpm_ni2f_reg_sm_11 # !dpm_ni2f_fifo_h_reg_fifo_empty)) & CASCADE(A1L349);

--A1L177 is ix2317~1
--operation mode is normal

A1L177 = (!ix2380_lc & (dpm_ni2f_reg_sm_11 # !dpm_ni2f_fifo_h_reg_fifo_empty)) & CASCADE(A1L349);


--R1_decR[1] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|pcimt32_cd:cfg_adr_dec|decR[1]
--operation mode is normal

R1_decR[1] = AMPP_FUNCTION(M1_cfg_adr_dec_ena, R1_dec_up[0], G1_ad_ir_address[2], G1_ad_ir_address[3], pci_rstn, GLOBAL(pci_clk));

--R1L21Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|pcimt32_cd:cfg_adr_dec|decR[1]~127
--operation mode is normal

R1L21Q = AMPP_FUNCTION(M1_cfg_adr_dec_ena, R1_dec_up[0], G1_ad_ir_address[2], G1_ad_ir_address[3], pci_rstn, GLOBAL(pci_clk));


--G1_low_cben_IR_data[0] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_cben_IR_data[0]
--operation mode is normal

G1_low_cben_IR_data[0] = AMPP_FUNCTION(G1_cben_IR_ce_data, pci_cben_0, pci_rstn, GLOBAL(pci_clk));

--G1L614Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_cben_IR_data[0]~4
--operation mode is normal

G1L614Q = AMPP_FUNCTION(G1_cben_IR_ce_data, pci_cben_0, pci_rstn, GLOBAL(pci_clk));


--P1L771 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|stat_cmd_ena[0]~52
--operation mode is normal

P1L771 = AMPP_FUNCTION(M1_cfg_dat_vld, R1_decR[1], G1_low_cben_IR_data[0]);

--P1L871 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|stat_cmd_ena[0]~54
--operation mode is normal

P1L871 = AMPP_FUNCTION(M1_cfg_dat_vld, R1_decR[1], G1_low_cben_IR_data[0]);


--G1_low_ad_IR_data[8] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[8]
--operation mode is normal

G1_low_ad_IR_data[8] = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_8, pci_rstn, GLOBAL(pci_clk));

--G1L832Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[8]~38
--operation mode is normal

G1L832Q = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_8, pci_rstn, GLOBAL(pci_clk));


--G1_low_cben_IR_data[1] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_cben_IR_data[1]
--operation mode is normal

G1_low_cben_IR_data[1] = AMPP_FUNCTION(G1_cben_IR_ce_data, pci_cben_1, pci_rstn, GLOBAL(pci_clk));

--G1L814Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_cben_IR_data[1]~5
--operation mode is normal

G1L814Q = AMPP_FUNCTION(G1_cben_IR_ce_data, pci_cben_1, pci_rstn, GLOBAL(pci_clk));


--P1L971 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|stat_cmd_ena[1]~53
--operation mode is normal

P1L971 = AMPP_FUNCTION(M1_cfg_dat_vld, R1_decR[1], G1_low_cben_IR_data[1]);

--P1L081 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|stat_cmd_ena[1]~55
--operation mode is normal

P1L081 = AMPP_FUNCTION(M1_cfg_dat_vld, R1_decR[1], G1_low_cben_IR_data[1]);


--K1_xxlad[10] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|xxlad[10]
--operation mode is normal

K1_xxlad[10] = AMPP_FUNCTION(K1_xxlad[7], K1_xxlad[6], K1_xxlad[5], K1_xxlad[4]);

--K1L58 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|xxlad[10]~225
--operation mode is normal

K1L58 = AMPP_FUNCTION(K1_xxlad[7], K1_xxlad[6], K1_xxlad[5], K1_xxlad[4]);


--K1_xxlad[9] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|xxlad[9]
--operation mode is normal

K1_xxlad[9] = AMPP_FUNCTION(K1_xxlad[3], K1_xxlad[2], K1_xxlad[1], K1_xxlad[0]);

--K1L28 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|xxlad[9]~226
--operation mode is normal

K1L28 = AMPP_FUNCTION(K1_xxlad[3], K1_xxlad[2], K1_xxlad[1], K1_xxlad[0]);


--G1_cben_ir_address[0] is pci_contr:pci|pci_mt32:pci_mt32_inst|cben_ir_address[0]
--operation mode is normal

G1_cben_ir_address[0] = AMPP_FUNCTION(G1_cben_IR_ce_address, pci_cben_0, pci_rstn, GLOBAL(pci_clk));

--G1L571Q is pci_contr:pci|pci_mt32:pci_mt32_inst|cben_ir_address[0]~7
--operation mode is normal

G1L571Q = AMPP_FUNCTION(G1_cben_IR_ce_address, pci_cben_0, pci_rstn, GLOBAL(pci_clk));


--G1_cben_ir_address[3] is pci_contr:pci|pci_mt32:pci_mt32_inst|cben_ir_address[3]
--operation mode is normal

G1_cben_ir_address[3] = AMPP_FUNCTION(G1_cben_IR_ce_address, pci_cben_3, pci_rstn, GLOBAL(pci_clk));

--G1L181Q is pci_contr:pci|pci_mt32:pci_mt32_inst|cben_ir_address[3]~8
--operation mode is normal

G1L181Q = AMPP_FUNCTION(G1_cben_IR_ce_address, pci_cben_3, pci_rstn, GLOBAL(pci_clk));


--G1_cben_ir_address[2] is pci_contr:pci|pci_mt32:pci_mt32_inst|cben_ir_address[2]
--operation mode is normal

G1_cben_ir_address[2] = AMPP_FUNCTION(G1_cben_IR_ce_address, pci_cben_2, pci_rstn, GLOBAL(pci_clk));

--G1L971Q is pci_contr:pci|pci_mt32:pci_mt32_inst|cben_ir_address[2]~9
--operation mode is normal

G1L971Q = AMPP_FUNCTION(G1_cben_IR_ce_address, pci_cben_2, pci_rstn, GLOBAL(pci_clk));


--G1_cben_ir_address[1] is pci_contr:pci|pci_mt32:pci_mt32_inst|cben_ir_address[1]
--operation mode is normal

G1_cben_ir_address[1] = AMPP_FUNCTION(G1_cben_IR_ce_address, pci_cben_1, pci_rstn, GLOBAL(pci_clk));

--G1L771Q is pci_contr:pci|pci_mt32:pci_mt32_inst|cben_ir_address[1]~10
--operation mode is normal

G1L771Q = AMPP_FUNCTION(G1_cben_IR_ce_address, pci_cben_1, pci_rstn, GLOBAL(pci_clk));


--K1_xxlad[8] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|xxlad[8]
--operation mode is normal

K1_xxlad[8] = AMPP_FUNCTION(G1_cben_ir_address[0], G1_cben_ir_address[3], G1_cben_ir_address[2], G1_cben_ir_address[1]);

--K1L97 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|xxlad[8]~227
--operation mode is normal

K1L97 = AMPP_FUNCTION(G1_cben_ir_address[0], G1_cben_ir_address[3], G1_cben_ir_address[2], G1_cben_ir_address[1]);


--G1_low_ad_IR_data[4] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[4]
--operation mode is normal

G1_low_ad_IR_data[4] = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_4, pci_rstn, GLOBAL(pci_clk));

--G1L032Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[4]~39
--operation mode is normal

G1L032Q = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_4, pci_rstn, GLOBAL(pci_clk));


--G1_low_ad_IR_data[0] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[0]
--operation mode is normal

G1_low_ad_IR_data[0] = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_0, pci_rstn, GLOBAL(pci_clk));

--G1L222Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[0]~40
--operation mode is normal

G1L222Q = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_0, pci_rstn, GLOBAL(pci_clk));


--E1_counter_cell[12] is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[12]
--operation mode is up_dn_cntr

E1_counter_cell[12]_lut_out = E1_counter_cell[12] $ E1L73;
E1_counter_cell[12] = DFFEA(E1_counter_cell[12]_lut_out, GLOBAL(pci_clk), , , , , );

--E1L93Q is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[12]~2
--operation mode is up_dn_cntr

E1L93Q = E1_counter_cell[12];

--E1L04 is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[12]~COUT
--operation mode is up_dn_cntr

E1L04 = CARRY(E1_counter_cell[12] & (E1L73));


--J1_MS_ADR is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MS_ADR
--operation mode is normal

J1_MS_ADR = AMPP_FUNCTION(J1_MS_ENA, pci_gntn, pci_rstn, GLOBAL(pci_clk));

--J1L373Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MS_ADR~56
--operation mode is normal

J1L373Q = AMPP_FUNCTION(J1_MS_ENA, pci_gntn, pci_rstn, GLOBAL(pci_clk));


--J1_MS_ADR2 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MS_ADR2
--operation mode is normal

J1_MS_ADR2 = AMPP_FUNCTION(J1_MS_ADR, J1_dac_cyc_reg, pci_rstn, GLOBAL(pci_clk));

--J1L173Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MS_ADR2~56
--operation mode is normal

J1L173Q = AMPP_FUNCTION(J1_MS_ADR, J1_dac_cyc_reg, pci_rstn, GLOBAL(pci_clk));


--G1_ad_IR_ce_address is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_IR_ce_address
--operation mode is normal

G1_ad_IR_ce_address = AMPP_FUNCTION(G1_trg_ad_IR_ce_A, J1_MS_ADR, J1_MS_ADR2);

--G1L761 is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_IR_ce_address~15
--operation mode is normal

G1L761 = AMPP_FUNCTION(G1_trg_ad_IR_ce_A, J1_MS_ADR, J1_MS_ADR2);


--dpm_ni2f_reg_sm_8 is dpm_ni2f_reg_sm_8
--operation mode is normal

dpm_ni2f_reg_sm_8_lut_out = dpm_ni2f_reg_sm_7;
dpm_ni2f_reg_sm_8 = DFFEA(dpm_ni2f_reg_sm_8_lut_out, lcst, !ix2254, , , , );

--A1L734Q is dpm_ni2f_reg_sm_8~1
--operation mode is normal

A1L734Q = dpm_ni2f_reg_sm_8;


--ix2323 is ix2323
--operation mode is normal

ix2323 = G1_cben_ir_address[3] & G1_cben_ir_address[2] # !G1_cben_ir_address[3] & (G1_cben_ir_address[1]);

--A1L787 is ix2323~1
--operation mode is normal

A1L787 = G1_cben_ir_address[3] & G1_cben_ir_address[2] # !G1_cben_ir_address[3] & (G1_cben_ir_address[1]);

--A1L887 is ix2323~2
--operation mode is normal

A1L887 = G1_cben_ir_address[3] & G1_cben_ir_address[2] # !G1_cben_ir_address[3] & (G1_cben_ir_address[1]);


--M1_lt_ack_R_r4 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_ack_R_r4
--operation mode is normal

M1_lt_ack_R_r4 = AMPP_FUNCTION(M1_LR_PXFR, A1L0321, M1_rd_backoff, pci_rstn, GLOBAL(pci_clk), M1L51);

--M1L033Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_ack_R_r4~17
--operation mode is normal

M1L033Q = AMPP_FUNCTION(M1_LR_PXFR, A1L0321, M1_rd_backoff, pci_rstn, GLOBAL(pci_clk), M1L51);


--M1_lt_ack_R_r3 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_ack_R_r3
--operation mode is normal

M1_lt_ack_R_r3 = AMPP_FUNCTION(M1_lt_ack_R_r3_lc3, A1L0321, M1_rd_backoff, pci_rstn, GLOBAL(pci_clk), M1L21);

--M1L823Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_ack_R_r3~17
--operation mode is normal

M1L823Q = AMPP_FUNCTION(M1_lt_ack_R_r3_lc3, A1L0321, M1_rd_backoff, pci_rstn, GLOBAL(pci_clk), M1L21);


--M1_lt_ack_R_r1 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_ack_R_r1
--operation mode is normal

M1_lt_ack_R_r1 = AMPP_FUNCTION(M1_lt_ack_R_r1_lc[7], M1_lt_ack_R_r1_lc[8], M1_lt_ack_R_r1_lc[9], A1L0321, pci_rstn, GLOBAL(pci_clk));

--M1L513Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_ack_R_r1~8
--operation mode is normal

M1L513Q = AMPP_FUNCTION(M1_lt_ack_R_r1_lc[7], M1_lt_ack_R_r1_lc[8], M1_lt_ack_R_r1_lc[9], A1L0321, pci_rstn, GLOBAL(pci_clk));


--M1_lt_ack_R_r2 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_ack_R_r2
--operation mode is normal

M1_lt_ack_R_r2 = AMPP_FUNCTION(M1L85, A1L5321, pci_rstn, GLOBAL(pci_clk));

--M1L713Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_ack_R_r2~16
--operation mode is normal

M1L713Q = AMPP_FUNCTION(M1L85, A1L5321, pci_rstn, GLOBAL(pci_clk));


--M1L133 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_ack_R~18
--operation mode is normal

M1L133 = AMPP_FUNCTION(M1_lt_ack_R_r4, M1_lt_ack_R_r3, M1_lt_ack_R_r1, M1_lt_ack_R_r2);

--M1L233 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_ack_R~19
--operation mode is normal

M1L233 = AMPP_FUNCTION(M1_lt_ack_R_r4, M1_lt_ack_R_r3, M1_lt_ack_R_r1, M1_lt_ack_R_r2);


--P1_bar_hitR[0] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|bar_hitR[0]
--operation mode is normal

P1_bar_hitR[0] = AMPP_FUNCTION(P1_bar_hit[0], P1_bar_hitR[0], M1_bar_hit_rst, pci_rstn, GLOBAL(pci_clk));

--P1L011Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|bar_hitR[0]~31
--operation mode is normal

P1L011Q = AMPP_FUNCTION(P1_bar_hit[0], P1_bar_hitR[0], M1_bar_hit_rst, pci_rstn, GLOBAL(pci_clk));


--M1_lt_tsr[0] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_tsr[0]
--operation mode is normal

M1_lt_tsr[0] = AMPP_FUNCTION(M1_TS_IDLE_NOT, P1_bar_hitR[0]);

--M1L473 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_tsr[0]~8
--operation mode is normal

M1L473 = AMPP_FUNCTION(M1_TS_IDLE_NOT, P1_bar_hitR[0]);


--dpm_ni2f_reg_sm_7 is dpm_ni2f_reg_sm_7
--operation mode is normal

dpm_ni2f_reg_sm_7_lut_out = dpm_ni2f_reg_sm_6;
dpm_ni2f_reg_sm_7 = DFFEA(dpm_ni2f_reg_sm_7_lut_out, lcst, !ix2254, , , , );

--A1L534Q is dpm_ni2f_reg_sm_7~1
--operation mode is normal

A1L534Q = dpm_ni2f_reg_sm_7;


--ix2356_lc is ix2356_lc
--operation mode is normal

ix2356_lc = dpm_ni2f_reg_sm_9 # dpm_ni2f_reg_sm_7 # dpm_ni2f_reg_sm_5 # dpm_ni2f_reg_sm_3;

--A1L478 is ix2356_lc~0
--operation mode is normal

A1L478 = dpm_ni2f_reg_sm_9 # dpm_ni2f_reg_sm_7 # dpm_ni2f_reg_sm_5 # dpm_ni2f_reg_sm_3;


--G1_mstr_trg_low is pci_contr:pci|pci_mt32:pci_mt32_inst|mstr_trg_low
--operation mode is normal

G1_mstr_trg_low = AMPP_FUNCTION(G1_trg_ad_sel, G1_mstr_ad_sel, G1_trg_cfg_cyc_out, G1_mstr_trg_hr_dat_sel);

--G1L635 is pci_contr:pci|pci_mt32:pci_mt32_inst|mstr_trg_low~34
--operation mode is normal

G1L635 = AMPP_FUNCTION(G1_trg_ad_sel, G1_mstr_ad_sel, G1_trg_cfg_cyc_out, G1_mstr_trg_hr_dat_sel);


--M1L4 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|$00085~0
--operation mode is normal

M1L4 = AMPP_FUNCTION(M1_stop_OR_NOT, M1_trdy_OR_NOT, A1L0321);

--M1L5 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|$00085~3
--operation mode is normal

M1L5 = AMPP_FUNCTION(M1_stop_OR_NOT, M1_trdy_OR_NOT, A1L0321);

--M1L6 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|$00085~4
--operation mode is normal

M1L6 = AMPP_FUNCTION(M1_stop_OR_NOT, M1_trdy_OR_NOT, A1L0321);


--M1_TS_TURN_AR is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|TS_TURN_AR
--operation mode is normal

M1_TS_TURN_AR = AMPP_FUNCTION(A1L0321, M1_TS_DISC, M1_TS_TURN_AR_d_lc1, pci_rstn, GLOBAL(pci_clk));

--M1L345Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|TS_TURN_AR~28
--operation mode is normal

M1L345Q = AMPP_FUNCTION(A1L0321, M1_TS_DISC, M1_TS_TURN_AR_d_lc1, pci_rstn, GLOBAL(pci_clk));


--J1_MS_PARK is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MS_PARK
--operation mode is normal

J1_MS_PARK = AMPP_FUNCTION(J1_$00167, J1_MS_PARK, pci_gntn, J1_l_req_vld, pci_rstn, GLOBAL(pci_clk));

--J1L404Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MS_PARK~14
--operation mode is normal

J1L404Q = AMPP_FUNCTION(J1_$00167, J1_MS_PARK, pci_gntn, J1_l_req_vld, pci_rstn, GLOBAL(pci_clk));


--J1_cbe_oer_r2_d is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|cbe_oer_r2_d
--operation mode is normal

J1_cbe_oer_r2_d = AMPP_FUNCTION(J1_MS_ENA, J1_MS_PARK);

--J1L141 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|cbe_oer_r2_d~1
--operation mode is normal

J1L141 = AMPP_FUNCTION(J1_MS_ENA, J1_MS_PARK);


--J1L57 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|_~509
--operation mode is normal

J1L57 = AMPP_FUNCTION(J1_ad_oer_lc2d, J1_cbe_oer_r2_d, J1_ad_oer_lc2a, pci_gntn);

--J1L68 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|_~1140
--operation mode is normal

J1L68 = AMPP_FUNCTION(J1_ad_oer_lc2d, J1_cbe_oer_r2_d, J1_ad_oer_lc2a, pci_gntn);

--J1L78 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|_~1141
--operation mode is normal

J1L78 = AMPP_FUNCTION(J1_ad_oer_lc2d, J1_cbe_oer_r2_d, J1_ad_oer_lc2a, pci_gntn);


--J1_dac_cyc_reg is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|dac_cyc_reg
--operation mode is normal

J1_dac_cyc_reg = AMPP_FUNCTION(J1_MS_IDLE_not, J1_dac_cmd, J1_lm_adr_ack_R, J1_dac_cyc_reg, pci_rstn, GLOBAL(pci_clk));

--J1L051Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|dac_cyc_reg~21
--operation mode is normal

J1L051Q = AMPP_FUNCTION(J1_MS_IDLE_not, J1_dac_cmd, J1_lm_adr_ack_R, J1_dac_cyc_reg, pci_rstn, GLOBAL(pci_clk));


--G1_mstr_cbe_ce is pci_contr:pci|pci_mt32:pci_mt32_inst|mstr_cbe_ce
--operation mode is normal

G1_mstr_cbe_ce = AMPP_FUNCTION(J1_MS_ENA, J1_MS_ADR, J1_MS_ADR2, J1_dac_cyc_reg);

--G1L325 is pci_contr:pci|pci_mt32:pci_mt32_inst|mstr_cbe_ce~0
--operation mode is normal

G1L325 = AMPP_FUNCTION(J1_MS_ENA, J1_MS_ADR, J1_MS_ADR2, J1_dac_cyc_reg);


--J1L47 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|_~498
--operation mode is normal

J1L47 = AMPP_FUNCTION(J1_cbe_oer_r1_lc3, J1_cbe_oer_r1_lc1, J1_cbe_oer_r2_d, pci_gntn);

--J1L88 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|_~1142
--operation mode is normal

J1L88 = AMPP_FUNCTION(J1_cbe_oer_r1_lc3, J1_cbe_oer_r1_lc1, J1_cbe_oer_r2_d, pci_gntn);

--J1L98 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|_~1143
--operation mode is normal

J1L98 = AMPP_FUNCTION(J1_cbe_oer_r1_lc3, J1_cbe_oer_r1_lc1, J1_cbe_oer_r2_d, pci_gntn);


--M1L47 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|_~437
--operation mode is normal

M1L47 = AMPP_FUNCTION(A1L5321, M1_devsel_OR_lc[3], M1_devsel_OR_lc[1], A1L0321);

--M1L98 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|_~1498
--operation mode is normal

M1L98 = AMPP_FUNCTION(A1L5321, M1_devsel_OR_lc[3], M1_devsel_OR_lc[1], A1L0321);

--M1L09 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|_~1499
--operation mode is normal

M1L09 = AMPP_FUNCTION(A1L5321, M1_devsel_OR_lc[3], M1_devsel_OR_lc[1], A1L0321);


--M1_TS_ADR_VLD is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|TS_ADR_VLD
--operation mode is normal

M1_TS_ADR_VLD = AMPP_FUNCTION(P1_mbar_hit, M1L861, M1_TS_IDLE_NOT, pci_rstn, GLOBAL(pci_clk));

--M1L315Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|TS_ADR_VLD~9
--operation mode is normal

M1L315Q = AMPP_FUNCTION(P1_mbar_hit, M1L861, M1_TS_IDLE_NOT, pci_rstn, GLOBAL(pci_clk));


--M1_targ_oeR_reg_lc[4] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|targ_oeR_reg_lc[4]
--operation mode is normal

M1_targ_oeR_reg_lc[4] = AMPP_FUNCTION(M1_targ_oeR_reg_lc[3], M1_adr_phase_lc1, M1_targ_oeR_reg_lc[2], M1_targ_oeR_reg_lc[1]);

--M1L584 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|targ_oeR_reg_lc[4]~64
--operation mode is normal

M1L584 = AMPP_FUNCTION(M1_targ_oeR_reg_lc[3], M1_adr_phase_lc1, M1_targ_oeR_reg_lc[2], M1_targ_oeR_reg_lc[1]);


--J1_frame_or_carry is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|frame_or_carry
--operation mode is arithmetic

J1_frame_or_carry = AMPP_FUNCTION();

--J1L281 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|frame_or_carry~11
--operation mode is arithmetic

J1L281 = AMPP_FUNCTION();

--J1L381 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|frame_or_carry~COUT
--operation mode is arithmetic

J1L381 = AMPP_FUNCTION(A1L7421, J1_frame_or_lc3);


--J1L07 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|_~415
--operation mode is normal

J1L07 = AMPP_FUNCTION(A1L5421, J1L191, J1_frame_or_lc2, J1L381);

--J1L09 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|_~1144
--operation mode is normal

J1L09 = AMPP_FUNCTION(A1L5421, J1L191, J1_frame_or_lc2, J1L381);

--J1L19 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|_~1145
--operation mode is normal

J1L19 = AMPP_FUNCTION(A1L5421, J1L191, J1_frame_or_lc2, J1L381);


--J1_dac_cyc_strobe is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|dac_cyc_strobe
--operation mode is normal

J1_dac_cyc_strobe = AMPP_FUNCTION(J1_MS_ENA, J1_dac_cmd, pci_gntn, pci_rstn, GLOBAL(pci_clk));

--J1L251Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|dac_cyc_strobe~43
--operation mode is normal

J1L251Q = AMPP_FUNCTION(J1_MS_ENA, J1_dac_cmd, pci_gntn, pci_rstn, GLOBAL(pci_clk));


--J1_MS_DXFR is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MS_DXFR
--operation mode is normal

J1_MS_DXFR = AMPP_FUNCTION(J1_ms_dxfr_lc1, J1_ms_dxfr_lc2, A1L5421, A1L7421, pci_rstn, GLOBAL(pci_clk));

--J1L293Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MS_DXFR~24
--operation mode is normal

J1L293Q = AMPP_FUNCTION(J1_ms_dxfr_lc1, J1_ms_dxfr_lc2, A1L5421, A1L7421, pci_rstn, GLOBAL(pci_clk));


--J1_irdy_oer_lc1 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|irdy_oer_lc1
--operation mode is normal

J1_irdy_oer_lc1 = AMPP_FUNCTION(J1_MS_ADR, J1_MS_ADR2, J1_MS_DXFR);

--J1L322 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|irdy_oer_lc1~22
--operation mode is normal

J1L322 = AMPP_FUNCTION(J1_MS_ADR, J1_MS_ADR2, J1_MS_DXFR);


--G1_mstr_par_oe_lc2 is pci_contr:pci|pci_mt32:pci_mt32_inst|mstr_par_oe_lc2
--operation mode is normal

G1_mstr_par_oe_lc2 = AMPP_FUNCTION(J1_MS_ADR, J1_MS_ADR2, G1_trg_par_oe, G1_mstr_par_oe_lc1);

--G1L035 is pci_contr:pci|pci_mt32:pci_mt32_inst|mstr_par_oe_lc2~26
--operation mode is normal

G1L035 = AMPP_FUNCTION(J1_MS_ADR, J1_MS_ADR2, G1_trg_par_oe, G1_mstr_par_oe_lc1);


--J1_perr_vldR is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|perr_vldR
--operation mode is normal

J1_perr_vldR = AMPP_FUNCTION(J1_MS_DXFR, J1_irdy_or_not, pci_rstn, GLOBAL(pci_clk), J1L295);

--J1L395Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|perr_vldR~30
--operation mode is normal

J1L395Q = AMPP_FUNCTION(J1_MS_DXFR, J1_irdy_or_not, pci_rstn, GLOBAL(pci_clk), J1L295);


--M1_perr_vldR is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|perr_vldR
--operation mode is normal

M1_perr_vldR = AMPP_FUNCTION(N3_REG, M1_trdy_OR_NOT, pci_rstn, GLOBAL(pci_clk), M1L81);

--M1L034Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|perr_vldR~18
--operation mode is normal

M1L034Q = AMPP_FUNCTION(N3_REG, M1_trdy_OR_NOT, pci_rstn, GLOBAL(pci_clk), M1L81);


--K1_perr_or_not_lc1 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|perr_or_not_lc1
--operation mode is normal

K1_perr_or_not_lc1 = AMPP_FUNCTION(P1_cmd_reg[6], J1_perr_vldR, M1_perr_vldR);

--K1L8 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|perr_or_not_lc1~16
--operation mode is normal

K1L8 = AMPP_FUNCTION(P1_cmd_reg[6], J1_perr_vldR, M1_perr_vldR);


--K1_xxl[11] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|xxl[11]
--operation mode is normal

K1_xxl[11] = AMPP_FUNCTION(K1_xxl[10], K1_xxl[9], K1_xxl[8]);

--K1L15 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|xxl[11]~224
--operation mode is normal

K1L15 = AMPP_FUNCTION(K1_xxl[10], K1_xxl[9], K1_xxl[8]);


--J1_MS_TAR is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MS_TAR
--operation mode is normal

J1_MS_TAR = AMPP_FUNCTION(J1_$00173, J1_$00174, A1L5421, A1L7421, pci_rstn, GLOBAL(pci_clk));

--J1L714Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MS_TAR~30
--operation mode is normal

J1L714Q = AMPP_FUNCTION(J1_$00173, J1_$00174, A1L5421, A1L7421, pci_rstn, GLOBAL(pci_clk));


--J1_wr_rdn is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|wr_rdn
--operation mode is normal

J1_wr_rdn = AMPP_FUNCTION(J1_wr_rdn_set, J1_wr_rdn, J1_MS_TAR, pci_rstn, GLOBAL(pci_clk));

--J1L906Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|wr_rdn~16
--operation mode is normal

J1L906Q = AMPP_FUNCTION(J1_wr_rdn_set, J1_wr_rdn, J1_MS_TAR, pci_rstn, GLOBAL(pci_clk));


--M1_LW_IDLE_NOT is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LW_IDLE_NOT
--operation mode is normal

M1_LW_IDLE_NOT = AMPP_FUNCTION(M1_LW_DONE, M1_LW_IDLE_NOT, M1_LW_IDLE_lc1, pci_rstn, GLOBAL(pci_clk));

--M1L393Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LW_IDLE_NOT~24
--operation mode is normal

M1L393Q = AMPP_FUNCTION(M1_LW_DONE, M1_LW_IDLE_NOT, M1_LW_IDLE_lc1, pci_rstn, GLOBAL(pci_clk));


--M1L87 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|_~1448
--operation mode is normal

M1L87 = AMPP_FUNCTION(G1_cben_ir_address[0], G1_cben_ir_address[1], M1_adr_phase_lc1, M1_LW_IDLE_NOT);

--M1L19 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|_~1500
--operation mode is normal

M1L19 = AMPP_FUNCTION(G1_cben_ir_address[0], G1_cben_ir_address[1], M1_adr_phase_lc1, M1_LW_IDLE_NOT);


--M1L96 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|_~340
--operation mode is normal

M1L96 = AMPP_FUNCTION(M1L68, A1L0321, A1L5321, M1L954);

--M1L29 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|_~1501
--operation mode is normal

M1L29 = AMPP_FUNCTION(M1L68, A1L0321, A1L5321, M1L954);

--M1L39 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|_~1502
--operation mode is normal

M1L39 = AMPP_FUNCTION(M1L68, A1L0321, A1L5321, M1L954);


--M1L07 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|_~380
--operation mode is normal

M1L07 = AMPP_FUNCTION(A1L5321, M1_trdy_OR_NOT, M1L205);

--M1L49 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|_~1503
--operation mode is normal

M1L49 = AMPP_FUNCTION(A1L5321, M1_trdy_OR_NOT, M1L205);

--M1L59 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|_~1504
--operation mode is normal

M1L59 = AMPP_FUNCTION(A1L5321, M1_trdy_OR_NOT, M1L205);


--dpm_ni2f_reg_des_data_r_0 is dpm_ni2f_reg_des_data_r_0
--operation mode is normal

dpm_ni2f_reg_des_data_r_0_lut_out = DES_DATA[0];
dpm_ni2f_reg_des_data_r_0 = DFFEA(dpm_ni2f_reg_des_data_r_0_lut_out, lcst, , , , , );

--A1L933Q is dpm_ni2f_reg_des_data_r_0~1
--operation mode is normal

A1L933Q = dpm_ni2f_reg_des_data_r_0;


--dpm_ni2f_reg_des_data_r_1 is dpm_ni2f_reg_des_data_r_1
--operation mode is normal

dpm_ni2f_reg_des_data_r_1_lut_out = DES_DATA[1];
dpm_ni2f_reg_des_data_r_1 = DFFEA(dpm_ni2f_reg_des_data_r_1_lut_out, lcst, , , , , );

--A1L143Q is dpm_ni2f_reg_des_data_r_1~1
--operation mode is normal

A1L143Q = dpm_ni2f_reg_des_data_r_1;


--dpm_ni2f_reg_des_data_r_2 is dpm_ni2f_reg_des_data_r_2
--operation mode is normal

dpm_ni2f_reg_des_data_r_2_lut_out = DES_DATA[2];
dpm_ni2f_reg_des_data_r_2 = DFFEA(dpm_ni2f_reg_des_data_r_2_lut_out, lcst, , , , , );

--A1L343Q is dpm_ni2f_reg_des_data_r_2~1
--operation mode is normal

A1L343Q = dpm_ni2f_reg_des_data_r_2;


--dpm_ni2f_reg_des_data_r_3 is dpm_ni2f_reg_des_data_r_3
--operation mode is normal

dpm_ni2f_reg_des_data_r_3_lut_out = DES_DATA[3];
dpm_ni2f_reg_des_data_r_3 = DFFEA(dpm_ni2f_reg_des_data_r_3_lut_out, lcst, , , , , );

--A1L543Q is dpm_ni2f_reg_des_data_r_3~1
--operation mode is normal

A1L543Q = dpm_ni2f_reg_des_data_r_3;


--dpm_ni2f_reg_des_data_r_4 is dpm_ni2f_reg_des_data_r_4
--operation mode is normal

dpm_ni2f_reg_des_data_r_4_lut_out = DES_DATA[4];
dpm_ni2f_reg_des_data_r_4 = DFFEA(dpm_ni2f_reg_des_data_r_4_lut_out, lcst, , , , , );

--A1L743Q is dpm_ni2f_reg_des_data_r_4~1
--operation mode is normal

A1L743Q = dpm_ni2f_reg_des_data_r_4;


--dpm_ni2f_reg_des_data_r_5 is dpm_ni2f_reg_des_data_r_5
--operation mode is normal

dpm_ni2f_reg_des_data_r_5_lut_out = DES_DATA[5];
dpm_ni2f_reg_des_data_r_5 = DFFEA(dpm_ni2f_reg_des_data_r_5_lut_out, lcst, , , , , );

--A1L943Q is dpm_ni2f_reg_des_data_r_5~1
--operation mode is normal

A1L943Q = dpm_ni2f_reg_des_data_r_5;


--dpm_ni2f_reg_des_data_r_6 is dpm_ni2f_reg_des_data_r_6
--operation mode is normal

dpm_ni2f_reg_des_data_r_6_lut_out = DES_DATA[6];
dpm_ni2f_reg_des_data_r_6 = DFFEA(dpm_ni2f_reg_des_data_r_6_lut_out, lcst, , , , , );

--A1L153Q is dpm_ni2f_reg_des_data_r_6~1
--operation mode is normal

A1L153Q = dpm_ni2f_reg_des_data_r_6;


--dpm_ni2f_reg_des_data_r_7 is dpm_ni2f_reg_des_data_r_7
--operation mode is normal

dpm_ni2f_reg_des_data_r_7_lut_out = DES_DATA[7];
dpm_ni2f_reg_des_data_r_7 = DFFEA(dpm_ni2f_reg_des_data_r_7_lut_out, lcst, , , , , );

--A1L353Q is dpm_ni2f_reg_des_data_r_7~1
--operation mode is normal

A1L353Q = dpm_ni2f_reg_des_data_r_7;


--dpm_ni2f_reg_des_data_r_8 is dpm_ni2f_reg_des_data_r_8
--operation mode is normal

dpm_ni2f_reg_des_data_r_8_lut_out = DES_DATA[8];
dpm_ni2f_reg_des_data_r_8 = DFFEA(dpm_ni2f_reg_des_data_r_8_lut_out, lcst, , , , , );

--A1L553Q is dpm_ni2f_reg_des_data_r_8~1
--operation mode is normal

A1L553Q = dpm_ni2f_reg_des_data_r_8;


--dpm_ni2f_reg_des_data_r_9 is dpm_ni2f_reg_des_data_r_9
--operation mode is normal

dpm_ni2f_reg_des_data_r_9_lut_out = DES_DATA[9];
dpm_ni2f_reg_des_data_r_9 = DFFEA(dpm_ni2f_reg_des_data_r_9_lut_out, lcst, , , , , );

--A1L753Q is dpm_ni2f_reg_des_data_r_9~1
--operation mode is normal

A1L753Q = dpm_ni2f_reg_des_data_r_9;


--dpm_ni2f_reg_des_data_r_10 is dpm_ni2f_reg_des_data_r_10
--operation mode is normal

dpm_ni2f_reg_des_data_r_10_lut_out = DES_DATA[10];
dpm_ni2f_reg_des_data_r_10 = DFFEA(dpm_ni2f_reg_des_data_r_10_lut_out, lcst, , , , , );

--A1L953Q is dpm_ni2f_reg_des_data_r_10~1
--operation mode is normal

A1L953Q = dpm_ni2f_reg_des_data_r_10;


--dpm_ni2f_reg_des_data_r_11 is dpm_ni2f_reg_des_data_r_11
--operation mode is normal

dpm_ni2f_reg_des_data_r_11_lut_out = DES_DATA[11];
dpm_ni2f_reg_des_data_r_11 = DFFEA(dpm_ni2f_reg_des_data_r_11_lut_out, lcst, , , , , );

--A1L163Q is dpm_ni2f_reg_des_data_r_11~1
--operation mode is normal

A1L163Q = dpm_ni2f_reg_des_data_r_11;


--dpm_ni2f_reg_des_data_r_12 is dpm_ni2f_reg_des_data_r_12
--operation mode is normal

dpm_ni2f_reg_des_data_r_12_lut_out = DES_DATA[12];
dpm_ni2f_reg_des_data_r_12 = DFFEA(dpm_ni2f_reg_des_data_r_12_lut_out, lcst, , , , , );

--A1L363Q is dpm_ni2f_reg_des_data_r_12~1
--operation mode is normal

A1L363Q = dpm_ni2f_reg_des_data_r_12;


--dpm_ni2f_reg_des_data_r_13 is dpm_ni2f_reg_des_data_r_13
--operation mode is normal

dpm_ni2f_reg_des_data_r_13_lut_out = DES_DATA[13];
dpm_ni2f_reg_des_data_r_13 = DFFEA(dpm_ni2f_reg_des_data_r_13_lut_out, lcst, , , , , );

--A1L563Q is dpm_ni2f_reg_des_data_r_13~1
--operation mode is normal

A1L563Q = dpm_ni2f_reg_des_data_r_13;


--dpm_ni2f_reg_des_data_r_14 is dpm_ni2f_reg_des_data_r_14
--operation mode is normal

dpm_ni2f_reg_des_data_r_14_lut_out = DES_DATA[14];
dpm_ni2f_reg_des_data_r_14 = DFFEA(dpm_ni2f_reg_des_data_r_14_lut_out, lcst, , , , , );

--A1L763Q is dpm_ni2f_reg_des_data_r_14~1
--operation mode is normal

A1L763Q = dpm_ni2f_reg_des_data_r_14;


--dpm_ni2f_reg_des_data_r_15 is dpm_ni2f_reg_des_data_r_15
--operation mode is normal

dpm_ni2f_reg_des_data_r_15_lut_out = DES_DATA[15];
dpm_ni2f_reg_des_data_r_15 = DFFEA(dpm_ni2f_reg_des_data_r_15_lut_out, lcst, , , , , );

--A1L963Q is dpm_ni2f_reg_des_data_r_15~1
--operation mode is normal

A1L963Q = dpm_ni2f_reg_des_data_r_15;


--dpm_ni2f_fifo_h_reg_nwords_10 is dpm_ni2f_fifo_h_reg_nwords_10
--operation mode is normal

dpm_ni2f_fifo_h_reg_nwords_10_lut_out = !A1L396;
dpm_ni2f_fifo_h_reg_nwords_10 = DFFEA(dpm_ni2f_fifo_h_reg_nwords_10_lut_out, lcst, !dpm_ni2f_reg_sreset120, , ix2302_lc, , );

--A1L111Q is dpm_ni2f_fifo_h_reg_nwords_10~1
--operation mode is normal

A1L111Q = dpm_ni2f_fifo_h_reg_nwords_10;


--dpm_ni2f_fifo_h_reg_nwords_9 is dpm_ni2f_fifo_h_reg_nwords_9
--operation mode is normal

dpm_ni2f_fifo_h_reg_nwords_9_lut_out = !A1L596;
dpm_ni2f_fifo_h_reg_nwords_9 = DFFEA(dpm_ni2f_fifo_h_reg_nwords_9_lut_out, lcst, !dpm_ni2f_reg_sreset120, , ix2302_lc, , );

--A1L901Q is dpm_ni2f_fifo_h_reg_nwords_9~1
--operation mode is normal

A1L901Q = dpm_ni2f_fifo_h_reg_nwords_9;


--dpm_ni2f_fifo_h_reg_nwords_8 is dpm_ni2f_fifo_h_reg_nwords_8
--operation mode is normal

dpm_ni2f_fifo_h_reg_nwords_8_lut_out = !A1L796;
dpm_ni2f_fifo_h_reg_nwords_8 = DFFEA(dpm_ni2f_fifo_h_reg_nwords_8_lut_out, lcst, !dpm_ni2f_reg_sreset120, , ix2302_lc, , );

--A1L701Q is dpm_ni2f_fifo_h_reg_nwords_8~1
--operation mode is normal

A1L701Q = dpm_ni2f_fifo_h_reg_nwords_8;


--dpm_ni2f_fifo_h_reg_nwords_7 is dpm_ni2f_fifo_h_reg_nwords_7
--operation mode is normal

dpm_ni2f_fifo_h_reg_nwords_7_lut_out = !A1L996;
dpm_ni2f_fifo_h_reg_nwords_7 = DFFEA(dpm_ni2f_fifo_h_reg_nwords_7_lut_out, lcst, !dpm_ni2f_reg_sreset120, , ix2302_lc, , );

--A1L501Q is dpm_ni2f_fifo_h_reg_nwords_7~1
--operation mode is normal

A1L501Q = dpm_ni2f_fifo_h_reg_nwords_7;


--dpm_ni2f_fifo_h_modgen_eq_73_ix17 is dpm_ni2f_fifo_h_modgen_eq_73_ix17
--operation mode is normal

dpm_ni2f_fifo_h_modgen_eq_73_ix17 = !dpm_ni2f_fifo_h_reg_nwords_10 & !dpm_ni2f_fifo_h_reg_nwords_9 & !dpm_ni2f_fifo_h_reg_nwords_8 & !dpm_ni2f_fifo_h_reg_nwords_7;

--A1L97 is dpm_ni2f_fifo_h_modgen_eq_73_ix17~1
--operation mode is normal

A1L97 = !dpm_ni2f_fifo_h_reg_nwords_10 & !dpm_ni2f_fifo_h_reg_nwords_9 & !dpm_ni2f_fifo_h_reg_nwords_8 & !dpm_ni2f_fifo_h_reg_nwords_7;

--A1L08 is dpm_ni2f_fifo_h_modgen_eq_73_ix17~2
--operation mode is normal

A1L08 = !dpm_ni2f_fifo_h_reg_nwords_10 & !dpm_ni2f_fifo_h_reg_nwords_9 & !dpm_ni2f_fifo_h_reg_nwords_8 & !dpm_ni2f_fifo_h_reg_nwords_7;


--dpm_ni2f_fifo_h_reg_nwords_6 is dpm_ni2f_fifo_h_reg_nwords_6
--operation mode is normal

dpm_ni2f_fifo_h_reg_nwords_6_lut_out = !A1L107;
dpm_ni2f_fifo_h_reg_nwords_6 = DFFEA(dpm_ni2f_fifo_h_reg_nwords_6_lut_out, lcst, !dpm_ni2f_reg_sreset120, , ix2302_lc, , );

--A1L301Q is dpm_ni2f_fifo_h_reg_nwords_6~1
--operation mode is normal

A1L301Q = dpm_ni2f_fifo_h_reg_nwords_6;


--dpm_ni2f_fifo_h_reg_nwords_5 is dpm_ni2f_fifo_h_reg_nwords_5
--operation mode is normal

dpm_ni2f_fifo_h_reg_nwords_5_lut_out = !A1L307;
dpm_ni2f_fifo_h_reg_nwords_5 = DFFEA(dpm_ni2f_fifo_h_reg_nwords_5_lut_out, lcst, !dpm_ni2f_reg_sreset120, , ix2302_lc, , );

--A1L101Q is dpm_ni2f_fifo_h_reg_nwords_5~1
--operation mode is normal

A1L101Q = dpm_ni2f_fifo_h_reg_nwords_5;


--dpm_ni2f_fifo_h_reg_nwords_4 is dpm_ni2f_fifo_h_reg_nwords_4
--operation mode is normal

dpm_ni2f_fifo_h_reg_nwords_4_lut_out = !A1L507;
dpm_ni2f_fifo_h_reg_nwords_4 = DFFEA(dpm_ni2f_fifo_h_reg_nwords_4_lut_out, lcst, !dpm_ni2f_reg_sreset120, , ix2302_lc, , );

--A1L99Q is dpm_ni2f_fifo_h_reg_nwords_4~1
--operation mode is normal

A1L99Q = dpm_ni2f_fifo_h_reg_nwords_4;


--dpm_ni2f_fifo_h_reg_nwords_3 is dpm_ni2f_fifo_h_reg_nwords_3
--operation mode is normal

dpm_ni2f_fifo_h_reg_nwords_3_lut_out = !A1L707;
dpm_ni2f_fifo_h_reg_nwords_3 = DFFEA(dpm_ni2f_fifo_h_reg_nwords_3_lut_out, lcst, !dpm_ni2f_reg_sreset120, , ix2302_lc, , );

--A1L79Q is dpm_ni2f_fifo_h_reg_nwords_3~1
--operation mode is normal

A1L79Q = dpm_ni2f_fifo_h_reg_nwords_3;


--A1L18 is dpm_ni2f_fifo_h_modgen_eq_73_ix21~0
--operation mode is normal

A1L18 = (!dpm_ni2f_fifo_h_reg_nwords_6 & !dpm_ni2f_fifo_h_reg_nwords_5 & !dpm_ni2f_fifo_h_reg_nwords_4 & !dpm_ni2f_fifo_h_reg_nwords_3) & CASCADE(A1L08);

--A1L28 is dpm_ni2f_fifo_h_modgen_eq_73_ix21~2
--operation mode is normal

A1L28 = (!dpm_ni2f_fifo_h_reg_nwords_6 & !dpm_ni2f_fifo_h_reg_nwords_5 & !dpm_ni2f_fifo_h_reg_nwords_4 & !dpm_ni2f_fifo_h_reg_nwords_3) & CASCADE(A1L08);

--A1L38 is dpm_ni2f_fifo_h_modgen_eq_73_ix21~3
--operation mode is normal

A1L38 = (!dpm_ni2f_fifo_h_reg_nwords_6 & !dpm_ni2f_fifo_h_reg_nwords_5 & !dpm_ni2f_fifo_h_reg_nwords_4 & !dpm_ni2f_fifo_h_reg_nwords_3) & CASCADE(A1L08);


--ix2301_lc is ix2301_lc
--operation mode is normal

ix2301_lc = dpm_ni2f_reg_rdreq_fifo & dpm_ni2f_fifo_h_reg_fifo_empty & (dpm_ni2f_fifo_h_reg_fifo_full # !dpm_ni2f_reg_des_valid_data) # !dpm_ni2f_reg_rdreq_fifo & dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_h_reg_fifo_full;

--A1L027 is ix2301_lc~0
--operation mode is normal

A1L027 = dpm_ni2f_reg_rdreq_fifo & dpm_ni2f_fifo_h_reg_fifo_empty & (dpm_ni2f_fifo_h_reg_fifo_full # !dpm_ni2f_reg_des_valid_data) # !dpm_ni2f_reg_rdreq_fifo & dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_h_reg_fifo_full;


--ix2314 is ix2314
--operation mode is normal

ix2314 = M1L133 & M1_lt_tsr[0];

--A1L267 is ix2314~1
--operation mode is normal

A1L267 = M1L133 & M1_lt_tsr[0];

--A1L367 is ix2314~2
--operation mode is normal

A1L367 = M1L133 & M1_lt_tsr[0];


--A1L987 is ix2324~0
--operation mode is normal

A1L987 = (G1_cben_ir_address[1] & G1_cben_ir_address[0] & (G1_cben_ir_address[2] # !G1_cben_ir_address[3])) & CASCADE(A1L367);

--A1L097 is ix2324~2
--operation mode is normal

A1L097 = (G1_cben_ir_address[1] & G1_cben_ir_address[0] & (G1_cben_ir_address[2] # !G1_cben_ir_address[3])) & CASCADE(A1L367);

--A1L197 is ix2324~3
--operation mode is normal

A1L197 = (G1_cben_ir_address[1] & G1_cben_ir_address[0] & (G1_cben_ir_address[2] # !G1_cben_ir_address[3])) & CASCADE(A1L367);


--ix2380_lc is ix2380_lc
--operation mode is normal

ix2380_lc = !dpm_ni2f_reg_sm_11 & !dpm_ni2f_reg_sm_1 & dpm_ni2f_reg_sm_0;

--A1L649 is ix2380_lc~0
--operation mode is normal

A1L649 = !dpm_ni2f_reg_sm_11 & !dpm_ni2f_reg_sm_1 & dpm_ni2f_reg_sm_0;


--M1_cfg_cyc is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|cfg_cyc
--operation mode is normal

M1_cfg_cyc = AMPP_FUNCTION(M1L161, M1_cfg_cyc, M1_TS_IDLE_NOT, M1_adr_phase_lc1, pci_rstn, GLOBAL(pci_clk));

--M1L261Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|cfg_cyc~118
--operation mode is normal

M1L261Q = AMPP_FUNCTION(M1L161, M1_cfg_cyc, M1_TS_IDLE_NOT, M1_adr_phase_lc1, pci_rstn, GLOBAL(pci_clk));


--M1_TS_DXFR_R is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|TS_DXFR_R
--operation mode is normal

M1_TS_DXFR_R = AMPP_FUNCTION(M1_TS_DXFR, pci_rstn, GLOBAL(pci_clk));

--M1L925Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|TS_DXFR_R~1
--operation mode is normal

M1L925Q = AMPP_FUNCTION(M1_TS_DXFR, pci_rstn, GLOBAL(pci_clk));


--M1_TS_DXFR is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|TS_DXFR
--operation mode is normal

M1_TS_DXFR = AMPP_FUNCTION(M1L625, M1L88, M1_TS_DXFR_d_lc[2], A1L0321, pci_rstn, GLOBAL(pci_clk));

--M1L035Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|TS_DXFR~13
--operation mode is normal

M1L035Q = AMPP_FUNCTION(M1L625, M1L88, M1_TS_DXFR_d_lc[2], A1L0321, pci_rstn, GLOBAL(pci_clk));


--M1_cfg_dat_vld is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|cfg_dat_vld
--operation mode is normal

M1_cfg_dat_vld = AMPP_FUNCTION(N3_REG, M1_cfg_cyc, M1_TS_DXFR_R, M1_TS_DXFR);

--M1L761 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|cfg_dat_vld~26
--operation mode is normal

M1L761 = AMPP_FUNCTION(N3_REG, M1_cfg_cyc, M1_TS_DXFR_R, M1_TS_DXFR);


--M1_frame_IR is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|frame_IR
--operation mode is normal

M1_frame_IR = AMPP_FUNCTION(A1L0321, pci_rstn, GLOBAL(pci_clk));

--M1L581Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|frame_IR~1
--operation mode is normal

M1L581Q = AMPP_FUNCTION(A1L0321, pci_rstn, GLOBAL(pci_clk));


--M1_frame_I1R is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|frame_I1R
--operation mode is normal

M1_frame_I1R = AMPP_FUNCTION(M1_frame_IR, pci_rstn, GLOBAL(pci_clk));

--M1L381Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|frame_I1R~1
--operation mode is normal

M1L381Q = AMPP_FUNCTION(M1_frame_IR, pci_rstn, GLOBAL(pci_clk));


--M1_adr_phase_lc1 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|adr_phase_lc1
--operation mode is normal

M1_adr_phase_lc1 = AMPP_FUNCTION(M1_frame_IR, M1_frame_I1R);

--M1L041 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|adr_phase_lc1~25
--operation mode is normal

M1L041 = AMPP_FUNCTION(M1_frame_IR, M1_frame_I1R);


--G1_ad_ir_address[31] is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[31]
--operation mode is normal

G1_ad_ir_address[31] = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_31, pci_rstn, GLOBAL(pci_clk));

--G1L461Q is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[31]~82
--operation mode is normal

G1L461Q = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_31, pci_rstn, GLOBAL(pci_clk));


--G1_ad_ir_address[30] is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[30]
--operation mode is normal

G1_ad_ir_address[30] = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_30, pci_rstn, GLOBAL(pci_clk));

--G1L261Q is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[30]~83
--operation mode is normal

G1L261Q = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_30, pci_rstn, GLOBAL(pci_clk));


--G1_ad_ir_address[29] is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[29]
--operation mode is normal

G1_ad_ir_address[29] = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_29, pci_rstn, GLOBAL(pci_clk));

--G1L061Q is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[29]~84
--operation mode is normal

G1L061Q = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_29, pci_rstn, GLOBAL(pci_clk));


--G1_ad_ir_address[28] is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[28]
--operation mode is normal

G1_ad_ir_address[28] = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_28, pci_rstn, GLOBAL(pci_clk));

--G1L851Q is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[28]~85
--operation mode is normal

G1L851Q = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_28, pci_rstn, GLOBAL(pci_clk));


--K1_xxlad[7] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|xxlad[7]
--operation mode is normal

K1_xxlad[7] = AMPP_FUNCTION(G1_ad_ir_address[31], G1_ad_ir_address[30], G1_ad_ir_address[29], G1_ad_ir_address[28]);

--K1L67 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|xxlad[7]~228
--operation mode is normal

K1L67 = AMPP_FUNCTION(G1_ad_ir_address[31], G1_ad_ir_address[30], G1_ad_ir_address[29], G1_ad_ir_address[28]);


--G1_ad_ir_address[27] is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[27]
--operation mode is normal

G1_ad_ir_address[27] = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_27, pci_rstn, GLOBAL(pci_clk));

--G1L651Q is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[27]~86
--operation mode is normal

G1L651Q = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_27, pci_rstn, GLOBAL(pci_clk));


--G1_ad_ir_address[26] is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[26]
--operation mode is normal

G1_ad_ir_address[26] = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_26, pci_rstn, GLOBAL(pci_clk));

--G1L451Q is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[26]~87
--operation mode is normal

G1L451Q = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_26, pci_rstn, GLOBAL(pci_clk));


--G1_ad_ir_address[25] is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[25]
--operation mode is normal

G1_ad_ir_address[25] = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_25, pci_rstn, GLOBAL(pci_clk));

--G1L251Q is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[25]~88
--operation mode is normal

G1L251Q = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_25, pci_rstn, GLOBAL(pci_clk));


--G1_ad_ir_address[24] is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[24]
--operation mode is normal

G1_ad_ir_address[24] = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_24, pci_rstn, GLOBAL(pci_clk));

--G1L051Q is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[24]~89
--operation mode is normal

G1L051Q = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_24, pci_rstn, GLOBAL(pci_clk));


--K1_xxlad[6] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|xxlad[6]
--operation mode is normal

K1_xxlad[6] = AMPP_FUNCTION(G1_ad_ir_address[27], G1_ad_ir_address[26], G1_ad_ir_address[25], G1_ad_ir_address[24]);

--K1L37 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|xxlad[6]~229
--operation mode is normal

K1L37 = AMPP_FUNCTION(G1_ad_ir_address[27], G1_ad_ir_address[26], G1_ad_ir_address[25], G1_ad_ir_address[24]);


--G1_ad_ir_address[23] is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[23]
--operation mode is normal

G1_ad_ir_address[23] = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_23, pci_rstn, GLOBAL(pci_clk));

--G1L841Q is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[23]~90
--operation mode is normal

G1L841Q = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_23, pci_rstn, GLOBAL(pci_clk));


--G1_ad_ir_address[22] is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[22]
--operation mode is normal

G1_ad_ir_address[22] = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_22, pci_rstn, GLOBAL(pci_clk));

--G1L641Q is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[22]~91
--operation mode is normal

G1L641Q = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_22, pci_rstn, GLOBAL(pci_clk));


--G1_ad_ir_address[21] is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[21]
--operation mode is normal

G1_ad_ir_address[21] = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_21, pci_rstn, GLOBAL(pci_clk));

--G1L441Q is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[21]~92
--operation mode is normal

G1L441Q = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_21, pci_rstn, GLOBAL(pci_clk));


--G1_ad_ir_address[20] is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[20]
--operation mode is normal

G1_ad_ir_address[20] = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_20, pci_rstn, GLOBAL(pci_clk));

--G1L241Q is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[20]~93
--operation mode is normal

G1L241Q = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_20, pci_rstn, GLOBAL(pci_clk));


--K1_xxlad[5] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|xxlad[5]
--operation mode is normal

K1_xxlad[5] = AMPP_FUNCTION(G1_ad_ir_address[23], G1_ad_ir_address[22], G1_ad_ir_address[21], G1_ad_ir_address[20]);

--K1L07 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|xxlad[5]~230
--operation mode is normal

K1L07 = AMPP_FUNCTION(G1_ad_ir_address[23], G1_ad_ir_address[22], G1_ad_ir_address[21], G1_ad_ir_address[20]);


--K1_xxlad[4] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|xxlad[4]
--operation mode is normal

K1_xxlad[4] = AMPP_FUNCTION(G1_ad_ir_address[16], G1_ad_ir_address[17], G1_ad_ir_address[18], G1_ad_ir_address[19]);

--K1L76 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|xxlad[4]~231
--operation mode is normal

K1L76 = AMPP_FUNCTION(G1_ad_ir_address[16], G1_ad_ir_address[17], G1_ad_ir_address[18], G1_ad_ir_address[19]);


--K1_xxlad[3] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|xxlad[3]
--operation mode is normal

K1_xxlad[3] = AMPP_FUNCTION(G1_ad_ir_address[12], G1_ad_ir_address[13], G1_ad_ir_address[14], G1_ad_ir_address[15]);

--K1L46 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|xxlad[3]~232
--operation mode is normal

K1L46 = AMPP_FUNCTION(G1_ad_ir_address[12], G1_ad_ir_address[13], G1_ad_ir_address[14], G1_ad_ir_address[15]);


--K1_xxlad[2] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|xxlad[2]
--operation mode is normal

K1_xxlad[2] = AMPP_FUNCTION(G1_ad_ir_address[8], G1_ad_ir_address[9], G1_ad_ir_address[10], G1_ad_ir_address[11]);

--K1L16 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|xxlad[2]~233
--operation mode is normal

K1L16 = AMPP_FUNCTION(G1_ad_ir_address[8], G1_ad_ir_address[9], G1_ad_ir_address[10], G1_ad_ir_address[11]);


--K1_xxlad[1] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|xxlad[1]
--operation mode is normal

K1_xxlad[1] = AMPP_FUNCTION(G1_ad_ir_address[4], G1_ad_ir_address[5], G1_ad_ir_address[6], G1_ad_ir_address[7]);

--K1L85 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|xxlad[1]~234
--operation mode is normal

K1L85 = AMPP_FUNCTION(G1_ad_ir_address[4], G1_ad_ir_address[5], G1_ad_ir_address[6], G1_ad_ir_address[7]);


--G1_ad_ir_address[1] is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[1]
--operation mode is normal

G1_ad_ir_address[1] = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_1, pci_rstn, GLOBAL(pci_clk));

--G1L401Q is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[1]~94
--operation mode is normal

G1L401Q = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_1, pci_rstn, GLOBAL(pci_clk));


--G1_ad_ir_address[0] is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[0]
--operation mode is normal

G1_ad_ir_address[0] = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_0, pci_rstn, GLOBAL(pci_clk));

--G1L201Q is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ir_address[0]~95
--operation mode is normal

G1L201Q = AMPP_FUNCTION(G1_ad_IR_ce_address, pci_ad_0, pci_rstn, GLOBAL(pci_clk));


--K1_xxlad[0] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|xxlad[0]
--operation mode is normal

K1_xxlad[0] = AMPP_FUNCTION(G1_ad_ir_address[2], G1_ad_ir_address[3], G1_ad_ir_address[1], G1_ad_ir_address[0]);

--K1L55 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|xxlad[0]~235
--operation mode is normal

K1L55 = AMPP_FUNCTION(G1_ad_ir_address[2], G1_ad_ir_address[3], G1_ad_ir_address[1], G1_ad_ir_address[0]);


--G1_ad_IR_ce_data is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_IR_ce_data
--operation mode is normal

G1_ad_IR_ce_data = AMPP_FUNCTION(G1_mstr_ad_IR_ce_D, G1_trg_ad_IR_ce_D);

--G1L071 is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_IR_ce_data~1
--operation mode is normal

G1L071 = AMPP_FUNCTION(G1_mstr_ad_IR_ce_D, G1_trg_ad_IR_ce_D);


--ix2313 is ix2313
--operation mode is normal

ix2313 = !M1_lt_adr[19] & !M1_lt_adr[5] & M1_lt_adr[4];

--A1L957 is ix2313~1
--operation mode is normal

A1L957 = !M1_lt_adr[19] & !M1_lt_adr[5] & M1_lt_adr[4];

--A1L067 is ix2313~2
--operation mode is normal

A1L067 = !M1_lt_adr[19] & !M1_lt_adr[5] & M1_lt_adr[4];


--A1L078 is ix2355~0
--operation mode is normal

A1L078 = (G1_cben_ir_address[1] & G1_cben_ir_address[0] & !ix2382_lc) & CASCADE(A1L757);

--A1L178 is ix2355~1
--operation mode is normal

A1L178 = (G1_cben_ir_address[1] & G1_cben_ir_address[0] & !ix2382_lc) & CASCADE(A1L757);


--E1_counter_cell[11] is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[11]
--operation mode is up_dn_cntr

E1_counter_cell[11]_lut_out = E1_counter_cell[11] $ E1L43;
E1_counter_cell[11] = DFFEA(E1_counter_cell[11]_lut_out, GLOBAL(pci_clk), , , , , );

--E1L63Q is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[11]~3
--operation mode is up_dn_cntr

E1L63Q = E1_counter_cell[11];

--E1L73 is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[11]~COUT
--operation mode is up_dn_cntr

E1L73 = CARRY(E1_counter_cell[11] & (E1L43));


--G1_trg_ad_IR_ce_A is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_ad_IR_ce_A
--operation mode is normal

G1_trg_ad_IR_ce_A = AMPP_FUNCTION(M1_ad_ir_ce_A_lc1, M1_ad_ir_ce_A_lc2);

--G1L445 is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_ad_IR_ce_A~7
--operation mode is normal

G1L445 = AMPP_FUNCTION(M1_ad_ir_ce_A_lc1, M1_ad_ir_ce_A_lc2);


--J1_adr_phase_end_lc1 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|adr_phase_end_lc1
--operation mode is normal

J1_adr_phase_end_lc1 = AMPP_FUNCTION(J1_MS_ADR, J1_dac_cyc_reg);

--J1L621 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|adr_phase_end_lc1~8
--operation mode is normal

J1L621 = AMPP_FUNCTION(J1_MS_ADR, J1_dac_cyc_reg);


--M1_LW_LXFR is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LW_LXFR
--operation mode is normal

M1_LW_LXFR = AMPP_FUNCTION(M1_LW_LXFR_lc[2], M1_LW_LXFR_lc[1], pci_rstn, GLOBAL(pci_clk), M1L104);

--M1L314Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LW_LXFR~0
--operation mode is normal

M1L314Q = AMPP_FUNCTION(M1_LW_LXFR_lc[2], M1_LW_LXFR_lc[1], pci_rstn, GLOBAL(pci_clk), M1L104);


--M1_TS_DISC is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|TS_DISC
--operation mode is normal

M1_TS_DISC = AMPP_FUNCTION(M1_TS_DISC, M1_TS_DISC_d_lc2, A1L0321, M1L43, pci_rstn, GLOBAL(pci_clk));

--M1L025Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|TS_DISC~38
--operation mode is normal

M1L025Q = AMPP_FUNCTION(M1_TS_DISC, M1_TS_DISC_d_lc2, A1L0321, M1L43, pci_rstn, GLOBAL(pci_clk));


--M1L85 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|_~55
--operation mode is normal

M1L85 = AMPP_FUNCTION(M1_LW_LXFR, M1_TS_DISC, M1_TS_TURN_AR, M1_trdy_OR_NOT);

--M1L69 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|_~1505
--operation mode is normal

M1L69 = AMPP_FUNCTION(M1_LW_LXFR, M1_TS_DISC, M1_TS_TURN_AR, M1_trdy_OR_NOT);


--dpm_ni2f_reg_sm_6 is dpm_ni2f_reg_sm_6
--operation mode is normal

dpm_ni2f_reg_sm_6_lut_out = dpm_ni2f_reg_sm_5;
dpm_ni2f_reg_sm_6 = DFFEA(dpm_ni2f_reg_sm_6_lut_out, lcst, !ix2254, , , , );

--A1L334Q is dpm_ni2f_reg_sm_6~1
--operation mode is normal

A1L334Q = dpm_ni2f_reg_sm_6;


--G1_trg_ad_sel is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_ad_sel
--operation mode is normal

G1_trg_ad_sel = AMPP_FUNCTION(M1_TS_IDLE_NOT, N3_REG);

--G1L845 is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_ad_sel~7
--operation mode is normal

G1L845 = AMPP_FUNCTION(M1_TS_IDLE_NOT, N3_REG);


--J1_DXFR_write is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|DXFR_write
--operation mode is normal

J1_DXFR_write = AMPP_FUNCTION(J1_DXFR_write_lc3, J1_DXFR_write_lc4, pci_rstn, GLOBAL(pci_clk), J1L661);

--J1L081Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|DXFR_write~8
--operation mode is normal

J1L081Q = AMPP_FUNCTION(J1_DXFR_write_lc3, J1_DXFR_write_lc4, pci_rstn, GLOBAL(pci_clk), J1L661);


--G1_mstr_ad_sel is pci_contr:pci|pci_mt32:pci_mt32_inst|mstr_ad_sel
--operation mode is normal

G1_mstr_ad_sel = AMPP_FUNCTION(J1_MS_ENA, J1_MS_ADR, J1_MS_ADR2, J1_DXFR_write);

--G1L915 is pci_contr:pci|pci_mt32:pci_mt32_inst|mstr_ad_sel~14
--operation mode is normal

G1L915 = AMPP_FUNCTION(J1_MS_ENA, J1_MS_ADR, J1_MS_ADR2, J1_DXFR_write);


--G1_trg_cfg_cyc_out is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_cyc_out
--operation mode is normal

G1_trg_cfg_cyc_out = AMPP_FUNCTION(M1_cfg_cyc, G1_cben_ir_address[0]);

--G1L356 is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_cyc_out~0
--operation mode is normal

G1L356 = AMPP_FUNCTION(M1_cfg_cyc, G1_cben_ir_address[0]);


--M1_WAIT_wait32 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|WAIT_wait32
--operation mode is normal

M1_WAIT_wait32 = AMPP_FUNCTION(M1_no_op_reg[11], A1L0321, pci_rstn, GLOBAL(pci_clk), M1L9);

--M1L955Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|WAIT_wait32~17
--operation mode is normal

M1L955Q = AMPP_FUNCTION(M1_no_op_reg[11], A1L0321, pci_rstn, GLOBAL(pci_clk), M1L9);


--J1_WAIT_WAIT32 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|WAIT_WAIT32
--operation mode is normal

J1_WAIT_WAIT32 = AMPP_FUNCTION(J1_no_op_reg[3], pci_rstn, GLOBAL(pci_clk), J1L9);

--J1L406Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|WAIT_WAIT32~17
--operation mode is normal

J1L406Q = AMPP_FUNCTION(J1_no_op_reg[3], pci_rstn, GLOBAL(pci_clk), J1L9);


--G1_mstr_trg_hr_dat_sel is pci_contr:pci|pci_mt32:pci_mt32_inst|mstr_trg_hr_dat_sel
--operation mode is normal

G1_mstr_trg_hr_dat_sel = AMPP_FUNCTION(J1_dac_cyc_strobe, M1_WAIT_wait32, J1_WAIT_WAIT32, J1_MW_LAST);

--G1L335 is pci_contr:pci|pci_mt32:pci_mt32_inst|mstr_trg_hr_dat_sel~19
--operation mode is normal

G1L335 = AMPP_FUNCTION(J1_dac_cyc_strobe, M1_WAIT_wait32, J1_WAIT_WAIT32, J1_MW_LAST);


--dpm_ni2f_reg_sram_qL_0 is dpm_ni2f_reg_sram_qL_0
--operation mode is normal

dpm_ni2f_reg_sram_qL_0_lut_out = dpm_ni2f_reg_sm_8 & (SRAM_IO_0) # !dpm_ni2f_reg_sm_8 & dpm_ni2f_reg_sram_qL_0;
dpm_ni2f_reg_sram_qL_0 = DFFEA(dpm_ni2f_reg_sram_qL_0_lut_out, lcst, , , , , );

--A1L774Q is dpm_ni2f_reg_sram_qL_0~0
--operation mode is normal

A1L774Q = dpm_ni2f_reg_sram_qL_0;


--dpm_dec_reg_rdata_CNF_0 is dpm_dec_reg_rdata_CNF_0
--operation mode is normal

dpm_dec_reg_rdata_CNF_0_lut_out = A1L078 & G1_low_ad_IR_data[0] # !A1L078 & (dpm_dec_reg_rdata_CNF_0);
dpm_dec_reg_rdata_CNF_0 = DFFEA(dpm_dec_reg_rdata_CNF_0_lut_out, GLOBAL(pci_clk), pci_rstn, , , , );

--A1L52Q is dpm_dec_reg_rdata_CNF_0~0
--operation mode is normal

A1L52Q = dpm_dec_reg_rdata_CNF_0;


--A1L575 is ix2244~0
--operation mode is normal

A1L575 = (dpm_ni2f_reg_sram_qL_0 & !M1_lt_adr[19] & (!ix2312_lc # !dpm_dec_reg_rdata_CNF_0) # !dpm_ni2f_reg_sram_qL_0 & (!ix2312_lc # !dpm_dec_reg_rdata_CNF_0)) & CASCADE(A1L969);

--A1L675 is ix2244~1
--operation mode is normal

A1L675 = (dpm_ni2f_reg_sram_qL_0 & !M1_lt_adr[19] & (!ix2312_lc # !dpm_dec_reg_rdata_CNF_0) # !dpm_ni2f_reg_sram_qL_0 & (!ix2312_lc # !dpm_dec_reg_rdata_CNF_0)) & CASCADE(A1L969);


--G1_low_data_out_HR[0] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[0]
--operation mode is normal

G1_low_data_out_HR[0] = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L575, pci_rstn, GLOBAL(pci_clk));

--G1L434Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[0]~832
--operation mode is normal

G1L434Q = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L575, pci_rstn, GLOBAL(pci_clk));


--G1L23 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~193
--operation mode is normal

G1L23 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[0], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L33 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1633
--operation mode is normal

G1L33 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[0], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L43 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1634
--operation mode is normal

G1L43 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[0], G1_trg_ad_sel, G1_mstr_ad_sel);


--G1L053 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[0]~576
--operation mode is normal

G1L053 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[0], G1L43);

--G1L153 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[0]~608
--operation mode is normal

G1L153 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[0], G1L43);


--H1_ad_ce[0] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[0]
--operation mode is normal

H1_ad_ce[0] = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);

--H1L3 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[0]~64
--operation mode is normal

H1L3 = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);


--J1_ad_oer_lc2d is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|ad_oer_lc2d
--operation mode is normal

J1_ad_oer_lc2d = AMPP_FUNCTION(J1_dac_cyc_strobe, J1_ad_oer_lc2c, J1_ad_oer_lc2b);

--J1L611 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|ad_oer_lc2d~22
--operation mode is normal

J1L611 = AMPP_FUNCTION(J1_dac_cyc_strobe, J1_ad_oer_lc2c, J1_ad_oer_lc2b);


--J1_idle_reg is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|idle_reg
--operation mode is normal

J1_idle_reg = AMPP_FUNCTION(A1L0321, pci_rstn, GLOBAL(pci_clk), J1L812);

--J1L912Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|idle_reg~8
--operation mode is normal

J1L912Q = AMPP_FUNCTION(A1L0321, pci_rstn, GLOBAL(pci_clk), J1L812);


--J1_MS_REQ is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MS_REQ
--operation mode is normal

J1_MS_REQ = AMPP_FUNCTION(J1_MS_REQ_d_lc[1], pci_gntn, J1_MS_REQ_d_lc[2], pci_rstn, GLOBAL(pci_clk));

--J1L314Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MS_REQ~19
--operation mode is normal

J1L314Q = AMPP_FUNCTION(J1_MS_REQ_d_lc[1], pci_gntn, J1_MS_REQ_d_lc[2], pci_rstn, GLOBAL(pci_clk));


--J1_MS_IDLE_not is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MS_IDLE_not
--operation mode is normal

J1_MS_IDLE_not = AMPP_FUNCTION(J1_MS_IDLE_lc1, pci_gntn, J1_MS_PARK, J1_l_req_vld, pci_rstn, GLOBAL(pci_clk));

--J1L204Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MS_IDLE_not~46
--operation mode is normal

J1L204Q = AMPP_FUNCTION(J1_MS_IDLE_lc1, pci_gntn, J1_MS_PARK, J1_l_req_vld, pci_rstn, GLOBAL(pci_clk));


--J1_ad_oer_lc2a is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|ad_oer_lc2a
--operation mode is normal

J1_ad_oer_lc2a = AMPP_FUNCTION(J1_idle_reg, J1_MS_REQ, J1_MS_IDLE_not);

--J1L701 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|ad_oer_lc2a~20
--operation mode is normal

J1L701 = AMPP_FUNCTION(J1_idle_reg, J1_MS_REQ, J1_MS_IDLE_not);


--J1_mstr_abrt is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|mstr_abrt
--operation mode is normal

J1_mstr_abrt = AMPP_FUNCTION(J1_devsel_toR, pci_rstn, GLOBAL(pci_clk));

--J1L224Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|mstr_abrt~11
--operation mode is normal

J1L224Q = AMPP_FUNCTION(J1_devsel_toR, pci_rstn, GLOBAL(pci_clk));


--J1_ad_oer_lc3 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|ad_oer_lc3
--operation mode is normal

J1_ad_oer_lc3 = AMPP_FUNCTION(J1_MS_DXFR, J1_wr_rdn, J1_mstr_abrt);

--J1L911 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|ad_oer_lc3~23
--operation mode is normal

J1L911 = AMPP_FUNCTION(J1_MS_DXFR, J1_wr_rdn, J1_mstr_abrt);


--dpm_ni2f_reg_sram_qL_1 is dpm_ni2f_reg_sram_qL_1
--operation mode is normal

dpm_ni2f_reg_sram_qL_1_lut_out = dpm_ni2f_reg_sm_8 & (SRAM_IO_1) # !dpm_ni2f_reg_sm_8 & dpm_ni2f_reg_sram_qL_1;
dpm_ni2f_reg_sram_qL_1 = DFFEA(dpm_ni2f_reg_sram_qL_1_lut_out, lcst, , , , , );

--A1L974Q is dpm_ni2f_reg_sram_qL_1~0
--operation mode is normal

A1L974Q = dpm_ni2f_reg_sram_qL_1;


--dpm_dec_reg_rdata_CNF_1 is dpm_dec_reg_rdata_CNF_1
--operation mode is normal

dpm_dec_reg_rdata_CNF_1_lut_out = A1L078 & G1_low_ad_IR_data[1] # !A1L078 & (dpm_dec_reg_rdata_CNF_1);
dpm_dec_reg_rdata_CNF_1 = DFFEA(dpm_dec_reg_rdata_CNF_1_lut_out, GLOBAL(pci_clk), pci_rstn, , , , );

--A1L72Q is dpm_dec_reg_rdata_CNF_1~0
--operation mode is normal

A1L72Q = dpm_dec_reg_rdata_CNF_1;


--A1L375 is ix2243~0
--operation mode is normal

A1L375 = (dpm_ni2f_reg_sram_qL_1 & !M1_lt_adr[19] & (!ix2312_lc # !dpm_dec_reg_rdata_CNF_1) # !dpm_ni2f_reg_sram_qL_1 & (!ix2312_lc # !dpm_dec_reg_rdata_CNF_1)) & CASCADE(A1L579);

--A1L475 is ix2243~1
--operation mode is normal

A1L475 = (dpm_ni2f_reg_sram_qL_1 & !M1_lt_adr[19] & (!ix2312_lc # !dpm_dec_reg_rdata_CNF_1) # !dpm_ni2f_reg_sram_qL_1 & (!ix2312_lc # !dpm_dec_reg_rdata_CNF_1)) & CASCADE(A1L579);


--G1_low_data_out_HR[1] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[1]
--operation mode is normal

G1_low_data_out_HR[1] = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L375, pci_rstn, GLOBAL(pci_clk));

--G1L634Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[1]~833
--operation mode is normal

G1L634Q = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L375, pci_rstn, GLOBAL(pci_clk));


--G1L13 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~192
--operation mode is normal

G1L13 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[1], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L53 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1635
--operation mode is normal

G1L53 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[1], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L63 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1636
--operation mode is normal

G1L63 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[1], G1_trg_ad_sel, G1_mstr_ad_sel);


--G1L253 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[1]~577
--operation mode is normal

G1L253 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[1], G1L63);

--G1L353 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[1]~609
--operation mode is normal

G1L353 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[1], G1L63);


--dpm_ni2f_reg_sram_qL_2 is dpm_ni2f_reg_sram_qL_2
--operation mode is normal

dpm_ni2f_reg_sram_qL_2_lut_out = dpm_ni2f_reg_sm_8 & (SRAM_IO_2) # !dpm_ni2f_reg_sm_8 & dpm_ni2f_reg_sram_qL_2;
dpm_ni2f_reg_sram_qL_2 = DFFEA(dpm_ni2f_reg_sram_qL_2_lut_out, lcst, , , , , );

--A1L184Q is dpm_ni2f_reg_sram_qL_2~0
--operation mode is normal

A1L184Q = dpm_ni2f_reg_sram_qL_2;


--dpm_dec_reg_rdata_CNF_2 is dpm_dec_reg_rdata_CNF_2
--operation mode is normal

dpm_dec_reg_rdata_CNF_2_lut_out = A1L078 & G1_low_ad_IR_data[2] # !A1L078 & (dpm_dec_reg_rdata_CNF_2);
dpm_dec_reg_rdata_CNF_2 = DFFEA(dpm_dec_reg_rdata_CNF_2_lut_out, GLOBAL(pci_clk), pci_rstn, , , , );

--A1L92Q is dpm_dec_reg_rdata_CNF_2~0
--operation mode is normal

A1L92Q = dpm_dec_reg_rdata_CNF_2;


--A1L175 is ix2242~0
--operation mode is normal

A1L175 = (dpm_ni2f_reg_sram_qL_2 & !M1_lt_adr[19] & (!ix2312_lc # !dpm_dec_reg_rdata_CNF_2) # !dpm_ni2f_reg_sram_qL_2 & (!ix2312_lc # !dpm_dec_reg_rdata_CNF_2)) & CASCADE(A1L189);

--A1L275 is ix2242~1
--operation mode is normal

A1L275 = (dpm_ni2f_reg_sram_qL_2 & !M1_lt_adr[19] & (!ix2312_lc # !dpm_dec_reg_rdata_CNF_2) # !dpm_ni2f_reg_sram_qL_2 & (!ix2312_lc # !dpm_dec_reg_rdata_CNF_2)) & CASCADE(A1L189);


--G1_low_data_out_HR[2] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[2]
--operation mode is normal

G1_low_data_out_HR[2] = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L175, pci_rstn, GLOBAL(pci_clk));

--G1L834Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[2]~834
--operation mode is normal

G1L834Q = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L175, pci_rstn, GLOBAL(pci_clk));


--G1L03 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~191
--operation mode is normal

G1L03 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[2], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L73 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1637
--operation mode is normal

G1L73 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[2], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L83 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1638
--operation mode is normal

G1L83 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[2], G1_trg_ad_sel, G1_mstr_ad_sel);


--G1L453 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[2]~578
--operation mode is normal

G1L453 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[2], G1L83);

--G1L553 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[2]~610
--operation mode is normal

G1L553 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[2], G1L83);


--dpm_ni2f_reg_sram_qL_3 is dpm_ni2f_reg_sram_qL_3
--operation mode is normal

dpm_ni2f_reg_sram_qL_3_lut_out = dpm_ni2f_reg_sm_8 & (SRAM_IO_3) # !dpm_ni2f_reg_sm_8 & dpm_ni2f_reg_sram_qL_3;
dpm_ni2f_reg_sram_qL_3 = DFFEA(dpm_ni2f_reg_sram_qL_3_lut_out, lcst, , , , , );

--A1L384Q is dpm_ni2f_reg_sram_qL_3~0
--operation mode is normal

A1L384Q = dpm_ni2f_reg_sram_qL_3;


--dpm_dec_reg_rdata_CNF_3 is dpm_dec_reg_rdata_CNF_3
--operation mode is normal

dpm_dec_reg_rdata_CNF_3_lut_out = A1L078 & G1_low_ad_IR_data[3] # !A1L078 & (dpm_dec_reg_rdata_CNF_3);
dpm_dec_reg_rdata_CNF_3 = DFFEA(dpm_dec_reg_rdata_CNF_3_lut_out, GLOBAL(pci_clk), pci_rstn, , , , );

--A1L13Q is dpm_dec_reg_rdata_CNF_3~0
--operation mode is normal

A1L13Q = dpm_dec_reg_rdata_CNF_3;


--A1L965 is ix2241~0
--operation mode is normal

A1L965 = (dpm_ni2f_reg_sram_qL_3 & !M1_lt_adr[19] & (!ix2312_lc # !dpm_dec_reg_rdata_CNF_3) # !dpm_ni2f_reg_sram_qL_3 & (!ix2312_lc # !dpm_dec_reg_rdata_CNF_3)) & CASCADE(A1L789);

--A1L075 is ix2241~1
--operation mode is normal

A1L075 = (dpm_ni2f_reg_sram_qL_3 & !M1_lt_adr[19] & (!ix2312_lc # !dpm_dec_reg_rdata_CNF_3) # !dpm_ni2f_reg_sram_qL_3 & (!ix2312_lc # !dpm_dec_reg_rdata_CNF_3)) & CASCADE(A1L789);


--G1_low_data_out_HR[3] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[3]
--operation mode is normal

G1_low_data_out_HR[3] = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L965, pci_rstn, GLOBAL(pci_clk));

--G1L044Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[3]~835
--operation mode is normal

G1L044Q = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L965, pci_rstn, GLOBAL(pci_clk));


--G1L92 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~190
--operation mode is normal

G1L92 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[3], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L93 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1639
--operation mode is normal

G1L93 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[3], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L04 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1640
--operation mode is normal

G1L04 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[3], G1_trg_ad_sel, G1_mstr_ad_sel);


--G1L653 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[3]~579
--operation mode is normal

G1L653 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[3], G1L04);

--G1L753 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[3]~611
--operation mode is normal

G1L753 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[3], G1L04);


--dpm_ni2f_reg_sram_qL_4 is dpm_ni2f_reg_sram_qL_4
--operation mode is normal

dpm_ni2f_reg_sram_qL_4_lut_out = dpm_ni2f_reg_sm_8 & (SRAM_IO_4) # !dpm_ni2f_reg_sm_8 & dpm_ni2f_reg_sram_qL_4;
dpm_ni2f_reg_sram_qL_4 = DFFEA(dpm_ni2f_reg_sram_qL_4_lut_out, lcst, , , , , );

--A1L584Q is dpm_ni2f_reg_sram_qL_4~0
--operation mode is normal

A1L584Q = dpm_ni2f_reg_sram_qL_4;


--dpm_dec_reg_rdata_CNF_4 is dpm_dec_reg_rdata_CNF_4
--operation mode is normal

dpm_dec_reg_rdata_CNF_4_lut_out = A1L078 & G1_low_ad_IR_data[4] # !A1L078 & (dpm_dec_reg_rdata_CNF_4);
dpm_dec_reg_rdata_CNF_4 = DFFEA(dpm_dec_reg_rdata_CNF_4_lut_out, GLOBAL(pci_clk), pci_rstn, , , , );

--A1L33Q is dpm_dec_reg_rdata_CNF_4~0
--operation mode is normal

A1L33Q = dpm_dec_reg_rdata_CNF_4;


--A1L765 is ix2240~0
--operation mode is normal

A1L765 = (dpm_ni2f_reg_sram_qL_4 & !M1_lt_adr[19] & (!ix2312_lc # !dpm_dec_reg_rdata_CNF_4) # !dpm_ni2f_reg_sram_qL_4 & (!ix2312_lc # !dpm_dec_reg_rdata_CNF_4)) & CASCADE(A1L399);

--A1L865 is ix2240~1
--operation mode is normal

A1L865 = (dpm_ni2f_reg_sram_qL_4 & !M1_lt_adr[19] & (!ix2312_lc # !dpm_dec_reg_rdata_CNF_4) # !dpm_ni2f_reg_sram_qL_4 & (!ix2312_lc # !dpm_dec_reg_rdata_CNF_4)) & CASCADE(A1L399);


--G1_low_data_out_HR[4] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[4]
--operation mode is normal

G1_low_data_out_HR[4] = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L765, pci_rstn, GLOBAL(pci_clk));

--G1L244Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[4]~836
--operation mode is normal

G1L244Q = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L765, pci_rstn, GLOBAL(pci_clk));


--G1L82 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~189
--operation mode is normal

G1L82 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[4], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L14 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1641
--operation mode is normal

G1L14 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[4], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L24 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1642
--operation mode is normal

G1L24 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[4], G1_trg_ad_sel, G1_mstr_ad_sel);


--G1L853 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[4]~580
--operation mode is normal

G1L853 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[4], G1L24);

--G1L953 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[4]~612
--operation mode is normal

G1L953 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[4], G1L24);


--dpm_ni2f_reg_sram_qL_5 is dpm_ni2f_reg_sram_qL_5
--operation mode is normal

dpm_ni2f_reg_sram_qL_5_lut_out = dpm_ni2f_reg_sm_8 & (SRAM_IO_5) # !dpm_ni2f_reg_sm_8 & dpm_ni2f_reg_sram_qL_5;
dpm_ni2f_reg_sram_qL_5 = DFFEA(dpm_ni2f_reg_sram_qL_5_lut_out, lcst, , , , , );

--A1L784Q is dpm_ni2f_reg_sram_qL_5~0
--operation mode is normal

A1L784Q = dpm_ni2f_reg_sram_qL_5;


--dpm_dec_reg_rdata_CNF_5 is dpm_dec_reg_rdata_CNF_5
--operation mode is normal

dpm_dec_reg_rdata_CNF_5_lut_out = A1L078 & G1_low_ad_IR_data[5] # !A1L078 & (dpm_dec_reg_rdata_CNF_5);
dpm_dec_reg_rdata_CNF_5 = DFFEA(dpm_dec_reg_rdata_CNF_5_lut_out, GLOBAL(pci_clk), pci_rstn, , , , );

--A1L53Q is dpm_dec_reg_rdata_CNF_5~0
--operation mode is normal

A1L53Q = dpm_dec_reg_rdata_CNF_5;


--A1L565 is ix2239~0
--operation mode is normal

A1L565 = (dpm_ni2f_reg_sram_qL_5 & !M1_lt_adr[19] & (!ix2312_lc # !dpm_dec_reg_rdata_CNF_5) # !dpm_ni2f_reg_sram_qL_5 & (!ix2312_lc # !dpm_dec_reg_rdata_CNF_5)) & CASCADE(A1L999);

--A1L665 is ix2239~1
--operation mode is normal

A1L665 = (dpm_ni2f_reg_sram_qL_5 & !M1_lt_adr[19] & (!ix2312_lc # !dpm_dec_reg_rdata_CNF_5) # !dpm_ni2f_reg_sram_qL_5 & (!ix2312_lc # !dpm_dec_reg_rdata_CNF_5)) & CASCADE(A1L999);


--G1_low_data_out_HR[5] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[5]
--operation mode is normal

G1_low_data_out_HR[5] = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L565, pci_rstn, GLOBAL(pci_clk));

--G1L444Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[5]~837
--operation mode is normal

G1L444Q = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L565, pci_rstn, GLOBAL(pci_clk));


--G1L72 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~188
--operation mode is normal

G1L72 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[5], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L34 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1643
--operation mode is normal

G1L34 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[5], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L44 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1644
--operation mode is normal

G1L44 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[5], G1_trg_ad_sel, G1_mstr_ad_sel);


--G1L063 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[5]~581
--operation mode is normal

G1L063 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[5], G1L44);

--G1L163 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[5]~613
--operation mode is normal

G1L163 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[5], G1L44);


--dpm_ni2f_reg_sram_qL_6 is dpm_ni2f_reg_sram_qL_6
--operation mode is normal

dpm_ni2f_reg_sram_qL_6_lut_out = dpm_ni2f_reg_sm_8 & (SRAM_IO_6) # !dpm_ni2f_reg_sm_8 & dpm_ni2f_reg_sram_qL_6;
dpm_ni2f_reg_sram_qL_6 = DFFEA(dpm_ni2f_reg_sram_qL_6_lut_out, lcst, , , , , );

--A1L984Q is dpm_ni2f_reg_sram_qL_6~0
--operation mode is normal

A1L984Q = dpm_ni2f_reg_sram_qL_6;


--dpm_dec_reg_rdata_CNF_6 is dpm_dec_reg_rdata_CNF_6
--operation mode is normal

dpm_dec_reg_rdata_CNF_6_lut_out = A1L078 & G1_low_ad_IR_data[6] # !A1L078 & (dpm_dec_reg_rdata_CNF_6);
dpm_dec_reg_rdata_CNF_6 = DFFEA(dpm_dec_reg_rdata_CNF_6_lut_out, GLOBAL(pci_clk), pci_rstn, , , , );

--A1L73Q is dpm_dec_reg_rdata_CNF_6~0
--operation mode is normal

A1L73Q = dpm_dec_reg_rdata_CNF_6;


--A1L365 is ix2238~0
--operation mode is normal

A1L365 = (dpm_ni2f_reg_sram_qL_6 & !M1_lt_adr[19] & (!ix2312_lc # !dpm_dec_reg_rdata_CNF_6) # !dpm_ni2f_reg_sram_qL_6 & (!ix2312_lc # !dpm_dec_reg_rdata_CNF_6)) & CASCADE(A1L5001);

--A1L465 is ix2238~1
--operation mode is normal

A1L465 = (dpm_ni2f_reg_sram_qL_6 & !M1_lt_adr[19] & (!ix2312_lc # !dpm_dec_reg_rdata_CNF_6) # !dpm_ni2f_reg_sram_qL_6 & (!ix2312_lc # !dpm_dec_reg_rdata_CNF_6)) & CASCADE(A1L5001);


--G1_low_data_out_HR[6] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[6]
--operation mode is normal

G1_low_data_out_HR[6] = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L365, pci_rstn, GLOBAL(pci_clk));

--G1L644Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[6]~838
--operation mode is normal

G1L644Q = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L365, pci_rstn, GLOBAL(pci_clk));


--G1L62 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~187
--operation mode is normal

G1L62 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[6], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L54 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1645
--operation mode is normal

G1L54 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[6], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L64 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1646
--operation mode is normal

G1L64 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[6], G1_trg_ad_sel, G1_mstr_ad_sel);


--G1L263 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[6]~582
--operation mode is normal

G1L263 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[6], G1L64);

--G1L363 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[6]~614
--operation mode is normal

G1L363 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[6], G1L64);


--dpm_ni2f_reg_sram_qL_7 is dpm_ni2f_reg_sram_qL_7
--operation mode is normal

dpm_ni2f_reg_sram_qL_7_lut_out = dpm_ni2f_reg_sm_8 & (SRAM_IO_7) # !dpm_ni2f_reg_sm_8 & dpm_ni2f_reg_sram_qL_7;
dpm_ni2f_reg_sram_qL_7 = DFFEA(dpm_ni2f_reg_sram_qL_7_lut_out, lcst, , , , , );

--A1L194Q is dpm_ni2f_reg_sram_qL_7~0
--operation mode is normal

A1L194Q = dpm_ni2f_reg_sram_qL_7;


--dpm_dec_reg_rdata_CNF_7 is dpm_dec_reg_rdata_CNF_7
--operation mode is normal

dpm_dec_reg_rdata_CNF_7_lut_out = A1L078 & G1_low_ad_IR_data[7] # !A1L078 & (dpm_dec_reg_rdata_CNF_7);
dpm_dec_reg_rdata_CNF_7 = DFFEA(dpm_dec_reg_rdata_CNF_7_lut_out, GLOBAL(pci_clk), pci_rstn, , , , );

--A1L93Q is dpm_dec_reg_rdata_CNF_7~0
--operation mode is normal

A1L93Q = dpm_dec_reg_rdata_CNF_7;


--A1L165 is ix2237~0
--operation mode is normal

A1L165 = (dpm_ni2f_reg_sram_qL_7 & !M1_lt_adr[19] & (!ix2312_lc # !dpm_dec_reg_rdata_CNF_7) # !dpm_ni2f_reg_sram_qL_7 & (!ix2312_lc # !dpm_dec_reg_rdata_CNF_7)) & CASCADE(A1L1101);

--A1L265 is ix2237~1
--operation mode is normal

A1L265 = (dpm_ni2f_reg_sram_qL_7 & !M1_lt_adr[19] & (!ix2312_lc # !dpm_dec_reg_rdata_CNF_7) # !dpm_ni2f_reg_sram_qL_7 & (!ix2312_lc # !dpm_dec_reg_rdata_CNF_7)) & CASCADE(A1L1101);


--G1_low_data_out_HR[7] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[7]
--operation mode is normal

G1_low_data_out_HR[7] = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L165, pci_rstn, GLOBAL(pci_clk));

--G1L844Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[7]~839
--operation mode is normal

G1L844Q = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L165, pci_rstn, GLOBAL(pci_clk));


--G1L52 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~186
--operation mode is normal

G1L52 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[7], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L74 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1647
--operation mode is normal

G1L74 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[7], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L84 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1648
--operation mode is normal

G1L84 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[7], G1_trg_ad_sel, G1_mstr_ad_sel);


--G1L463 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[7]~583
--operation mode is normal

G1L463 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[7], G1L84);

--G1L563 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[7]~615
--operation mode is normal

G1L563 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[7], G1L84);


--E3_q[8] is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[8]
--operation mode is clrb_cntr

E3_q[8]_lut_out = (E3_q[8] $ (ix2252_lc & E3L71)) & VCC;
E3_q[8] = DFFEA(E3_q[8]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E3L38Q is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[8]~0
--operation mode is clrb_cntr

E3L38Q = E3_q[8];

--E3L91 is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[8]~COUT
--operation mode is clrb_cntr

E3L91 = CARRY(E3_q[8] & (E3L71));


--A1L955 is ix2236~0
--operation mode is normal

A1L955 = (E9_q[8] & !ix2322_lc & (!ix2321_lc # !E3_q[8]) # !E9_q[8] & (!ix2321_lc # !E3_q[8])) & CASCADE(A1L7101);

--A1L065 is ix2236~1
--operation mode is normal

A1L065 = (E9_q[8] & !ix2322_lc & (!ix2321_lc # !E3_q[8]) # !E9_q[8] & (!ix2321_lc # !E3_q[8])) & CASCADE(A1L7101);


--G1_low_data_out_HR[8] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[8]
--operation mode is normal

G1_low_data_out_HR[8] = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L955, pci_rstn, GLOBAL(pci_clk));

--G1L054Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[8]~840
--operation mode is normal

G1L054Q = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L955, pci_rstn, GLOBAL(pci_clk));


--G1L42 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~185
--operation mode is normal

G1L42 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[8], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L94 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1649
--operation mode is normal

G1L94 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[8], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L05 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1650
--operation mode is normal

G1L05 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[8], G1_trg_ad_sel, G1_mstr_ad_sel);


--G1L663 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[8]~584
--operation mode is normal

G1L663 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[8], G1L05);

--G1L763 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[8]~616
--operation mode is normal

G1L763 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[8], G1L05);


--E3_q[9] is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[9]
--operation mode is clrb_cntr

E3_q[9]_lut_out = (E3_q[9] $ (ix2252_lc & E3L91)) & VCC;
E3_q[9] = DFFEA(E3_q[9]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E3L58Q is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[9]~1
--operation mode is clrb_cntr

E3L58Q = E3_q[9];

--E3L12 is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[9]~COUT
--operation mode is clrb_cntr

E3L12 = CARRY(E3_q[9] & (E3L91));


--A1L755 is ix2235~0
--operation mode is normal

A1L755 = (E9_q[9] & !ix2322_lc & (!ix2321_lc # !E3_q[9]) # !E9_q[9] & (!ix2321_lc # !E3_q[9])) & CASCADE(A1L3201);

--A1L855 is ix2235~1
--operation mode is normal

A1L855 = (E9_q[9] & !ix2322_lc & (!ix2321_lc # !E3_q[9]) # !E9_q[9] & (!ix2321_lc # !E3_q[9])) & CASCADE(A1L3201);


--G1_low_data_out_HR[9] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[9]
--operation mode is normal

G1_low_data_out_HR[9] = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L755, pci_rstn, GLOBAL(pci_clk));

--G1L254Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[9]~841
--operation mode is normal

G1L254Q = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L755, pci_rstn, GLOBAL(pci_clk));


--G1L32 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~184
--operation mode is normal

G1L32 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[9], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L15 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1651
--operation mode is normal

G1L15 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[9], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L25 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1652
--operation mode is normal

G1L25 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[9], G1_trg_ad_sel, G1_mstr_ad_sel);


--G1L863 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[9]~585
--operation mode is normal

G1L863 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[9], G1L25);

--G1L963 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[9]~617
--operation mode is normal

G1L963 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[9], G1L25);


--E3_q[10] is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[10]
--operation mode is clrb_cntr

E3_q[10]_lut_out = (E3_q[10] $ (ix2252_lc & E3L12)) & VCC;
E3_q[10] = DFFEA(E3_q[10]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E3L78Q is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[10]~2
--operation mode is clrb_cntr

E3L78Q = E3_q[10];

--E3L32 is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[10]~COUT
--operation mode is clrb_cntr

E3L32 = CARRY(E3_q[10] & (E3L12));


--A1L555 is ix2234~0
--operation mode is normal

A1L555 = (E9_q[10] & !ix2322_lc & (!ix2321_lc # !E3_q[10]) # !E9_q[10] & (!ix2321_lc # !E3_q[10])) & CASCADE(A1L048);

--A1L655 is ix2234~1
--operation mode is normal

A1L655 = (E9_q[10] & !ix2322_lc & (!ix2321_lc # !E3_q[10]) # !E9_q[10] & (!ix2321_lc # !E3_q[10])) & CASCADE(A1L048);


--G1_low_data_out_HR[10] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[10]
--operation mode is normal

G1_low_data_out_HR[10] = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L555, pci_rstn, GLOBAL(pci_clk));

--G1L454Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[10]~842
--operation mode is normal

G1L454Q = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L555, pci_rstn, GLOBAL(pci_clk));


--G1L22 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~183
--operation mode is normal

G1L22 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[10], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L35 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1653
--operation mode is normal

G1L35 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[10], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L45 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1654
--operation mode is normal

G1L45 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[10], G1_trg_ad_sel, G1_mstr_ad_sel);


--G1L073 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[10]~586
--operation mode is normal

G1L073 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[10], G1L45);

--G1L173 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[10]~618
--operation mode is normal

G1L173 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[10], G1L45);


--E3_q[11] is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[11]
--operation mode is clrb_cntr

E3_q[11]_lut_out = (E3_q[11] $ (ix2252_lc & E3L32)) & VCC;
E3_q[11] = DFFEA(E3_q[11]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E3L98Q is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[11]~3
--operation mode is clrb_cntr

E3L98Q = E3_q[11];

--E3L52 is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[11]~COUT
--operation mode is clrb_cntr

E3L52 = CARRY(E3_q[11] & (E3L32));


--A1L355 is ix2233~0
--operation mode is normal

A1L355 = (E9_q[11] & !ix2322_lc & (!ix2321_lc # !E3_q[11]) # !E9_q[11] & (!ix2321_lc # !E3_q[11])) & CASCADE(A1L738);

--A1L455 is ix2233~1
--operation mode is normal

A1L455 = (E9_q[11] & !ix2322_lc & (!ix2321_lc # !E3_q[11]) # !E9_q[11] & (!ix2321_lc # !E3_q[11])) & CASCADE(A1L738);


--G1_low_data_out_HR[11] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[11]
--operation mode is normal

G1_low_data_out_HR[11] = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L355, pci_rstn, GLOBAL(pci_clk));

--G1L654Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[11]~843
--operation mode is normal

G1L654Q = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L355, pci_rstn, GLOBAL(pci_clk));


--G1L12 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~182
--operation mode is normal

G1L12 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[11], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L55 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1655
--operation mode is normal

G1L55 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[11], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L65 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1656
--operation mode is normal

G1L65 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[11], G1_trg_ad_sel, G1_mstr_ad_sel);


--G1L273 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[11]~587
--operation mode is normal

G1L273 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[11], G1L65);

--G1L373 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[11]~619
--operation mode is normal

G1L373 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[11], G1L65);


--E3_q[12] is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[12]
--operation mode is clrb_cntr

E3_q[12]_lut_out = (E3_q[12] $ (ix2252_lc & E3L52)) & VCC;
E3_q[12] = DFFEA(E3_q[12]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E3L19Q is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[12]~4
--operation mode is clrb_cntr

E3L19Q = E3_q[12];

--E3L72 is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[12]~COUT
--operation mode is clrb_cntr

E3L72 = CARRY(E3_q[12] & (E3L52));


--A1L155 is ix2232~0
--operation mode is normal

A1L155 = (E9_q[12] & !ix2322_lc & (!ix2321_lc # !E3_q[12]) # !E9_q[12] & (!ix2321_lc # !E3_q[12])) & CASCADE(A1L438);

--A1L255 is ix2232~1
--operation mode is normal

A1L255 = (E9_q[12] & !ix2322_lc & (!ix2321_lc # !E3_q[12]) # !E9_q[12] & (!ix2321_lc # !E3_q[12])) & CASCADE(A1L438);


--G1_low_data_out_HR[12] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[12]
--operation mode is normal

G1_low_data_out_HR[12] = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L155, pci_rstn, GLOBAL(pci_clk));

--G1L854Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[12]~844
--operation mode is normal

G1L854Q = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L155, pci_rstn, GLOBAL(pci_clk));


--G1L02 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~181
--operation mode is normal

G1L02 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[12], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L75 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1657
--operation mode is normal

G1L75 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[12], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L85 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1658
--operation mode is normal

G1L85 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[12], G1_trg_ad_sel, G1_mstr_ad_sel);


--G1L473 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[12]~588
--operation mode is normal

G1L473 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[12], G1L85);

--G1L573 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[12]~620
--operation mode is normal

G1L573 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[12], G1L85);


--E3_q[13] is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[13]
--operation mode is clrb_cntr

E3_q[13]_lut_out = (E3_q[13] $ (ix2252_lc & E3L72)) & VCC;
E3_q[13] = DFFEA(E3_q[13]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E3L39Q is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[13]~5
--operation mode is clrb_cntr

E3L39Q = E3_q[13];

--E3L92 is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[13]~COUT
--operation mode is clrb_cntr

E3L92 = CARRY(E3_q[13] & (E3L72));


--A1L945 is ix2231~0
--operation mode is normal

A1L945 = (E9_q[13] & !ix2322_lc & (!ix2321_lc # !E3_q[13]) # !E9_q[13] & (!ix2321_lc # !E3_q[13])) & CASCADE(A1L138);

--A1L055 is ix2231~1
--operation mode is normal

A1L055 = (E9_q[13] & !ix2322_lc & (!ix2321_lc # !E3_q[13]) # !E9_q[13] & (!ix2321_lc # !E3_q[13])) & CASCADE(A1L138);


--G1_low_data_out_HR[13] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[13]
--operation mode is normal

G1_low_data_out_HR[13] = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L945, pci_rstn, GLOBAL(pci_clk));

--G1L064Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[13]~845
--operation mode is normal

G1L064Q = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L945, pci_rstn, GLOBAL(pci_clk));


--G1L91 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~180
--operation mode is normal

G1L91 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[13], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L95 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1659
--operation mode is normal

G1L95 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[13], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L06 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1660
--operation mode is normal

G1L06 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[13], G1_trg_ad_sel, G1_mstr_ad_sel);


--G1L673 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[13]~589
--operation mode is normal

G1L673 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[13], G1L06);

--G1L773 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[13]~621
--operation mode is normal

G1L773 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[13], G1L06);


--E3_q[14] is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[14]
--operation mode is clrb_cntr

E3_q[14]_lut_out = (E3_q[14] $ (ix2252_lc & E3L92)) & VCC;
E3_q[14] = DFFEA(E3_q[14]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E3L59Q is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[14]~6
--operation mode is clrb_cntr

E3L59Q = E3_q[14];

--E3L13 is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[14]~COUT
--operation mode is clrb_cntr

E3L13 = CARRY(E3_q[14] & (E3L92));


--A1L745 is ix2230~0
--operation mode is normal

A1L745 = (E9_q[14] & !ix2322_lc & (!ix2321_lc # !E3_q[14]) # !E9_q[14] & (!ix2321_lc # !E3_q[14])) & CASCADE(A1L828);

--A1L845 is ix2230~1
--operation mode is normal

A1L845 = (E9_q[14] & !ix2322_lc & (!ix2321_lc # !E3_q[14]) # !E9_q[14] & (!ix2321_lc # !E3_q[14])) & CASCADE(A1L828);


--G1_low_data_out_HR[14] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[14]
--operation mode is normal

G1_low_data_out_HR[14] = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L745, pci_rstn, GLOBAL(pci_clk));

--G1L264Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[14]~846
--operation mode is normal

G1L264Q = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L745, pci_rstn, GLOBAL(pci_clk));


--G1L81 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~179
--operation mode is normal

G1L81 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[14], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L16 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1661
--operation mode is normal

G1L16 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[14], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L26 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1662
--operation mode is normal

G1L26 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[14], G1_trg_ad_sel, G1_mstr_ad_sel);


--G1L873 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[14]~590
--operation mode is normal

G1L873 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[14], G1L26);

--G1L973 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[14]~622
--operation mode is normal

G1L973 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[14], G1L26);


--E3_q[15] is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[15]
--operation mode is clrb_cntr

E3_q[15]_lut_out = (E3_q[15] $ (ix2252_lc & E3L13)) & VCC;
E3_q[15] = DFFEA(E3_q[15]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E3L79Q is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[15]~7
--operation mode is clrb_cntr

E3L79Q = E3_q[15];

--E3L33 is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[15]~COUT
--operation mode is clrb_cntr

E3L33 = CARRY(E3_q[15] & (E3L13));


--A1L545 is ix2229~0
--operation mode is normal

A1L545 = (E9_q[15] & !ix2322_lc & (!ix2321_lc # !E3_q[15]) # !E9_q[15] & (!ix2321_lc # !E3_q[15])) & CASCADE(A1L528);

--A1L645 is ix2229~1
--operation mode is normal

A1L645 = (E9_q[15] & !ix2322_lc & (!ix2321_lc # !E3_q[15]) # !E9_q[15] & (!ix2321_lc # !E3_q[15])) & CASCADE(A1L528);


--G1_low_data_out_HR[15] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[15]
--operation mode is normal

G1_low_data_out_HR[15] = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L545, pci_rstn, GLOBAL(pci_clk));

--G1L464Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[15]~847
--operation mode is normal

G1L464Q = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L545, pci_rstn, GLOBAL(pci_clk));


--G1L71 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~178
--operation mode is normal

G1L71 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[15], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L36 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1663
--operation mode is normal

G1L36 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[15], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L46 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1664
--operation mode is normal

G1L46 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[15], G1_trg_ad_sel, G1_mstr_ad_sel);


--G1L083 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[15]~591
--operation mode is normal

G1L083 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[15], G1L46);

--G1L183 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[15]~623
--operation mode is normal

G1L183 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[15], G1L46);


--E3_q[16] is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[16]
--operation mode is clrb_cntr

E3_q[16]_lut_out = (E3_q[16] $ (ix2252_lc & E3L33)) & VCC;
E3_q[16] = DFFEA(E3_q[16]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E3L99Q is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[16]~8
--operation mode is clrb_cntr

E3L99Q = E3_q[16];

--E3L53 is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[16]~COUT
--operation mode is clrb_cntr

E3L53 = CARRY(E3_q[16] & (E3L33));


--A1L345 is ix2228~0
--operation mode is normal

A1L345 = (E9_q[16] & !ix2322_lc & (!ix2321_lc # !E3_q[16]) # !E9_q[16] & (!ix2321_lc # !E3_q[16])) & CASCADE(A1L228);

--A1L445 is ix2228~1
--operation mode is normal

A1L445 = (E9_q[16] & !ix2322_lc & (!ix2321_lc # !E3_q[16]) # !E9_q[16] & (!ix2321_lc # !E3_q[16])) & CASCADE(A1L228);


--G1_low_data_out_HR[16] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[16]
--operation mode is normal

G1_low_data_out_HR[16] = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L345, pci_rstn, GLOBAL(pci_clk));

--G1L664Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[16]~848
--operation mode is normal

G1L664Q = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L345, pci_rstn, GLOBAL(pci_clk));


--G1L61 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~177
--operation mode is normal

G1L61 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[16], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L56 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1665
--operation mode is normal

G1L56 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[16], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L66 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1666
--operation mode is normal

G1L66 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[16], G1_trg_ad_sel, G1_mstr_ad_sel);


--G1L283 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[16]~592
--operation mode is normal

G1L283 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[16], G1L66);

--G1L383 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[16]~624
--operation mode is normal

G1L383 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[16], G1L66);


--E3_q[17] is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[17]
--operation mode is clrb_cntr

E3_q[17]_lut_out = (E3_q[17] $ (ix2252_lc & E3L53)) & VCC;
E3_q[17] = DFFEA(E3_q[17]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E3L101Q is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[17]~9
--operation mode is clrb_cntr

E3L101Q = E3_q[17];

--E3L73 is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[17]~COUT
--operation mode is clrb_cntr

E3L73 = CARRY(E3_q[17] & (E3L53));


--A1L145 is ix2227~0
--operation mode is normal

A1L145 = (E9_q[17] & !ix2322_lc & (!ix2321_lc # !E3_q[17]) # !E9_q[17] & (!ix2321_lc # !E3_q[17])) & CASCADE(A1L918);

--A1L245 is ix2227~1
--operation mode is normal

A1L245 = (E9_q[17] & !ix2322_lc & (!ix2321_lc # !E3_q[17]) # !E9_q[17] & (!ix2321_lc # !E3_q[17])) & CASCADE(A1L918);


--G1_low_data_out_HR[17] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[17]
--operation mode is normal

G1_low_data_out_HR[17] = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L145, pci_rstn, GLOBAL(pci_clk));

--G1L864Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[17]~849
--operation mode is normal

G1L864Q = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L145, pci_rstn, GLOBAL(pci_clk));


--G1L51 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~176
--operation mode is normal

G1L51 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[17], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L76 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1667
--operation mode is normal

G1L76 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[17], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L86 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1668
--operation mode is normal

G1L86 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[17], G1_trg_ad_sel, G1_mstr_ad_sel);


--G1L483 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[17]~593
--operation mode is normal

G1L483 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[17], G1L86);

--G1L583 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[17]~625
--operation mode is normal

G1L583 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[17], G1L86);


--E8_q[0] is lpm_counter:dpm_ni2f_rcounter_ix7|alt_counter_f10ke:wysi_counter|q[0]
--operation mode is clrb_cntr

E8_q[0]_lut_out = (dpm_ni2f_reg_sm_10 $ E8_q[0]) & A1L905;
E8_q[0] = DFFEA(E8_q[0]_lut_out, lcst, , , , , );

--E8L51Q is lpm_counter:dpm_ni2f_rcounter_ix7|alt_counter_f10ke:wysi_counter|q[0]~0
--operation mode is clrb_cntr

E8L51Q = E8_q[0];

--E8L3 is lpm_counter:dpm_ni2f_rcounter_ix7|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT
--operation mode is clrb_cntr

E8L3 = CARRY(E8_q[0]);


--E3_q[18] is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[18]
--operation mode is clrb_cntr

E3_q[18]_lut_out = (E3_q[18] $ (ix2252_lc & E3L73)) & VCC;
E3_q[18] = DFFEA(E3_q[18]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E3L301Q is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[18]~10
--operation mode is clrb_cntr

E3L301Q = E3_q[18];

--E3L93 is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[18]~COUT
--operation mode is clrb_cntr

E3L93 = CARRY(E3_q[18] & (E3L73));


--A1L935 is ix2226~0
--operation mode is normal

A1L935 = (E8_q[0] & !ix2322_lc & (!ix2321_lc # !E3_q[18]) # !E8_q[0] & (!ix2321_lc # !E3_q[18])) & CASCADE(A1L618);

--A1L045 is ix2226~1
--operation mode is normal

A1L045 = (E8_q[0] & !ix2322_lc & (!ix2321_lc # !E3_q[18]) # !E8_q[0] & (!ix2321_lc # !E3_q[18])) & CASCADE(A1L618);


--G1_low_data_out_HR[18] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[18]
--operation mode is normal

G1_low_data_out_HR[18] = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L935, pci_rstn, GLOBAL(pci_clk));

--G1L074Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[18]~850
--operation mode is normal

G1L074Q = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L935, pci_rstn, GLOBAL(pci_clk));


--G1L41 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~175
--operation mode is normal

G1L41 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[18], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L96 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1669
--operation mode is normal

G1L96 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[18], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L07 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1670
--operation mode is normal

G1L07 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[18], G1_trg_ad_sel, G1_mstr_ad_sel);


--G1L683 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[18]~594
--operation mode is normal

G1L683 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[18], G1L07);

--G1L783 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[18]~626
--operation mode is normal

G1L783 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[18], G1L07);


--E8_q[1] is lpm_counter:dpm_ni2f_rcounter_ix7|alt_counter_f10ke:wysi_counter|q[1]
--operation mode is clrb_cntr

E8_q[1]_lut_out = (E8_q[1] $ (dpm_ni2f_reg_sm_10 & E8L3)) & A1L905;
E8_q[1] = DFFEA(E8_q[1]_lut_out, lcst, , , , , );

--E8L71Q is lpm_counter:dpm_ni2f_rcounter_ix7|alt_counter_f10ke:wysi_counter|q[1]~1
--operation mode is clrb_cntr

E8L71Q = E8_q[1];

--E8L5 is lpm_counter:dpm_ni2f_rcounter_ix7|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT
--operation mode is clrb_cntr

E8L5 = CARRY(E8_q[1] & (E8L3));


--E3_q[19] is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[19]
--operation mode is clrb_cntr

E3_q[19]_lut_out = (E3_q[19] $ (ix2252_lc & E3L93)) & VCC;
E3_q[19] = DFFEA(E3_q[19]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E3L501Q is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[19]~11
--operation mode is clrb_cntr

E3L501Q = E3_q[19];

--E3L14 is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[19]~COUT
--operation mode is clrb_cntr

E3L14 = CARRY(E3_q[19] & (E3L93));


--A1L735 is ix2225~0
--operation mode is normal

A1L735 = (E8_q[1] & !ix2322_lc & (!ix2321_lc # !E3_q[19]) # !E8_q[1] & (!ix2321_lc # !E3_q[19])) & CASCADE(A1L318);

--A1L835 is ix2225~1
--operation mode is normal

A1L835 = (E8_q[1] & !ix2322_lc & (!ix2321_lc # !E3_q[19]) # !E8_q[1] & (!ix2321_lc # !E3_q[19])) & CASCADE(A1L318);


--G1_low_data_out_HR[19] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[19]
--operation mode is normal

G1_low_data_out_HR[19] = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L735, pci_rstn, GLOBAL(pci_clk));

--G1L274Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[19]~851
--operation mode is normal

G1L274Q = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L735, pci_rstn, GLOBAL(pci_clk));


--G1L31 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~174
--operation mode is normal

G1L31 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[19], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L17 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1671
--operation mode is normal

G1L17 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[19], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L27 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1672
--operation mode is normal

G1L27 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[19], G1_trg_ad_sel, G1_mstr_ad_sel);


--G1L883 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[19]~595
--operation mode is normal

G1L883 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[19], G1L27);

--G1L983 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[19]~627
--operation mode is normal

G1L983 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[19], G1L27);


--E8_q[2] is lpm_counter:dpm_ni2f_rcounter_ix7|alt_counter_f10ke:wysi_counter|q[2]
--operation mode is clrb_cntr

E8_q[2]_lut_out = (E8_q[2] $ (dpm_ni2f_reg_sm_10 & E8L5)) & A1L905;
E8_q[2] = DFFEA(E8_q[2]_lut_out, lcst, , , , , );

--E8L91Q is lpm_counter:dpm_ni2f_rcounter_ix7|alt_counter_f10ke:wysi_counter|q[2]~2
--operation mode is clrb_cntr

E8L91Q = E8_q[2];

--E8L7 is lpm_counter:dpm_ni2f_rcounter_ix7|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT
--operation mode is clrb_cntr

E8L7 = CARRY(E8_q[2] & (E8L5));


--E3_q[20] is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[20]
--operation mode is clrb_cntr

E3_q[20]_lut_out = (E3_q[20] $ (ix2252_lc & E3L14)) & VCC;
E3_q[20] = DFFEA(E3_q[20]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E3L701Q is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[20]~12
--operation mode is clrb_cntr

E3L701Q = E3_q[20];

--E3L34 is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[20]~COUT
--operation mode is clrb_cntr

E3L34 = CARRY(E3_q[20] & (E3L14));


--A1L535 is ix2224~0
--operation mode is normal

A1L535 = (E8_q[2] & !ix2322_lc & (!ix2321_lc # !E3_q[20]) # !E8_q[2] & (!ix2321_lc # !E3_q[20])) & CASCADE(A1L018);

--A1L635 is ix2224~1
--operation mode is normal

A1L635 = (E8_q[2] & !ix2322_lc & (!ix2321_lc # !E3_q[20]) # !E8_q[2] & (!ix2321_lc # !E3_q[20])) & CASCADE(A1L018);


--G1_low_data_out_HR[20] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[20]
--operation mode is normal

G1_low_data_out_HR[20] = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L535, pci_rstn, GLOBAL(pci_clk));

--G1L474Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[20]~852
--operation mode is normal

G1L474Q = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L535, pci_rstn, GLOBAL(pci_clk));


--G1L21 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~173
--operation mode is normal

G1L21 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[20], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L37 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1673
--operation mode is normal

G1L37 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[20], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L47 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1674
--operation mode is normal

G1L47 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[20], G1_trg_ad_sel, G1_mstr_ad_sel);


--G1L093 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[20]~596
--operation mode is normal

G1L093 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[20], G1L47);

--G1L193 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[20]~628
--operation mode is normal

G1L193 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[20], G1L47);


--E8_q[3] is lpm_counter:dpm_ni2f_rcounter_ix7|alt_counter_f10ke:wysi_counter|q[3]
--operation mode is clrb_cntr

E8_q[3]_lut_out = (E8_q[3] $ (dpm_ni2f_reg_sm_10 & E8L7)) & A1L905;
E8_q[3] = DFFEA(E8_q[3]_lut_out, lcst, , , , , );

--E8L12Q is lpm_counter:dpm_ni2f_rcounter_ix7|alt_counter_f10ke:wysi_counter|q[3]~3
--operation mode is clrb_cntr

E8L12Q = E8_q[3];

--E8L9 is lpm_counter:dpm_ni2f_rcounter_ix7|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT
--operation mode is clrb_cntr

E8L9 = CARRY(E8_q[3] & (E8L7));


--E3_q[21] is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[21]
--operation mode is clrb_cntr

E3_q[21]_lut_out = (E3_q[21] $ (ix2252_lc & E3L34)) & VCC;
E3_q[21] = DFFEA(E3_q[21]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E3L901Q is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[21]~13
--operation mode is clrb_cntr

E3L901Q = E3_q[21];

--E3L54 is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[21]~COUT
--operation mode is clrb_cntr

E3L54 = CARRY(E3_q[21] & (E3L34));


--A1L335 is ix2223~0
--operation mode is normal

A1L335 = (E8_q[3] & !ix2322_lc & (!ix2321_lc # !E3_q[21]) # !E8_q[3] & (!ix2321_lc # !E3_q[21])) & CASCADE(A1L708);

--A1L435 is ix2223~1
--operation mode is normal

A1L435 = (E8_q[3] & !ix2322_lc & (!ix2321_lc # !E3_q[21]) # !E8_q[3] & (!ix2321_lc # !E3_q[21])) & CASCADE(A1L708);


--G1_low_data_out_HR[21] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[21]
--operation mode is normal

G1_low_data_out_HR[21] = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L335, pci_rstn, GLOBAL(pci_clk));

--G1L674Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[21]~853
--operation mode is normal

G1L674Q = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L335, pci_rstn, GLOBAL(pci_clk));


--G1L11 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~172
--operation mode is normal

G1L11 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[21], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L57 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1675
--operation mode is normal

G1L57 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[21], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L67 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1676
--operation mode is normal

G1L67 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[21], G1_trg_ad_sel, G1_mstr_ad_sel);


--G1L293 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[21]~597
--operation mode is normal

G1L293 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[21], G1L67);

--G1L393 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[21]~629
--operation mode is normal

G1L393 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[21], G1L67);


--E8_q[4] is lpm_counter:dpm_ni2f_rcounter_ix7|alt_counter_f10ke:wysi_counter|q[4]
--operation mode is clrb_cntr

E8_q[4]_lut_out = (E8_q[4] $ (dpm_ni2f_reg_sm_10 & E8L9)) & A1L905;
E8_q[4] = DFFEA(E8_q[4]_lut_out, lcst, , , , , );

--E8L32Q is lpm_counter:dpm_ni2f_rcounter_ix7|alt_counter_f10ke:wysi_counter|q[4]~4
--operation mode is clrb_cntr

E8L32Q = E8_q[4];

--E8L11 is lpm_counter:dpm_ni2f_rcounter_ix7|alt_counter_f10ke:wysi_counter|counter_cell[4]~COUT
--operation mode is clrb_cntr

E8L11 = CARRY(E8_q[4] & (E8L9));


--E3_q[22] is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[22]
--operation mode is clrb_cntr

E3_q[22]_lut_out = (E3_q[22] $ (ix2252_lc & E3L54)) & VCC;
E3_q[22] = DFFEA(E3_q[22]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E3L111Q is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[22]~14
--operation mode is clrb_cntr

E3L111Q = E3_q[22];

--E3L74 is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[22]~COUT
--operation mode is clrb_cntr

E3L74 = CARRY(E3_q[22] & (E3L54));


--A1L135 is ix2222~0
--operation mode is normal

A1L135 = (E8_q[4] & !ix2322_lc & (!ix2321_lc # !E3_q[22]) # !E8_q[4] & (!ix2321_lc # !E3_q[22])) & CASCADE(A1L408);

--A1L235 is ix2222~1
--operation mode is normal

A1L235 = (E8_q[4] & !ix2322_lc & (!ix2321_lc # !E3_q[22]) # !E8_q[4] & (!ix2321_lc # !E3_q[22])) & CASCADE(A1L408);


--G1_low_data_out_HR[22] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[22]
--operation mode is normal

G1_low_data_out_HR[22] = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L135, pci_rstn, GLOBAL(pci_clk));

--G1L874Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[22]~854
--operation mode is normal

G1L874Q = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L135, pci_rstn, GLOBAL(pci_clk));


--G1L01 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~171
--operation mode is normal

G1L01 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[22], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L77 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1677
--operation mode is normal

G1L77 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[22], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L87 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1678
--operation mode is normal

G1L87 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[22], G1_trg_ad_sel, G1_mstr_ad_sel);


--G1L493 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[22]~598
--operation mode is normal

G1L493 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[22], G1L87);

--G1L593 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[22]~630
--operation mode is normal

G1L593 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[22], G1L87);


--E8_q[5] is lpm_counter:dpm_ni2f_rcounter_ix7|alt_counter_f10ke:wysi_counter|q[5]
--operation mode is clrb_cntr

E8_q[5]_lut_out = (E8_q[5] $ (dpm_ni2f_reg_sm_10 & E8L11)) & A1L905;
E8_q[5] = DFFEA(E8_q[5]_lut_out, lcst, , , , , );

--E8L52Q is lpm_counter:dpm_ni2f_rcounter_ix7|alt_counter_f10ke:wysi_counter|q[5]~5
--operation mode is clrb_cntr

E8L52Q = E8_q[5];


--E3_q[23] is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[23]
--operation mode is clrb_cntr

E3_q[23]_lut_out = (E3_q[23] $ (ix2252_lc & E3L74)) & VCC;
E3_q[23] = DFFEA(E3_q[23]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E3L311Q is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[23]~15
--operation mode is clrb_cntr

E3L311Q = E3_q[23];

--E3L94 is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[23]~COUT
--operation mode is clrb_cntr

E3L94 = CARRY(E3_q[23] & (E3L74));


--A1L925 is ix2221~0
--operation mode is normal

A1L925 = (E8_q[5] & !ix2322_lc & (!ix2321_lc # !E3_q[23]) # !E8_q[5] & (!ix2321_lc # !E3_q[23])) & CASCADE(A1L108);

--A1L035 is ix2221~1
--operation mode is normal

A1L035 = (E8_q[5] & !ix2322_lc & (!ix2321_lc # !E3_q[23]) # !E8_q[5] & (!ix2321_lc # !E3_q[23])) & CASCADE(A1L108);


--G1_low_data_out_HR[23] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[23]
--operation mode is normal

G1_low_data_out_HR[23] = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L925, pci_rstn, GLOBAL(pci_clk));

--G1L084Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[23]~855
--operation mode is normal

G1L084Q = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L925, pci_rstn, GLOBAL(pci_clk));


--G1L9 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~170
--operation mode is normal

G1L9 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[23], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L97 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1679
--operation mode is normal

G1L97 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[23], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L08 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1680
--operation mode is normal

G1L08 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[23], G1_trg_ad_sel, G1_mstr_ad_sel);


--G1L693 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[23]~599
--operation mode is normal

G1L693 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[23], G1L08);

--G1L793 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[23]~631
--operation mode is normal

G1L793 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[23], G1L08);


--dpm_ni2f_reg_sram_qH_8 is dpm_ni2f_reg_sram_qH_8
--operation mode is normal

dpm_ni2f_reg_sram_qH_8_lut_out = dpm_ni2f_reg_sm_10 & (SRAM_IO_8) # !dpm_ni2f_reg_sm_10 & dpm_ni2f_reg_sram_qH_8;
dpm_ni2f_reg_sram_qH_8 = DFFEA(dpm_ni2f_reg_sram_qH_8_lut_out, lcst, , , , , );

--A1L164Q is dpm_ni2f_reg_sram_qH_8~0
--operation mode is normal

A1L164Q = dpm_ni2f_reg_sram_qH_8;


--ix2423 is ix2423
--operation mode is normal

ix2423 = !dpm_ni2f_reg_sram_qH_8 # !M1_lt_adr[19];

--A1L0701 is ix2423~1
--operation mode is normal

A1L0701 = !dpm_ni2f_reg_sram_qH_8 # !M1_lt_adr[19];

--A1L1701 is ix2423~2
--operation mode is normal

A1L1701 = !dpm_ni2f_reg_sram_qH_8 # !M1_lt_adr[19];


--E2_q[24] is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[24]
--operation mode is clrb_cntr

E2_q[24]_lut_out = (E2_q[24] $ (ix2253_lc & E2L94)) & VCC;
E2_q[24] = DFFEA(E2_q[24]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E2L511Q is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[24]~0
--operation mode is clrb_cntr

E2L511Q = E2_q[24];

--E2L15 is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[24]~COUT
--operation mode is clrb_cntr

E2L15 = CARRY(E2_q[24] & (E2L94));


--E3_q[24] is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[24]
--operation mode is clrb_cntr

E3_q[24]_lut_out = (E3_q[24] $ (ix2252_lc & E3L94)) & VCC;
E3_q[24] = DFFEA(E3_q[24]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E3L511Q is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[24]~16
--operation mode is clrb_cntr

E3L511Q = E3_q[24];

--E3L15 is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[24]~COUT
--operation mode is clrb_cntr

E3L15 = CARRY(E3_q[24] & (E3L94));


--A1L725 is ix2220~0
--operation mode is normal

A1L725 = (E2_q[24] & !A1L877 & (!ix2321_lc # !E3_q[24]) # !E2_q[24] & (!ix2321_lc # !E3_q[24])) & CASCADE(A1L1701);

--A1L825 is ix2220~1
--operation mode is normal

A1L825 = (E2_q[24] & !A1L877 & (!ix2321_lc # !E3_q[24]) # !E2_q[24] & (!ix2321_lc # !E3_q[24])) & CASCADE(A1L1701);


--G1_low_data_out_HR[24] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[24]
--operation mode is normal

G1_low_data_out_HR[24] = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L725, pci_rstn, GLOBAL(pci_clk));

--G1L284Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[24]~856
--operation mode is normal

G1L284Q = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L725, pci_rstn, GLOBAL(pci_clk));


--G1L8 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~169
--operation mode is normal

G1L8 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[24], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L18 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1681
--operation mode is normal

G1L18 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[24], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L28 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1682
--operation mode is normal

G1L28 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[24], G1_trg_ad_sel, G1_mstr_ad_sel);


--G1L893 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[24]~600
--operation mode is normal

G1L893 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[24], G1L28);

--G1L993 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[24]~632
--operation mode is normal

G1L993 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[24], G1L28);


--dpm_ni2f_reg_sram_qH_9 is dpm_ni2f_reg_sram_qH_9
--operation mode is normal

dpm_ni2f_reg_sram_qH_9_lut_out = dpm_ni2f_reg_sm_10 & (SRAM_IO_9) # !dpm_ni2f_reg_sm_10 & dpm_ni2f_reg_sram_qH_9;
dpm_ni2f_reg_sram_qH_9 = DFFEA(dpm_ni2f_reg_sram_qH_9_lut_out, lcst, , , , , );

--A1L364Q is dpm_ni2f_reg_sram_qH_9~0
--operation mode is normal

A1L364Q = dpm_ni2f_reg_sram_qH_9;


--ix2424 is ix2424
--operation mode is normal

ix2424 = !dpm_ni2f_reg_sram_qH_9 # !M1_lt_adr[19];

--A1L3701 is ix2424~1
--operation mode is normal

A1L3701 = !dpm_ni2f_reg_sram_qH_9 # !M1_lt_adr[19];

--A1L4701 is ix2424~2
--operation mode is normal

A1L4701 = !dpm_ni2f_reg_sram_qH_9 # !M1_lt_adr[19];


--E2_q[25] is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[25]
--operation mode is clrb_cntr

E2_q[25]_lut_out = (E2_q[25] $ (ix2253_lc & E2L15)) & VCC;
E2_q[25] = DFFEA(E2_q[25]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E2L711Q is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[25]~1
--operation mode is clrb_cntr

E2L711Q = E2_q[25];

--E2L35 is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[25]~COUT
--operation mode is clrb_cntr

E2L35 = CARRY(E2_q[25] & (E2L15));


--E3_q[25] is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[25]
--operation mode is clrb_cntr

E3_q[25]_lut_out = (E3_q[25] $ (ix2252_lc & E3L15)) & VCC;
E3_q[25] = DFFEA(E3_q[25]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E3L711Q is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[25]~17
--operation mode is clrb_cntr

E3L711Q = E3_q[25];

--E3L35 is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[25]~COUT
--operation mode is clrb_cntr

E3L35 = CARRY(E3_q[25] & (E3L15));


--A1L525 is ix2219~0
--operation mode is normal

A1L525 = (E2_q[25] & !A1L877 & (!ix2321_lc # !E3_q[25]) # !E2_q[25] & (!ix2321_lc # !E3_q[25])) & CASCADE(A1L4701);

--A1L625 is ix2219~1
--operation mode is normal

A1L625 = (E2_q[25] & !A1L877 & (!ix2321_lc # !E3_q[25]) # !E2_q[25] & (!ix2321_lc # !E3_q[25])) & CASCADE(A1L4701);


--G1_low_data_out_HR[25] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[25]
--operation mode is normal

G1_low_data_out_HR[25] = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L525, pci_rstn, GLOBAL(pci_clk));

--G1L484Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[25]~857
--operation mode is normal

G1L484Q = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L525, pci_rstn, GLOBAL(pci_clk));


--G1L7 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~168
--operation mode is normal

G1L7 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[25], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L38 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1683
--operation mode is normal

G1L38 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[25], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L48 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1684
--operation mode is normal

G1L48 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[25], G1_trg_ad_sel, G1_mstr_ad_sel);


--G1L004 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[25]~601
--operation mode is normal

G1L004 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[25], G1L48);

--G1L104 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[25]~633
--operation mode is normal

G1L104 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[25], G1L48);


--dpm_ni2f_reg_sram_qH_10 is dpm_ni2f_reg_sram_qH_10
--operation mode is normal

dpm_ni2f_reg_sram_qH_10_lut_out = dpm_ni2f_reg_sm_10 & (SRAM_IO_10) # !dpm_ni2f_reg_sm_10 & dpm_ni2f_reg_sram_qH_10;
dpm_ni2f_reg_sram_qH_10 = DFFEA(dpm_ni2f_reg_sram_qH_10_lut_out, lcst, , , , , );

--A1L564Q is dpm_ni2f_reg_sram_qH_10~0
--operation mode is normal

A1L564Q = dpm_ni2f_reg_sram_qH_10;


--ix2425 is ix2425
--operation mode is normal

ix2425 = !dpm_ni2f_reg_sram_qH_10 # !M1_lt_adr[19];

--A1L6701 is ix2425~1
--operation mode is normal

A1L6701 = !dpm_ni2f_reg_sram_qH_10 # !M1_lt_adr[19];

--A1L7701 is ix2425~2
--operation mode is normal

A1L7701 = !dpm_ni2f_reg_sram_qH_10 # !M1_lt_adr[19];


--E2_q[26] is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[26]
--operation mode is clrb_cntr

E2_q[26]_lut_out = (E2_q[26] $ (ix2253_lc & E2L35)) & VCC;
E2_q[26] = DFFEA(E2_q[26]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E2L911Q is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[26]~2
--operation mode is clrb_cntr

E2L911Q = E2_q[26];

--E2L55 is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[26]~COUT
--operation mode is clrb_cntr

E2L55 = CARRY(E2_q[26] & (E2L35));


--E3_q[26] is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[26]
--operation mode is clrb_cntr

E3_q[26]_lut_out = (E3_q[26] $ (ix2252_lc & E3L35)) & VCC;
E3_q[26] = DFFEA(E3_q[26]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E3L911Q is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[26]~18
--operation mode is clrb_cntr

E3L911Q = E3_q[26];

--E3L55 is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[26]~COUT
--operation mode is clrb_cntr

E3L55 = CARRY(E3_q[26] & (E3L35));


--A1L325 is ix2218~0
--operation mode is normal

A1L325 = (E2_q[26] & !A1L877 & (!ix2321_lc # !E3_q[26]) # !E2_q[26] & (!ix2321_lc # !E3_q[26])) & CASCADE(A1L7701);

--A1L425 is ix2218~1
--operation mode is normal

A1L425 = (E2_q[26] & !A1L877 & (!ix2321_lc # !E3_q[26]) # !E2_q[26] & (!ix2321_lc # !E3_q[26])) & CASCADE(A1L7701);


--G1_low_data_out_HR[26] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[26]
--operation mode is normal

G1_low_data_out_HR[26] = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L325, pci_rstn, GLOBAL(pci_clk));

--G1L684Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[26]~858
--operation mode is normal

G1L684Q = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L325, pci_rstn, GLOBAL(pci_clk));


--G1L6 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~167
--operation mode is normal

G1L6 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[26], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L58 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1685
--operation mode is normal

G1L58 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[26], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L68 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1686
--operation mode is normal

G1L68 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[26], G1_trg_ad_sel, G1_mstr_ad_sel);


--G1L204 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[26]~602
--operation mode is normal

G1L204 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[26], G1L68);

--G1L304 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[26]~634
--operation mode is normal

G1L304 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[26], G1L68);


--dpm_ni2f_reg_sram_qH_11 is dpm_ni2f_reg_sram_qH_11
--operation mode is normal

dpm_ni2f_reg_sram_qH_11_lut_out = dpm_ni2f_reg_sm_10 & (SRAM_IO_11) # !dpm_ni2f_reg_sm_10 & dpm_ni2f_reg_sram_qH_11;
dpm_ni2f_reg_sram_qH_11 = DFFEA(dpm_ni2f_reg_sram_qH_11_lut_out, lcst, , , , , );

--A1L764Q is dpm_ni2f_reg_sram_qH_11~0
--operation mode is normal

A1L764Q = dpm_ni2f_reg_sram_qH_11;


--ix2426 is ix2426
--operation mode is normal

ix2426 = !dpm_ni2f_reg_sram_qH_11 # !M1_lt_adr[19];

--A1L9701 is ix2426~1
--operation mode is normal

A1L9701 = !dpm_ni2f_reg_sram_qH_11 # !M1_lt_adr[19];

--A1L0801 is ix2426~2
--operation mode is normal

A1L0801 = !dpm_ni2f_reg_sram_qH_11 # !M1_lt_adr[19];


--E2_q[27] is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[27]
--operation mode is clrb_cntr

E2_q[27]_lut_out = (E2_q[27] $ (ix2253_lc & E2L55)) & VCC;
E2_q[27] = DFFEA(E2_q[27]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E2L121Q is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[27]~3
--operation mode is clrb_cntr

E2L121Q = E2_q[27];

--E2L75 is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[27]~COUT
--operation mode is clrb_cntr

E2L75 = CARRY(E2_q[27] & (E2L55));


--E3_q[27] is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[27]
--operation mode is clrb_cntr

E3_q[27]_lut_out = (E3_q[27] $ (ix2252_lc & E3L55)) & VCC;
E3_q[27] = DFFEA(E3_q[27]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E3L121Q is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[27]~19
--operation mode is clrb_cntr

E3L121Q = E3_q[27];

--E3L75 is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[27]~COUT
--operation mode is clrb_cntr

E3L75 = CARRY(E3_q[27] & (E3L55));


--A1L125 is ix2217~0
--operation mode is normal

A1L125 = (E2_q[27] & !A1L877 & (!ix2321_lc # !E3_q[27]) # !E2_q[27] & (!ix2321_lc # !E3_q[27])) & CASCADE(A1L0801);

--A1L225 is ix2217~1
--operation mode is normal

A1L225 = (E2_q[27] & !A1L877 & (!ix2321_lc # !E3_q[27]) # !E2_q[27] & (!ix2321_lc # !E3_q[27])) & CASCADE(A1L0801);


--G1_low_data_out_HR[27] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[27]
--operation mode is normal

G1_low_data_out_HR[27] = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L125, pci_rstn, GLOBAL(pci_clk));

--G1L884Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[27]~859
--operation mode is normal

G1L884Q = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L125, pci_rstn, GLOBAL(pci_clk));


--G1L5 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~166
--operation mode is normal

G1L5 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[27], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L78 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1687
--operation mode is normal

G1L78 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[27], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L88 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1688
--operation mode is normal

G1L88 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[27], G1_trg_ad_sel, G1_mstr_ad_sel);


--G1L404 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[27]~603
--operation mode is normal

G1L404 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[27], G1L88);

--G1L504 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[27]~635
--operation mode is normal

G1L504 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[27], G1L88);


--dpm_ni2f_reg_sram_qH_12 is dpm_ni2f_reg_sram_qH_12
--operation mode is normal

dpm_ni2f_reg_sram_qH_12_lut_out = dpm_ni2f_reg_sm_10 & (SRAM_IO_12) # !dpm_ni2f_reg_sm_10 & dpm_ni2f_reg_sram_qH_12;
dpm_ni2f_reg_sram_qH_12 = DFFEA(dpm_ni2f_reg_sram_qH_12_lut_out, lcst, , , , , );

--A1L964Q is dpm_ni2f_reg_sram_qH_12~0
--operation mode is normal

A1L964Q = dpm_ni2f_reg_sram_qH_12;


--ix2427 is ix2427
--operation mode is normal

ix2427 = !dpm_ni2f_reg_sram_qH_12 # !M1_lt_adr[19];

--A1L2801 is ix2427~1
--operation mode is normal

A1L2801 = !dpm_ni2f_reg_sram_qH_12 # !M1_lt_adr[19];

--A1L3801 is ix2427~2
--operation mode is normal

A1L3801 = !dpm_ni2f_reg_sram_qH_12 # !M1_lt_adr[19];


--E2_q[28] is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[28]
--operation mode is clrb_cntr

E2_q[28]_lut_out = (E2_q[28] $ (ix2253_lc & E2L75)) & VCC;
E2_q[28] = DFFEA(E2_q[28]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E2L321Q is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[28]~4
--operation mode is clrb_cntr

E2L321Q = E2_q[28];

--E2L95 is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[28]~COUT
--operation mode is clrb_cntr

E2L95 = CARRY(E2_q[28] & (E2L75));


--E3_q[28] is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[28]
--operation mode is clrb_cntr

E3_q[28]_lut_out = (E3_q[28] $ (ix2252_lc & E3L75)) & VCC;
E3_q[28] = DFFEA(E3_q[28]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E3L321Q is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[28]~20
--operation mode is clrb_cntr

E3L321Q = E3_q[28];

--E3L95 is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[28]~COUT
--operation mode is clrb_cntr

E3L95 = CARRY(E3_q[28] & (E3L75));


--A1L915 is ix2216~0
--operation mode is normal

A1L915 = (E2_q[28] & !A1L877 & (!ix2321_lc # !E3_q[28]) # !E2_q[28] & (!ix2321_lc # !E3_q[28])) & CASCADE(A1L3801);

--A1L025 is ix2216~1
--operation mode is normal

A1L025 = (E2_q[28] & !A1L877 & (!ix2321_lc # !E3_q[28]) # !E2_q[28] & (!ix2321_lc # !E3_q[28])) & CASCADE(A1L3801);


--G1_low_data_out_HR[28] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[28]
--operation mode is normal

G1_low_data_out_HR[28] = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L915, pci_rstn, GLOBAL(pci_clk));

--G1L094Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[28]~860
--operation mode is normal

G1L094Q = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L915, pci_rstn, GLOBAL(pci_clk));


--G1L4 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~165
--operation mode is normal

G1L4 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[28], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L98 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1689
--operation mode is normal

G1L98 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[28], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L09 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1690
--operation mode is normal

G1L09 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[28], G1_trg_ad_sel, G1_mstr_ad_sel);


--G1L604 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[28]~604
--operation mode is normal

G1L604 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[28], G1L09);

--G1L704 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[28]~636
--operation mode is normal

G1L704 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[28], G1L09);


--dpm_ni2f_reg_sram_qH_13 is dpm_ni2f_reg_sram_qH_13
--operation mode is normal

dpm_ni2f_reg_sram_qH_13_lut_out = dpm_ni2f_reg_sm_10 & (SRAM_IO_13) # !dpm_ni2f_reg_sm_10 & dpm_ni2f_reg_sram_qH_13;
dpm_ni2f_reg_sram_qH_13 = DFFEA(dpm_ni2f_reg_sram_qH_13_lut_out, lcst, , , , , );

--A1L174Q is dpm_ni2f_reg_sram_qH_13~0
--operation mode is normal

A1L174Q = dpm_ni2f_reg_sram_qH_13;


--ix2428 is ix2428
--operation mode is normal

ix2428 = !dpm_ni2f_reg_sram_qH_13 # !M1_lt_adr[19];

--A1L5801 is ix2428~1
--operation mode is normal

A1L5801 = !dpm_ni2f_reg_sram_qH_13 # !M1_lt_adr[19];

--A1L6801 is ix2428~2
--operation mode is normal

A1L6801 = !dpm_ni2f_reg_sram_qH_13 # !M1_lt_adr[19];


--E2_q[29] is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[29]
--operation mode is clrb_cntr

E2_q[29]_lut_out = (E2_q[29] $ (ix2253_lc & E2L95)) & VCC;
E2_q[29] = DFFEA(E2_q[29]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E2L521Q is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[29]~5
--operation mode is clrb_cntr

E2L521Q = E2_q[29];

--E2L16 is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[29]~COUT
--operation mode is clrb_cntr

E2L16 = CARRY(E2_q[29] & (E2L95));


--E3_q[29] is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[29]
--operation mode is clrb_cntr

E3_q[29]_lut_out = (E3_q[29] $ (ix2252_lc & E3L95)) & VCC;
E3_q[29] = DFFEA(E3_q[29]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E3L521Q is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[29]~21
--operation mode is clrb_cntr

E3L521Q = E3_q[29];

--E3L16 is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[29]~COUT
--operation mode is clrb_cntr

E3L16 = CARRY(E3_q[29] & (E3L95));


--A1L715 is ix2215~0
--operation mode is normal

A1L715 = (E2_q[29] & !A1L877 & (!ix2321_lc # !E3_q[29]) # !E2_q[29] & (!ix2321_lc # !E3_q[29])) & CASCADE(A1L6801);

--A1L815 is ix2215~1
--operation mode is normal

A1L815 = (E2_q[29] & !A1L877 & (!ix2321_lc # !E3_q[29]) # !E2_q[29] & (!ix2321_lc # !E3_q[29])) & CASCADE(A1L6801);


--G1_low_data_out_HR[29] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[29]
--operation mode is normal

G1_low_data_out_HR[29] = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L715, pci_rstn, GLOBAL(pci_clk));

--G1L294Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[29]~861
--operation mode is normal

G1L294Q = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L715, pci_rstn, GLOBAL(pci_clk));


--G1L3 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~164
--operation mode is normal

G1L3 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[29], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L19 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1691
--operation mode is normal

G1L19 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[29], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L29 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1692
--operation mode is normal

G1L29 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[29], G1_trg_ad_sel, G1_mstr_ad_sel);


--G1L804 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[29]~605
--operation mode is normal

G1L804 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[29], G1L29);

--G1L904 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[29]~637
--operation mode is normal

G1L904 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[29], G1L29);


--dpm_ni2f_reg_sram_qH_14 is dpm_ni2f_reg_sram_qH_14
--operation mode is normal

dpm_ni2f_reg_sram_qH_14_lut_out = dpm_ni2f_reg_sm_10 & (SRAM_IO_14) # !dpm_ni2f_reg_sm_10 & dpm_ni2f_reg_sram_qH_14;
dpm_ni2f_reg_sram_qH_14 = DFFEA(dpm_ni2f_reg_sram_qH_14_lut_out, lcst, , , , , );

--A1L374Q is dpm_ni2f_reg_sram_qH_14~0
--operation mode is normal

A1L374Q = dpm_ni2f_reg_sram_qH_14;


--ix2429 is ix2429
--operation mode is normal

ix2429 = !dpm_ni2f_reg_sram_qH_14 # !M1_lt_adr[19];

--A1L8801 is ix2429~1
--operation mode is normal

A1L8801 = !dpm_ni2f_reg_sram_qH_14 # !M1_lt_adr[19];

--A1L9801 is ix2429~2
--operation mode is normal

A1L9801 = !dpm_ni2f_reg_sram_qH_14 # !M1_lt_adr[19];


--E2_q[30] is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[30]
--operation mode is clrb_cntr

E2_q[30]_lut_out = (E2_q[30] $ (ix2253_lc & E2L16)) & VCC;
E2_q[30] = DFFEA(E2_q[30]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E2L721Q is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[30]~6
--operation mode is clrb_cntr

E2L721Q = E2_q[30];

--E2L36 is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[30]~COUT
--operation mode is clrb_cntr

E2L36 = CARRY(E2_q[30] & (E2L16));


--E3_q[30] is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[30]
--operation mode is clrb_cntr

E3_q[30]_lut_out = (E3_q[30] $ (ix2252_lc & E3L16)) & VCC;
E3_q[30] = DFFEA(E3_q[30]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E3L721Q is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[30]~22
--operation mode is clrb_cntr

E3L721Q = E3_q[30];

--E3L36 is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[30]~COUT
--operation mode is clrb_cntr

E3L36 = CARRY(E3_q[30] & (E3L16));


--A1L515 is ix2214~0
--operation mode is normal

A1L515 = (E2_q[30] & !A1L877 & (!ix2321_lc # !E3_q[30]) # !E2_q[30] & (!ix2321_lc # !E3_q[30])) & CASCADE(A1L9801);

--A1L615 is ix2214~1
--operation mode is normal

A1L615 = (E2_q[30] & !A1L877 & (!ix2321_lc # !E3_q[30]) # !E2_q[30] & (!ix2321_lc # !E3_q[30])) & CASCADE(A1L9801);


--G1_low_data_out_HR[30] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[30]
--operation mode is normal

G1_low_data_out_HR[30] = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L515, pci_rstn, GLOBAL(pci_clk));

--G1L494Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[30]~862
--operation mode is normal

G1L494Q = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L515, pci_rstn, GLOBAL(pci_clk));


--G1L2 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~163
--operation mode is normal

G1L2 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[30], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L39 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1693
--operation mode is normal

G1L39 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[30], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L49 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1694
--operation mode is normal

G1L49 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[30], G1_trg_ad_sel, G1_mstr_ad_sel);


--G1L014 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[30]~606
--operation mode is normal

G1L014 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[30], G1L49);

--G1L114 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[30]~638
--operation mode is normal

G1L114 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[30], G1L49);


--dpm_ni2f_reg_sram_qH_15 is dpm_ni2f_reg_sram_qH_15
--operation mode is normal

dpm_ni2f_reg_sram_qH_15_lut_out = dpm_ni2f_reg_sm_10 & (SRAM_IO_15) # !dpm_ni2f_reg_sm_10 & dpm_ni2f_reg_sram_qH_15;
dpm_ni2f_reg_sram_qH_15 = DFFEA(dpm_ni2f_reg_sram_qH_15_lut_out, lcst, , , , , );

--A1L574Q is dpm_ni2f_reg_sram_qH_15~0
--operation mode is normal

A1L574Q = dpm_ni2f_reg_sram_qH_15;


--ix2430 is ix2430
--operation mode is normal

ix2430 = !dpm_ni2f_reg_sram_qH_15 # !M1_lt_adr[19];

--A1L1901 is ix2430~1
--operation mode is normal

A1L1901 = !dpm_ni2f_reg_sram_qH_15 # !M1_lt_adr[19];

--A1L2901 is ix2430~2
--operation mode is normal

A1L2901 = !dpm_ni2f_reg_sram_qH_15 # !M1_lt_adr[19];


--E2_q[31] is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[31]
--operation mode is clrb_cntr

E2_q[31]_lut_out = (E2_q[31] $ (ix2253_lc & E2L36)) & VCC;
E2_q[31] = DFFEA(E2_q[31]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E2L921Q is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[31]~7
--operation mode is clrb_cntr

E2L921Q = E2_q[31];


--E3_q[31] is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[31]
--operation mode is clrb_cntr

E3_q[31]_lut_out = (E3_q[31] $ (ix2252_lc & E3L36)) & VCC;
E3_q[31] = DFFEA(E3_q[31]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E3L921Q is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[31]~23
--operation mode is clrb_cntr

E3L921Q = E3_q[31];


--A1L315 is ix2213~0
--operation mode is normal

A1L315 = (E2_q[31] & !A1L877 & (!ix2321_lc # !E3_q[31]) # !E2_q[31] & (!ix2321_lc # !E3_q[31])) & CASCADE(A1L2901);

--A1L415 is ix2213~1
--operation mode is normal

A1L415 = (E2_q[31] & !A1L877 & (!ix2321_lc # !E3_q[31]) # !E2_q[31] & (!ix2321_lc # !E3_q[31])) & CASCADE(A1L2901);


--G1_low_data_out_HR[31] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[31]
--operation mode is normal

G1_low_data_out_HR[31] = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L315, pci_rstn, GLOBAL(pci_clk));

--G1L694Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR[31]~863
--operation mode is normal

G1L694Q = AMPP_FUNCTION(G1_low_data_out_hr_ena_d, G1_low_data_out_HR_lc, G1_mstr_ad_sel, A1L315, pci_rstn, GLOBAL(pci_clk));


--G1L1 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~162
--operation mode is normal

G1L1 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[31], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L59 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1695
--operation mode is normal

G1L59 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[31], G1_trg_ad_sel, G1_mstr_ad_sel);

--G1L69 is pci_contr:pci|pci_mt32:pci_mt32_inst|_~1696
--operation mode is normal

G1L69 = AMPP_FUNCTION(G1_mstr_trg_hr_dat_sel, G1_low_data_out_HR[31], G1_trg_ad_sel, G1_mstr_ad_sel);


--G1L214 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[31]~607
--operation mode is normal

G1L214 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[31], G1L69);

--G1L314 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_out_lc1_NOT[31]~639
--operation mode is normal

G1L314 = AMPP_FUNCTION(G1_trg_cfg_cyc_out, G1_trg_ad_sel, G1_trg_cfg_ad_out[31], G1L69);


--J1_lm_adr_ack_R is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lm_adr_ack_R
--operation mode is normal

J1_lm_adr_ack_R = AMPP_FUNCTION(J1_lm_adr_ack_R_lc1, J1_lm_adr_ack_R, J1_lm_adr_ack_R_lc2, pci_gntn, pci_rstn, GLOBAL(pci_clk));

--J1L082Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lm_adr_ack_R~11
--operation mode is normal

J1L082Q = AMPP_FUNCTION(J1_lm_adr_ack_R_lc1, J1_lm_adr_ack_R, J1_lm_adr_ack_R_lc2, pci_gntn, pci_rstn, GLOBAL(pci_clk));


--J1_cbe_oer_r1_lc3 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|cbe_oer_r1_lc3
--operation mode is normal

J1_cbe_oer_r1_lc3 = AMPP_FUNCTION(J1_MS_ADR, J1_MS_ADR2, J1_cbe_oer_r1_lc2);

--J1L931 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|cbe_oer_r1_lc3~22
--operation mode is normal

J1L931 = AMPP_FUNCTION(J1_MS_ADR, J1_MS_ADR2, J1_cbe_oer_r1_lc2);


--J1_cbe_oer_r3_d is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|cbe_oer_r3_d
--operation mode is normal

J1_cbe_oer_r3_d = AMPP_FUNCTION(J1_MS_DXFR, J1_mstr_abrt);

--J1L441 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|cbe_oer_r3_d~8
--operation mode is normal

J1L441 = AMPP_FUNCTION(J1_MS_DXFR, J1_mstr_abrt);


--M1_devsel_OR_lc[1] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|devsel_OR_lc[1]
--operation mode is normal

M1_devsel_OR_lc[1] = AMPP_FUNCTION(M1_TS_DISC, M1_TS_DXFR);

--M1L671 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|devsel_OR_lc[1]~11
--operation mode is normal

M1L671 = AMPP_FUNCTION(M1_TS_DISC, M1_TS_DXFR);


--M1_targ_oeR_reg_lc[3] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|targ_oeR_reg_lc[3]
--operation mode is normal

M1_targ_oeR_reg_lc[3] = AMPP_FUNCTION(M1_TS_IDLE_NOT, M1_TS_TURN_AR);

--M1L284 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|targ_oeR_reg_lc[3]~65
--operation mode is normal

M1L284 = AMPP_FUNCTION(M1_TS_IDLE_NOT, M1_TS_TURN_AR);


--M1_targ_oeR_reg_lc[2] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|targ_oeR_reg_lc[2]
--operation mode is normal

M1_targ_oeR_reg_lc[2] = AMPP_FUNCTION(M1_TS_IDLE_NOT, G1_ad_ir_address[1], G1_ad_ir_address[0]);

--M1L974 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|targ_oeR_reg_lc[2]~66
--operation mode is normal

M1L974 = AMPP_FUNCTION(M1_TS_IDLE_NOT, G1_ad_ir_address[1], G1_ad_ir_address[0]);


--M1_idsel_IR is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|idsel_IR
--operation mode is normal

M1_idsel_IR = AMPP_FUNCTION(pci_idsel, pci_rstn, GLOBAL(pci_clk));

--M1L781Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|idsel_IR~2
--operation mode is normal

M1L781Q = AMPP_FUNCTION(pci_idsel, pci_rstn, GLOBAL(pci_clk));


--M1_targ_oeR_reg_lc[1] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|targ_oeR_reg_lc[1]
--operation mode is normal

M1_targ_oeR_reg_lc[1] = AMPP_FUNCTION(G1_cben_ir_address[3], G1_cben_ir_address[1], M1_idsel_IR, G1_cben_ir_address[2]);

--M1L674 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|targ_oeR_reg_lc[1]~67
--operation mode is normal

M1L674 = AMPP_FUNCTION(G1_cben_ir_address[3], G1_cben_ir_address[1], M1_idsel_IR, G1_cben_ir_address[2]);


--P1_bar_hit[0] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|bar_hit[0]
--operation mode is normal

P1_bar_hit[0] = AMPP_FUNCTION(M1_adr_phase_lc1, P1_cyc_vld[0], U41_aeb_out);

--P1L701 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|bar_hit[0]~22
--operation mode is normal

P1L701 = AMPP_FUNCTION(M1_adr_phase_lc1, P1_cyc_vld[0], U41_aeb_out);


--M1_TS_IDLE_d_lc is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|TS_IDLE_d_lc
--operation mode is normal

M1_TS_IDLE_d_lc = AMPP_FUNCTION(M1_TS_TURN_AR, K1_serr_or, M1_TS_ADR_VLD);

--M1L635 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|TS_IDLE_d_lc~8
--operation mode is normal

M1L635 = AMPP_FUNCTION(M1_TS_TURN_AR, K1_serr_or, M1_TS_ADR_VLD);


--M1_TS_IDLE_d_lc1 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|TS_IDLE_d_lc1
--operation mode is normal

M1_TS_IDLE_d_lc1 = AMPP_FUNCTION(M1_TS_IDLE_NOT, M1L861);

--M1L435 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|TS_IDLE_d_lc1~1
--operation mode is normal

M1L435 = AMPP_FUNCTION(M1_TS_IDLE_NOT, M1L861);


--J1_frame_or_lc2 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|frame_or_lc2
--operation mode is normal

J1_frame_or_lc2 = AMPP_FUNCTION(J1_frame_or_lc2a, J1_frame_or_lc2b);

--J1L002 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|frame_or_lc2~1
--operation mode is normal

J1L002 = AMPP_FUNCTION(J1_frame_or_lc2a, J1_frame_or_lc2b);


--J1L86 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|_~380
--operation mode is normal

J1L86 = AMPP_FUNCTION(A1L7421, J1_irdy_or_lc[7]);

--J1L29 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|_~1146
--operation mode is normal

J1L29 = AMPP_FUNCTION(A1L7421, J1_irdy_or_lc[7]);

--J1L39 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|_~1147
--operation mode is normal

J1L39 = AMPP_FUNCTION(A1L7421, J1_irdy_or_lc[7]);


--J1L81 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|$00145~10
--operation mode is normal

J1L81 = AMPP_FUNCTION(A1L7421, J1_irdy_or_lc[8], J1_irdy_or_lc[6], A1L5421, J1L39);

--J1L91 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|$00145~12
--operation mode is normal

J1L91 = AMPP_FUNCTION(A1L7421, J1_irdy_or_lc[8], J1_irdy_or_lc[6], A1L5421, J1L39);

--J1L02 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|$00145~13
--operation mode is normal

J1L02 = AMPP_FUNCTION(A1L7421, J1_irdy_or_lc[8], J1_irdy_or_lc[6], A1L5421, J1L39);


--J1_MW_HOLD is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_HOLD
--operation mode is normal

J1_MW_HOLD = AMPP_FUNCTION(J1_MW_HOLD_lc[1], A1L5421, J1_MW_HOLD_lc[2], pci_rstn, GLOBAL(pci_clk), J1L05);

--J1L384Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_HOLD~5
--operation mode is normal

J1L384Q = AMPP_FUNCTION(J1_MW_HOLD_lc[1], A1L5421, J1_MW_HOLD_lc[2], pci_rstn, GLOBAL(pci_clk), J1L05);


--J1_park is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|park
--operation mode is normal

J1_park = AMPP_FUNCTION(A1L0321, P1_cmd_reg[2], pci_gntn, pci_rstn, GLOBAL(pci_clk), J1L385);

--J1L485Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|park~30
--operation mode is normal

J1L485Q = AMPP_FUNCTION(A1L0321, P1_cmd_reg[2], pci_gntn, pci_rstn, GLOBAL(pci_clk), J1L385);


--J1_MS_ENA_d_lc is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MS_ENA_d_lc
--operation mode is normal

J1_MS_ENA_d_lc = AMPP_FUNCTION(J1_MS_REQ, J1_park);

--J1L693 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MS_ENA_d_lc~22
--operation mode is normal

J1L693 = AMPP_FUNCTION(J1_MS_REQ, J1_park);


--P1_cmd_reg[2] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|cmd_reg[2]
--operation mode is normal

P1_cmd_reg[2] = AMPP_FUNCTION(P1L771, G1_low_ad_IR_data[2], pci_rstn, GLOBAL(pci_clk));

--P1L431Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|cmd_reg[2]~8
--operation mode is normal

P1L431Q = AMPP_FUNCTION(P1L771, G1_low_ad_IR_data[2], pci_rstn, GLOBAL(pci_clk));


--J1_MR_IDLE_not is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_IDLE_not
--operation mode is normal

J1_MR_IDLE_not = AMPP_FUNCTION(J1_MR_END, J1_MR_IDLE_not, J1_MR_IDLE_lc1, pci_rstn, GLOBAL(pci_clk));

--J1L003Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_IDLE_not~12
--operation mode is normal

J1L003Q = AMPP_FUNCTION(J1_MR_END, J1_MR_IDLE_not, J1_MR_IDLE_lc1, pci_rstn, GLOBAL(pci_clk));


--J1_l_req_vld is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|l_req_vld
--operation mode is normal

J1_l_req_vld = AMPP_FUNCTION(P1_cmd_reg[2], J1_MR_IDLE_not);

--J1L452 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|l_req_vld~17
--operation mode is normal

J1L452 = AMPP_FUNCTION(P1_cmd_reg[2], J1_MR_IDLE_not);


--L1_parc[10] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pg:parity_gen|parc[10]
--operation mode is arithmetic

L1_parc[10] = AMPP_FUNCTION();

--L1L43 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pg:parity_gen|parc[10]~39
--operation mode is arithmetic

L1L43 = AMPP_FUNCTION();

--L1L53 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pg:parity_gen|parc[10]~COUT
--operation mode is arithmetic

L1L53 = AMPP_FUNCTION(L1_par[9], L1_par[8]);


--G1_trg_par_oe is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_par_oe
--operation mode is normal

G1_trg_par_oe = AMPP_FUNCTION(N3_REG, M1_TS_TURN_AR, M1_TS_IDLE_NOT);

--G1L556 is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_par_oe~7
--operation mode is normal

G1L556 = AMPP_FUNCTION(N3_REG, M1_TS_TURN_AR, M1_TS_IDLE_NOT);


--G1_mstr_par_oe_lc1 is pci_contr:pci|pci_mt32:pci_mt32_inst|mstr_par_oe_lc1
--operation mode is normal

G1_mstr_par_oe_lc1 = AMPP_FUNCTION(J1_MS_ADR2, J1_MS_PARK, J1_MS_DXFR, J1_wr_rdn);

--G1L725 is pci_contr:pci|pci_mt32:pci_mt32_inst|mstr_par_oe_lc1~7
--operation mode is normal

G1L725 = AMPP_FUNCTION(J1_MS_ADR2, J1_MS_PARK, J1_MS_DXFR, J1_wr_rdn);


--J1_perr_vldr_carry is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|perr_vldr_carry
--operation mode is arithmetic

J1_perr_vldr_carry = AMPP_FUNCTION();

--J1L195 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|perr_vldr_carry~11
--operation mode is arithmetic

J1L195 = AMPP_FUNCTION();

--J1L295 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|perr_vldr_carry~COUT
--operation mode is arithmetic

J1L295 = AMPP_FUNCTION(A1L7421, J1_wr_rdn);


--K1_xxl[10] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|xxl[10]
--operation mode is normal

K1_xxl[10] = AMPP_FUNCTION(K1_xxl[7], K1_xxl[6], K1_xxl[5], K1_xxl[4]);

--K1L84 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|xxl[10]~225
--operation mode is normal

K1L84 = AMPP_FUNCTION(K1_xxl[7], K1_xxl[6], K1_xxl[5], K1_xxl[4]);


--K1_xxl[9] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|xxl[9]
--operation mode is normal

K1_xxl[9] = AMPP_FUNCTION(K1_xxl[3], K1_xxl[2], K1_xxl[1], K1_xxl[0]);

--K1L54 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|xxl[9]~226
--operation mode is normal

K1L54 = AMPP_FUNCTION(K1_xxl[3], K1_xxl[2], K1_xxl[1], K1_xxl[0]);


--G1_low_cben_IR_data[3] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_cben_IR_data[3]
--operation mode is normal

G1_low_cben_IR_data[3] = AMPP_FUNCTION(G1_cben_IR_ce_data, pci_cben_3, pci_rstn, GLOBAL(pci_clk));

--G1L224Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_cben_IR_data[3]~6
--operation mode is normal

G1L224Q = AMPP_FUNCTION(G1_cben_IR_ce_data, pci_cben_3, pci_rstn, GLOBAL(pci_clk));


--G1_low_cben_IR_data[2] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_cben_IR_data[2]
--operation mode is normal

G1_low_cben_IR_data[2] = AMPP_FUNCTION(G1_cben_IR_ce_data, pci_cben_2, pci_rstn, GLOBAL(pci_clk));

--G1L024Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_cben_IR_data[2]~7
--operation mode is normal

G1L024Q = AMPP_FUNCTION(G1_cben_IR_ce_data, pci_cben_2, pci_rstn, GLOBAL(pci_clk));


--K1_xxl[8] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|xxl[8]
--operation mode is normal

K1_xxl[8] = AMPP_FUNCTION(G1_low_cben_IR_data[0], G1_low_cben_IR_data[1], G1_low_cben_IR_data[3], G1_low_cben_IR_data[2]);

--K1L24 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|xxl[8]~227
--operation mode is normal

K1L24 = AMPP_FUNCTION(G1_low_cben_IR_data[0], G1_low_cben_IR_data[1], G1_low_cben_IR_data[3], G1_low_cben_IR_data[2]);


--M1_LW_DONE is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LW_DONE
--operation mode is normal

M1_LW_DONE = AMPP_FUNCTION(M1_LW_DONE_lc[2], M1_LW_LXFR, pci_rstn, GLOBAL(pci_clk), M1L873);

--M1L683Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LW_DONE~14
--operation mode is normal

M1L683Q = AMPP_FUNCTION(M1_LW_DONE_lc[2], M1_LW_LXFR, pci_rstn, GLOBAL(pci_clk), M1L873);


--M1_stop_or_lc[5] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|stop_or_lc[5]
--operation mode is normal

M1_stop_or_lc[5] = AMPP_FUNCTION(M1_cfg_cyc, M1_TS_DXFR, M1_targ_burst_lc, M1_stop_OR_NOT);

--M1L364 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|stop_or_lc[5]~51
--operation mode is normal

M1L364 = AMPP_FUNCTION(M1_cfg_cyc, M1_TS_DXFR, M1_targ_burst_lc, M1_stop_OR_NOT);


--dpm_ni2f_fifo_l_reg_fifo_full is dpm_ni2f_fifo_l_reg_fifo_full
--operation mode is normal

dpm_ni2f_fifo_l_reg_fifo_full_lut_out = ix2285_lc & !dpm_ni2f_reg_rdreq_fifo & (A1L091) # !ix2285_lc & (dpm_ni2f_fifo_l_reg_fifo_full);
dpm_ni2f_fifo_l_reg_fifo_full = DFFEA(dpm_ni2f_fifo_l_reg_fifo_full_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--A1L302Q is dpm_ni2f_fifo_l_reg_fifo_full~0
--operation mode is normal

A1L302Q = dpm_ni2f_fifo_l_reg_fifo_full;


--dpm_ni2f_fifo_l_reg_fifo_empty is dpm_ni2f_fifo_l_reg_fifo_empty
--operation mode is normal

dpm_ni2f_fifo_l_reg_fifo_empty_lut_out = ix2284_lc & (dpm_ni2f_reg_des_valid_data # !A1L891) # !ix2284_lc & (dpm_ni2f_fifo_l_reg_fifo_empty);
dpm_ni2f_fifo_l_reg_fifo_empty = DFFEA(dpm_ni2f_fifo_l_reg_fifo_empty_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--A1L102Q is dpm_ni2f_fifo_l_reg_fifo_empty~0
--operation mode is normal

A1L102Q = dpm_ni2f_fifo_l_reg_fifo_empty;


--ix2288_lc is ix2288_lc
--operation mode is normal

ix2288_lc = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_l_reg_fifo_full & (dpm_ni2f_fifo_l_reg_fifo_empty # !dpm_ni2f_reg_rdreq_fifo);

--A1L296 is ix2288_lc~0
--operation mode is normal

A1L296 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_l_reg_fifo_full & (dpm_ni2f_fifo_l_reg_fifo_empty # !dpm_ni2f_reg_rdreq_fifo);


--ix2287_lc is ix2287_lc
--operation mode is normal

ix2287_lc = dpm_ni2f_reg_rdreq_fifo & dpm_ni2f_fifo_l_reg_fifo_empty & (!dpm_ni2f_fifo_l_reg_fifo_full # !dpm_ni2f_reg_des_valid_data);

--A1L986 is ix2287_lc~0
--operation mode is normal

A1L986 = dpm_ni2f_reg_rdreq_fifo & dpm_ni2f_fifo_l_reg_fifo_empty & (!dpm_ni2f_fifo_l_reg_fifo_full # !dpm_ni2f_reg_des_valid_data);


--ix2304_lc is ix2304_lc
--operation mode is normal

ix2304_lc = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_h_reg_fifo_full & (dpm_ni2f_fifo_h_reg_fifo_empty # !dpm_ni2f_reg_rdreq_fifo);

--A1L927 is ix2304_lc~0
--operation mode is normal

A1L927 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_h_reg_fifo_full & (dpm_ni2f_fifo_h_reg_fifo_empty # !dpm_ni2f_reg_rdreq_fifo);


--ix2303_lc is ix2303_lc
--operation mode is normal

ix2303_lc = dpm_ni2f_reg_rdreq_fifo & dpm_ni2f_fifo_h_reg_fifo_empty & (!dpm_ni2f_fifo_h_reg_fifo_full # !dpm_ni2f_reg_des_valid_data);

--A1L627 is ix2303_lc~0
--operation mode is normal

A1L627 = dpm_ni2f_reg_rdreq_fifo & dpm_ni2f_fifo_h_reg_fifo_empty & (!dpm_ni2f_fifo_h_reg_fifo_full # !dpm_ni2f_reg_des_valid_data);


--ix2302_lc is ix2302_lc
--operation mode is normal

ix2302_lc = dpm_ni2f_reg_rdreq_fifo & (dpm_ni2f_fifo_h_reg_fifo_empty $ (dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_h_reg_fifo_full)) # !dpm_ni2f_reg_rdreq_fifo & dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_h_reg_fifo_full;

--A1L327 is ix2302_lc~0
--operation mode is normal

A1L327 = dpm_ni2f_reg_rdreq_fifo & (dpm_ni2f_fifo_h_reg_fifo_empty $ (dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_h_reg_fifo_full)) # !dpm_ni2f_reg_rdreq_fifo & dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_h_reg_fifo_full;


--A1L67 is dpm_ni2f_fifo_h_modgen_eq_69_ix25~0
--operation mode is normal

A1L67 = (dpm_ni2f_fifo_h_reg_nwords_2 & dpm_ni2f_fifo_h_reg_nwords_1 & !dpm_ni2f_fifo_h_reg_nwords_0) & CASCADE(A1L57);

--A1L77 is dpm_ni2f_fifo_h_modgen_eq_69_ix25~1
--operation mode is normal

A1L77 = (dpm_ni2f_fifo_h_reg_nwords_2 & dpm_ni2f_fifo_h_reg_nwords_1 & !dpm_ni2f_fifo_h_reg_nwords_0) & CASCADE(A1L57);


--M1_cfg_adr_dec_ena_lc2 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|cfg_adr_dec_ena_lc2
--operation mode is normal

M1_cfg_adr_dec_ena_lc2 = AMPP_FUNCTION(G1_cben_ir_address[3], G1_cben_ir_address[1], G1_cben_ir_address[2]);

--M1L551 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|cfg_adr_dec_ena_lc2~1
--operation mode is normal

M1L551 = AMPP_FUNCTION(G1_cben_ir_address[3], G1_cben_ir_address[1], G1_cben_ir_address[2]);


--M1L061 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|cfg_cyc~115
--operation mode is normal

M1L061 = AMPP_FUNCTION(M1_idsel_IR, G1_ad_ir_address[1], G1_ad_ir_address[0]);

--M1L361 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|cfg_cyc~119
--operation mode is normal

M1L361 = AMPP_FUNCTION(M1_idsel_IR, G1_ad_ir_address[1], G1_ad_ir_address[0]);


--M1L161 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|cfg_cyc~116
--operation mode is normal

M1L161 = AMPP_FUNCTION(M1_adr_phase_lc1, M1_cfg_adr_dec_ena_lc2, M1L061);

--M1L461 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|cfg_cyc~120
--operation mode is normal

M1L461 = AMPP_FUNCTION(M1_adr_phase_lc1, M1_cfg_adr_dec_ena_lc2, M1L061);


--R1_dec_up[0] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|pcimt32_cd:cfg_adr_dec|dec_up[0]
--operation mode is normal

R1_dec_up[0] = AMPP_FUNCTION(G1_ad_ir_address[4], G1_ad_ir_address[5], G1_ad_ir_address[6], G1_ad_ir_address[7]);

--R1L4 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|pcimt32_cd:cfg_adr_dec|dec_up[0]~54
--operation mode is normal

R1L4 = AMPP_FUNCTION(G1_ad_ir_address[4], G1_ad_ir_address[5], G1_ad_ir_address[6], G1_ad_ir_address[7]);


--G1_cben_IR_ce_data is pci_contr:pci|pci_mt32:pci_mt32_inst|cben_IR_ce_data
--operation mode is normal

G1_cben_IR_ce_data = AMPP_FUNCTION(G1_mstr_cben_ir_ce_d, G1_trg_cben_IR_ce_D);

--G1L781 is pci_contr:pci|pci_mt32:pci_mt32_inst|cben_IR_ce_data~1
--operation mode is normal

G1L781 = AMPP_FUNCTION(G1_mstr_cben_ir_ce_d, G1_trg_cben_IR_ce_D);


--G1_cben_IR_ce_address is pci_contr:pci|pci_mt32:pci_mt32_inst|cben_IR_ce_address
--operation mode is normal

G1_cben_IR_ce_address = AMPP_FUNCTION(J1_MS_ADR, J1_MS_ADR2, G1_trg_cben_IR_ce_A);

--G1L481 is pci_contr:pci|pci_mt32:pci_mt32_inst|cben_IR_ce_address~15
--operation mode is normal

G1L481 = AMPP_FUNCTION(J1_MS_ADR, J1_MS_ADR2, G1_trg_cben_IR_ce_A);


--J1_MR_LLXFR_r1 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LLXFR_r1
--operation mode is normal

J1_MR_LLXFR_r1 = AMPP_FUNCTION(J1_MR_LLXFR_r1_d_lc1, J1_no_op_reg[1], A1L5421, A1L7421, pci_rstn, GLOBAL(pci_clk));

--J1L323Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LLXFR_r1~16
--operation mode is normal

J1L323Q = AMPP_FUNCTION(J1_MR_LLXFR_r1_d_lc1, J1_no_op_reg[1], A1L5421, A1L7421, pci_rstn, GLOBAL(pci_clk));


--J1_MR_LLWAIT_r1 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LLWAIT_r1
--operation mode is normal

J1_MR_LLWAIT_r1 = AMPP_FUNCTION(J1_MR_LLWAIT_r1_lc2, A1L5421, pci_rstn, GLOBAL(pci_clk), J1L503);

--J1L013Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LLWAIT_r1~7
--operation mode is normal

J1L013Q = AMPP_FUNCTION(J1_MR_LLWAIT_r1_lc2, A1L5421, pci_rstn, GLOBAL(pci_clk), J1L503);


--J1_MR_LLWAIT_r2 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LLWAIT_r2
--operation mode is normal

J1_MR_LLWAIT_r2 = AMPP_FUNCTION(J1_devsel_toR, pci_rstn, GLOBAL(pci_clk), J1L413);

--J1L513Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LLWAIT_r2~7
--operation mode is normal

J1L513Q = AMPP_FUNCTION(J1_devsel_toR, pci_rstn, GLOBAL(pci_clk), J1L413);


--J1L99 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|ad_IR_ce_D~31
--operation mode is normal

J1L99 = AMPP_FUNCTION(J1_MS_IDLE_not, J1_MR_LLXFR_r1, J1_MR_LLWAIT_r1, J1_MR_LLWAIT_r2);

--J1L101 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|ad_IR_ce_D~33
--operation mode is normal

J1L101 = AMPP_FUNCTION(J1_MS_IDLE_not, J1_MR_LLXFR_r1, J1_MR_LLWAIT_r1, J1_MR_LLWAIT_r2);


--J1_MR_LLXFR_r2 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LLXFR_r2
--operation mode is normal

J1_MR_LLXFR_r2 = AMPP_FUNCTION(pci_rstn, GLOBAL(pci_clk), J1L723);

--J1L133Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LLXFR_r2~19
--operation mode is normal

J1L133Q = AMPP_FUNCTION(pci_rstn, GLOBAL(pci_clk), J1L723);


--J1_MR_LWAIT is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LWAIT
--operation mode is normal

J1_MR_LWAIT = AMPP_FUNCTION(J1_MR_LWAIT_lc2, A1L5421, pci_rstn, GLOBAL(pci_clk), J1L843);

--J1L453Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LWAIT~0
--operation mode is normal

J1L453Q = AMPP_FUNCTION(J1_MR_LWAIT_lc2, A1L5421, pci_rstn, GLOBAL(pci_clk), J1L843);


--G1_mstr_ad_IR_ce_D is pci_contr:pci|pci_mt32:pci_mt32_inst|mstr_ad_IR_ce_D
--operation mode is normal

G1_mstr_ad_IR_ce_D = AMPP_FUNCTION(J1L99, J1_MR_LLXFR_r2, J1_MR_LWAIT);

--G1L715 is pci_contr:pci|pci_mt32:pci_mt32_inst|mstr_ad_IR_ce_D~7
--operation mode is normal

G1L715 = AMPP_FUNCTION(J1L99, J1_MR_LLXFR_r2, J1_MR_LWAIT);


--G1_trg_ad_IR_ce_D is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_ad_IR_ce_D
--operation mode is normal

G1_trg_ad_IR_ce_D = AMPP_FUNCTION(M1_ad_ir_ce_D_lc1, M1_TS_TURN_AR, M1_cfg_cyc, J1_mstr_actv_lc);

--G1L645 is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_ad_IR_ce_D~7
--operation mode is normal

G1L645 = AMPP_FUNCTION(M1_ad_ir_ce_D_lc1, M1_TS_TURN_AR, M1_cfg_cyc, J1_mstr_actv_lc);


--ix2382_lc is ix2382_lc
--operation mode is normal

ix2382_lc = G1_cben_ir_address[3] & !G1_cben_ir_address[2] # !M1_lt_tsr[0] # !M1L133;

--A1L259 is ix2382_lc~0
--operation mode is normal

A1L259 = G1_cben_ir_address[3] & !G1_cben_ir_address[2] # !M1_lt_tsr[0] # !M1L133;


--E1_counter_cell[10] is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[10]
--operation mode is up_dn_cntr

E1_counter_cell[10]_lut_out = E1_counter_cell[10] $ E1L13;
E1_counter_cell[10] = DFFEA(E1_counter_cell[10]_lut_out, GLOBAL(pci_clk), , , , , );

--E1L33Q is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[10]~4
--operation mode is up_dn_cntr

E1L33Q = E1_counter_cell[10];

--E1L43 is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[10]~COUT
--operation mode is up_dn_cntr

E1L43 = CARRY(E1_counter_cell[10] & (E1L13));


--M1_ad_ir_ce_A_lc1 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|ad_ir_ce_A_lc1
--operation mode is normal

M1_ad_ir_ce_A_lc1 = AMPP_FUNCTION(M1_TS_IDLE_NOT, M1_adr_phase_lc1, M1_cfg_cyc);

--M1L221 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|ad_ir_ce_A_lc1~8
--operation mode is normal

M1L221 = AMPP_FUNCTION(M1_TS_IDLE_NOT, M1_adr_phase_lc1, M1_cfg_cyc);


--M1_ad_ir_ce_A_lc2 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|ad_ir_ce_A_lc2
--operation mode is normal

M1_ad_ir_ce_A_lc2 = AMPP_FUNCTION(M1_TS_TURN_AR, M1_LW_LXFR, M1_cfg_cyc, M1_TS_IDLE_NOT);

--M1L521 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|ad_ir_ce_A_lc2~8
--operation mode is normal

M1L521 = AMPP_FUNCTION(M1_TS_TURN_AR, M1_LW_LXFR, M1_cfg_cyc, M1_TS_IDLE_NOT);


--M1_lt_rdynR is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_rdynR
--operation mode is normal

M1_lt_rdynR = AMPP_FUNCTION(dpm_dec_reg_LT_RDY_n_pci, pci_rstn, GLOBAL(pci_clk));

--M1L173Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_rdynR~11
--operation mode is normal

M1L173Q = AMPP_FUNCTION(dpm_dec_reg_LT_RDY_n_pci, pci_rstn, GLOBAL(pci_clk));


--M1L31 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|$00129~0
--operation mode is normal

M1L31 = AMPP_FUNCTION(A1L5321, M1_lt_rdynR);

--M1L41 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|$00129~10
--operation mode is normal

M1L41 = AMPP_FUNCTION(A1L5321, M1_lt_rdynR);

--M1L51 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|$00129~11
--operation mode is normal

M1L51 = AMPP_FUNCTION(A1L5321, M1_lt_rdynR);


--M1_no_op_reg[2] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[2]
--operation mode is normal

M1_no_op_reg[2] = AMPP_FUNCTION(pci_rstn, GLOBAL(pci_clk));

--M1L324Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[2]~9
--operation mode is normal

M1L324Q = AMPP_FUNCTION(pci_rstn, GLOBAL(pci_clk));


--M1L01 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|$00127~0
--operation mode is normal

M1L01 = AMPP_FUNCTION(M1_no_op_reg[2], A1L5321);

--M1L11 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|$00127~10
--operation mode is normal

M1L11 = AMPP_FUNCTION(M1_no_op_reg[2], A1L5321);

--M1L21 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|$00127~11
--operation mode is normal

M1L21 = AMPP_FUNCTION(M1_no_op_reg[2], A1L5321);


--M1_LW_WAIT is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LW_WAIT
--operation mode is normal

M1_LW_WAIT = AMPP_FUNCTION(M1_LW_WAIT, dpm_dec_reg_LT_RDY_n_pci, pci_rstn, GLOBAL(pci_clk), M1L714);

--M1L814Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LW_WAIT~12
--operation mode is normal

M1L814Q = AMPP_FUNCTION(M1_LW_WAIT, dpm_dec_reg_LT_RDY_n_pci, pci_rstn, GLOBAL(pci_clk), M1L714);


--M1_lt_ack_R_r1_lc[7] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_ack_R_r1_lc[7]
--operation mode is normal

M1_lt_ack_R_r1_lc[7] = AMPP_FUNCTION(M1_lt_ack_R_r1_lc[6], M1_LW_WAIT, M1_lt_ack_R_r1_lc[4], M1_rd_backoff);

--M1L903 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_ack_R_r1_lc[7]~114
--operation mode is normal

M1L903 = AMPP_FUNCTION(M1_lt_ack_R_r1_lc[6], M1_LW_WAIT, M1_lt_ack_R_r1_lc[4], M1_rd_backoff);


--M1_LR_LXFR is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_LXFR
--operation mode is normal

M1_LR_LXFR = AMPP_FUNCTION(M1_LR_LXFR, M1_LR_LXFR_lc[5], M1L812, pci_rstn, GLOBAL(pci_clk), M1L012);

--M1L722Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_LXFR~18
--operation mode is normal

M1L722Q = AMPP_FUNCTION(M1_LR_LXFR, M1_LR_LXFR_lc[5], M1L812, pci_rstn, GLOBAL(pci_clk), M1L012);


--M1_lt_ack_R_r1_lc[9] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_ack_R_r1_lc[9]
--operation mode is normal

M1_lt_ack_R_r1_lc[9] = AMPP_FUNCTION(M1_LR_LXFR, M1_rd_backoff);

--M1L413 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_ack_R_r1_lc[9]~115
--operation mode is normal

M1L413 = AMPP_FUNCTION(M1_LR_LXFR, M1_rd_backoff);


--M1_LW_LXFR_carry[2] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LW_LXFR_carry[2]
--operation mode is arithmetic

M1_LW_LXFR_carry[2] = AMPP_FUNCTION();

--M1L004 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LW_LXFR_carry[2]~32
--operation mode is arithmetic

M1L004 = AMPP_FUNCTION();

--M1L104 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LW_LXFR_carry[2]~COUT
--operation mode is arithmetic

M1L104 = AMPP_FUNCTION(A1L5321, M1_LW_LXFR_lc[3], M1L893);


--M1_bar_hit_rst is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|bar_hit_rst
--operation mode is normal

M1_bar_hit_rst = AMPP_FUNCTION(K1_serr_or, M1_TS_TURN_AR, M1_TS_IDLE_NOT, M1_adr_phase_lc1);

--M1L341 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|bar_hit_rst~13
--operation mode is normal

M1L341 = AMPP_FUNCTION(K1_serr_or, M1_TS_TURN_AR, M1_TS_IDLE_NOT, M1_adr_phase_lc1);


--J1_dxfr_write_carry is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|dxfr_write_carry
--operation mode is arithmetic

J1_dxfr_write_carry = AMPP_FUNCTION();

--J1L561 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|dxfr_write_carry~11
--operation mode is arithmetic

J1L561 = AMPP_FUNCTION();

--J1L661 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|dxfr_write_carry~COUT
--operation mode is arithmetic

J1L661 = AMPP_FUNCTION(A1L5421, A1L7421);


--J1_no_op_reg[3] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|no_op_reg[3]
--operation mode is normal

J1_no_op_reg[3] = AMPP_FUNCTION(pci_rstn, GLOBAL(pci_clk));

--J1L075Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|no_op_reg[3]~18
--operation mode is normal

J1L075Q = AMPP_FUNCTION(pci_rstn, GLOBAL(pci_clk));


--J1_MW_LAST_r[3] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_LAST_r[3]
--operation mode is normal

J1_MW_LAST_r[3] = AMPP_FUNCTION(A1L5421, J1_MW_LAST, J1_devsel_toR, pci_rstn, GLOBAL(pci_clk), J1L74);

--J1L405Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_LAST_r[3]~21
--operation mode is normal

J1L405Q = AMPP_FUNCTION(A1L5421, J1_MW_LAST, J1_devsel_toR, pci_rstn, GLOBAL(pci_clk), J1L74);


--J1_MW_LAST_r[2] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_LAST_r[2]
--operation mode is normal

J1_MW_LAST_r[2] = AMPP_FUNCTION(J1_last_xfr, J1_MW_LAST_lc[3], pci_rstn, GLOBAL(pci_clk));

--J1L205Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_LAST_r[2]~22
--operation mode is normal

J1L205Q = AMPP_FUNCTION(J1_last_xfr, J1_MW_LAST_lc[3], pci_rstn, GLOBAL(pci_clk));


--J1_MW_LAST_r[1] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_LAST_r[1]
--operation mode is normal

J1_MW_LAST_r[1] = AMPP_FUNCTION(A1L5421, J1_MW_LAST_lc[1], J1_last_xfr, J1_MW_LAST_lc[2], pci_rstn, GLOBAL(pci_clk), J1L44);

--J1L005Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_LAST_r[1]~23
--operation mode is normal

J1L005Q = AMPP_FUNCTION(A1L5421, J1_MW_LAST_lc[1], J1_last_xfr, J1_MW_LAST_lc[2], pci_rstn, GLOBAL(pci_clk), J1L44);


--J1_MW_LAST is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_LAST
--operation mode is normal

J1_MW_LAST = AMPP_FUNCTION(J1_MW_LAST_r[3], J1_MW_LAST_r[2], J1_MW_LAST_r[1]);

--J1L605 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_LAST~36
--operation mode is normal

J1L605 = AMPP_FUNCTION(J1_MW_LAST_r[3], J1_MW_LAST_r[2], J1_MW_LAST_r[1]);


--E3_q[0] is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[0]
--operation mode is clrb_cntr

E3_q[0]_lut_out = (ix2252_lc $ E3_q[0]) & VCC;
E3_q[0] = DFFEA(E3_q[0]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E3L76Q is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[0]~24
--operation mode is clrb_cntr

E3L76Q = E3_q[0];

--E3L3 is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT
--operation mode is clrb_cntr

E3L3 = CARRY(E3_q[0]);


--A1L769 is ix2389~0
--operation mode is normal

A1L769 = (E9_q[0] & !ix2322_lc & (!ix2321_lc # !E3_q[0]) # !E9_q[0] & (!ix2321_lc # !E3_q[0])) & CASCADE(A1L468);

--A1L869 is ix2389~2
--operation mode is normal

A1L869 = (E9_q[0] & !ix2322_lc & (!ix2321_lc # !E3_q[0]) # !E9_q[0] & (!ix2321_lc # !E3_q[0])) & CASCADE(A1L468);

--A1L969 is ix2389~3
--operation mode is normal

A1L969 = (E9_q[0] & !ix2322_lc & (!ix2321_lc # !E3_q[0]) # !E9_q[0] & (!ix2321_lc # !E3_q[0])) & CASCADE(A1L468);


--ix2312_lc is ix2312_lc
--operation mode is normal

ix2312_lc = !M1_lt_adr[19] & M1_lt_adr[5] & !M1_lt_adr[4];

--A1L657 is ix2312_lc~0
--operation mode is normal

A1L657 = !M1_lt_adr[19] & M1_lt_adr[5] & !M1_lt_adr[4];

--A1L757 is ix2312~0
--operation mode is normal

A1L757 = !M1_lt_adr[19] & M1_lt_adr[5] & !M1_lt_adr[4];


--P1_ad_dat_out[0] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[0]
--operation mode is normal

P1_ad_dat_out[0] = AMPP_FUNCTION(R1_decR[2], P1L4, R1_decR[1], P1_cmd_reg[0], pci_rstn, GLOBAL(pci_clk));

--P1L22Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[0]~1
--operation mode is normal

P1L22Q = AMPP_FUNCTION(R1_decR[2], P1L4, R1_decR[1], P1_cmd_reg[0], pci_rstn, GLOBAL(pci_clk));


--G1_ad_ce_nc is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ce_nc
--operation mode is normal

G1_ad_ce_nc = AMPP_FUNCTION(G1_mstr_ADOR_ena, G1_trg_ADOR_ena);

--G1L99 is pci_contr:pci|pci_mt32:pci_mt32_inst|ad_ce_nc~8
--operation mode is normal

G1L99 = AMPP_FUNCTION(G1_mstr_ADOR_ena, G1_trg_ADOR_ena);


--M1_TS_TURN_AR_d_lc1 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|TS_TURN_AR_d_lc1
--operation mode is normal

M1_TS_TURN_AR_d_lc1 = AMPP_FUNCTION(M1_TS_DXFR, M1_trdy_OR_NOT);

--M1L245 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|TS_TURN_AR_d_lc1~13
--operation mode is normal

M1L245 = AMPP_FUNCTION(M1_TS_DXFR, M1_trdy_OR_NOT);


--J1_ad_oer_lc2c is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|ad_oer_lc2c
--operation mode is normal

J1_ad_oer_lc2c = AMPP_FUNCTION(J1_wr_rdn, J1_MS_ADR, J1_MS_ADR2);

--J1L311 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|ad_oer_lc2c~23
--operation mode is normal

J1L311 = AMPP_FUNCTION(J1_wr_rdn, J1_MS_ADR, J1_MS_ADR2);


--J1_ad_oer_lc2b is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|ad_oer_lc2b
--operation mode is normal

J1_ad_oer_lc2b = AMPP_FUNCTION(J1_MS_DXFR, J1_wr_rdn, J1_irdy_or_not, J1_frame_or_not);

--J1L011 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|ad_oer_lc2b~36
--operation mode is normal

J1L011 = AMPP_FUNCTION(J1_MS_DXFR, J1_wr_rdn, J1_irdy_or_not, J1_frame_or_not);


--J1_$00167 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|$00167
--operation mode is normal

J1_$00167 = AMPP_FUNCTION(J1_park, J1_l_req_vld, J1_MS_IDLE_not);

--J1L32 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|$00167~30
--operation mode is normal

J1L32 = AMPP_FUNCTION(J1_park, J1_l_req_vld, J1_MS_IDLE_not);


--J1_idle_reg_d_carry is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|idle_reg_d_carry
--operation mode is arithmetic

J1_idle_reg_d_carry = AMPP_FUNCTION();

--J1L712 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|idle_reg_d_carry~18
--operation mode is arithmetic

J1L712 = AMPP_FUNCTION();

--J1L812 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|idle_reg_d_carry~COUT
--operation mode is arithmetic

J1L812 = AMPP_FUNCTION(A1L5321, P1_cmd_reg[2]);


--J1_devsel_toR is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|devsel_toR
--operation mode is normal

J1_devsel_toR = AMPP_FUNCTION(A1L8221, J1_MS_DXFR, J1_devsel_toR_lc1, pci_rstn, GLOBAL(pci_clk));

--J1L061Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|devsel_toR~25
--operation mode is normal

J1L061Q = AMPP_FUNCTION(A1L8221, J1_MS_DXFR, J1_devsel_toR_lc1, pci_rstn, GLOBAL(pci_clk));


--E3_q[1] is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[1]
--operation mode is clrb_cntr

E3_q[1]_lut_out = (E3_q[1] $ (ix2252_lc & E3L3)) & VCC;
E3_q[1] = DFFEA(E3_q[1]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E3L96Q is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[1]~25
--operation mode is clrb_cntr

E3L96Q = E3_q[1];

--E3L5 is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT
--operation mode is clrb_cntr

E3L5 = CARRY(E3_q[1] & (E3L3));


--A1L379 is ix2391~0
--operation mode is normal

A1L379 = (E9_q[1] & !ix2322_lc & (!ix2321_lc # !E3_q[1]) # !E9_q[1] & (!ix2321_lc # !E3_q[1])) & CASCADE(A1L168);

--A1L479 is ix2391~2
--operation mode is normal

A1L479 = (E9_q[1] & !ix2322_lc & (!ix2321_lc # !E3_q[1]) # !E9_q[1] & (!ix2321_lc # !E3_q[1])) & CASCADE(A1L168);

--A1L579 is ix2391~3
--operation mode is normal

A1L579 = (E9_q[1] & !ix2322_lc & (!ix2321_lc # !E3_q[1]) # !E9_q[1] & (!ix2321_lc # !E3_q[1])) & CASCADE(A1L168);


--P1_ad_dat_out[1] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[1]
--operation mode is normal

P1_ad_dat_out[1] = AMPP_FUNCTION(R1_decR[0], P1L3, R1_decR[1], P1_cmd_reg[1], pci_rstn, GLOBAL(pci_clk));

--P1L42Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[1]~2
--operation mode is normal

P1L42Q = AMPP_FUNCTION(R1_decR[0], P1L3, R1_decR[1], P1_cmd_reg[1], pci_rstn, GLOBAL(pci_clk));


--E3_q[2] is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[2]
--operation mode is clrb_cntr

E3_q[2]_lut_out = (E3_q[2] $ (ix2252_lc & E3L5)) & VCC;
E3_q[2] = DFFEA(E3_q[2]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E3L17Q is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[2]~26
--operation mode is clrb_cntr

E3L17Q = E3_q[2];

--E3L7 is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT
--operation mode is clrb_cntr

E3L7 = CARRY(E3_q[2] & (E3L5));


--A1L979 is ix2393~0
--operation mode is normal

A1L979 = (E9_q[2] & !ix2322_lc & (!ix2321_lc # !E3_q[2]) # !E9_q[2] & (!ix2321_lc # !E3_q[2])) & CASCADE(A1L858);

--A1L089 is ix2393~2
--operation mode is normal

A1L089 = (E9_q[2] & !ix2322_lc & (!ix2321_lc # !E3_q[2]) # !E9_q[2] & (!ix2321_lc # !E3_q[2])) & CASCADE(A1L858);

--A1L189 is ix2393~3
--operation mode is normal

A1L189 = (E9_q[2] & !ix2322_lc & (!ix2321_lc # !E3_q[2]) # !E9_q[2] & (!ix2321_lc # !E3_q[2])) & CASCADE(A1L858);


--P1_ad_dat_out[2] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[2]
--operation mode is normal

P1_ad_dat_out[2] = AMPP_FUNCTION(R1_decR[1], R1_decR[3], P1_cache_line[2], P1_cmd_reg[2], pci_rstn, GLOBAL(pci_clk));

--P1L62Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[2]~3
--operation mode is normal

P1L62Q = AMPP_FUNCTION(R1_decR[1], R1_decR[3], P1_cache_line[2], P1_cmd_reg[2], pci_rstn, GLOBAL(pci_clk));


--E3_q[3] is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[3]
--operation mode is clrb_cntr

E3_q[3]_lut_out = (E3_q[3] $ (ix2252_lc & E3L7)) & VCC;
E3_q[3] = DFFEA(E3_q[3]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E3L37Q is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[3]~27
--operation mode is clrb_cntr

E3L37Q = E3_q[3];

--E3L9 is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT
--operation mode is clrb_cntr

E3L9 = CARRY(E3_q[3] & (E3L7));


--A1L589 is ix2395~0
--operation mode is normal

A1L589 = (E9_q[3] & !ix2322_lc & (!ix2321_lc # !E3_q[3]) # !E9_q[3] & (!ix2321_lc # !E3_q[3])) & CASCADE(A1L558);

--A1L689 is ix2395~2
--operation mode is normal

A1L689 = (E9_q[3] & !ix2322_lc & (!ix2321_lc # !E3_q[3]) # !E9_q[3] & (!ix2321_lc # !E3_q[3])) & CASCADE(A1L558);

--A1L789 is ix2395~3
--operation mode is normal

A1L789 = (E9_q[3] & !ix2322_lc & (!ix2321_lc # !E3_q[3]) # !E9_q[3] & (!ix2321_lc # !E3_q[3])) & CASCADE(A1L558);


--P1_ad_dat_out[3] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[3]
--operation mode is normal

P1_ad_dat_out[3] = AMPP_FUNCTION(R1_decR[3], P1_cache_line[3], pci_rstn, GLOBAL(pci_clk));

--P1L82Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[3]~4
--operation mode is normal

P1L82Q = AMPP_FUNCTION(R1_decR[3], P1_cache_line[3], pci_rstn, GLOBAL(pci_clk));


--E3_q[4] is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[4]
--operation mode is clrb_cntr

E3_q[4]_lut_out = (E3_q[4] $ (ix2252_lc & E3L9)) & VCC;
E3_q[4] = DFFEA(E3_q[4]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E3L57Q is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[4]~28
--operation mode is clrb_cntr

E3L57Q = E3_q[4];

--E3L11 is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[4]~COUT
--operation mode is clrb_cntr

E3L11 = CARRY(E3_q[4] & (E3L9));


--A1L199 is ix2397~0
--operation mode is normal

A1L199 = (E9_q[4] & !ix2322_lc & (!ix2321_lc # !E3_q[4]) # !E9_q[4] & (!ix2321_lc # !E3_q[4])) & CASCADE(A1L258);

--A1L299 is ix2397~2
--operation mode is normal

A1L299 = (E9_q[4] & !ix2322_lc & (!ix2321_lc # !E3_q[4]) # !E9_q[4] & (!ix2321_lc # !E3_q[4])) & CASCADE(A1L258);

--A1L399 is ix2397~3
--operation mode is normal

A1L399 = (E9_q[4] & !ix2322_lc & (!ix2321_lc # !E3_q[4]) # !E9_q[4] & (!ix2321_lc # !E3_q[4])) & CASCADE(A1L258);


--P1_ad_dat_out[4] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[4]
--operation mode is normal

P1_ad_dat_out[4] = AMPP_FUNCTION(R1_decR[0], P1L2, R1_decR[1], P1_cmd_reg[4], pci_rstn, GLOBAL(pci_clk));

--P1L03Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[4]~5
--operation mode is normal

P1L03Q = AMPP_FUNCTION(R1_decR[0], P1L2, R1_decR[1], P1_cmd_reg[4], pci_rstn, GLOBAL(pci_clk));


--E3_q[5] is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[5]
--operation mode is clrb_cntr

E3_q[5]_lut_out = (E3_q[5] $ (ix2252_lc & E3L11)) & VCC;
E3_q[5] = DFFEA(E3_q[5]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E3L77Q is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[5]~29
--operation mode is clrb_cntr

E3L77Q = E3_q[5];

--E3L31 is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[5]~COUT
--operation mode is clrb_cntr

E3L31 = CARRY(E3_q[5] & (E3L11));


--A1L799 is ix2399~0
--operation mode is normal

A1L799 = (E9_q[5] & !ix2322_lc & (!ix2321_lc # !E3_q[5]) # !E9_q[5] & (!ix2321_lc # !E3_q[5])) & CASCADE(A1L948);

--A1L899 is ix2399~2
--operation mode is normal

A1L899 = (E9_q[5] & !ix2322_lc & (!ix2321_lc # !E3_q[5]) # !E9_q[5] & (!ix2321_lc # !E3_q[5])) & CASCADE(A1L948);

--A1L999 is ix2399~3
--operation mode is normal

A1L999 = (E9_q[5] & !ix2322_lc & (!ix2321_lc # !E3_q[5]) # !E9_q[5] & (!ix2321_lc # !E3_q[5])) & CASCADE(A1L948);


--P1_ad_dat_out[5] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[5]
--operation mode is normal

P1_ad_dat_out[5] = AMPP_FUNCTION(R1_decR[0], R1_decR[3], P1_cache_line[5], pci_rstn, GLOBAL(pci_clk));

--P1L23Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[5]~6
--operation mode is normal

P1L23Q = AMPP_FUNCTION(R1_decR[0], R1_decR[3], P1_cache_line[5], pci_rstn, GLOBAL(pci_clk));


--E3_q[6] is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[6]
--operation mode is clrb_cntr

E3_q[6]_lut_out = (E3_q[6] $ (ix2252_lc & E3L31)) & VCC;
E3_q[6] = DFFEA(E3_q[6]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E3L97Q is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[6]~30
--operation mode is clrb_cntr

E3L97Q = E3_q[6];

--E3L51 is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[6]~COUT
--operation mode is clrb_cntr

E3L51 = CARRY(E3_q[6] & (E3L31));


--A1L3001 is ix2401~0
--operation mode is normal

A1L3001 = (E9_q[6] & !ix2322_lc & (!ix2321_lc # !E3_q[6]) # !E9_q[6] & (!ix2321_lc # !E3_q[6])) & CASCADE(A1L648);

--A1L4001 is ix2401~2
--operation mode is normal

A1L4001 = (E9_q[6] & !ix2322_lc & (!ix2321_lc # !E3_q[6]) # !E9_q[6] & (!ix2321_lc # !E3_q[6])) & CASCADE(A1L648);

--A1L5001 is ix2401~3
--operation mode is normal

A1L5001 = (E9_q[6] & !ix2322_lc & (!ix2321_lc # !E3_q[6]) # !E9_q[6] & (!ix2321_lc # !E3_q[6])) & CASCADE(A1L648);


--P1_ad_dat_out[6] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[6]
--operation mode is normal

P1_ad_dat_out[6] = AMPP_FUNCTION(R1_decR[0], P1L1, P1_cmd_reg[6], R1_decR[1], pci_rstn, GLOBAL(pci_clk));

--P1L43Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[6]~7
--operation mode is normal

P1L43Q = AMPP_FUNCTION(R1_decR[0], P1L1, P1_cmd_reg[6], R1_decR[1], pci_rstn, GLOBAL(pci_clk));


--E3_q[7] is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[7]
--operation mode is clrb_cntr

E3_q[7]_lut_out = (E3_q[7] $ (ix2252_lc & E3L51)) & VCC;
E3_q[7] = DFFEA(E3_q[7]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E3L18Q is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|q[7]~31
--operation mode is clrb_cntr

E3L18Q = E3_q[7];

--E3L71 is lpm_counter:dpm_ni2f_des_valid_data_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[7]~COUT
--operation mode is clrb_cntr

E3L71 = CARRY(E3_q[7] & (E3L51));


--A1L9001 is ix2403~0
--operation mode is normal

A1L9001 = (E9_q[7] & !ix2322_lc & (!ix2321_lc # !E3_q[7]) # !E9_q[7] & (!ix2321_lc # !E3_q[7])) & CASCADE(A1L348);

--A1L0101 is ix2403~2
--operation mode is normal

A1L0101 = (E9_q[7] & !ix2322_lc & (!ix2321_lc # !E3_q[7]) # !E9_q[7] & (!ix2321_lc # !E3_q[7])) & CASCADE(A1L348);

--A1L1101 is ix2403~3
--operation mode is normal

A1L1101 = (E9_q[7] & !ix2322_lc & (!ix2321_lc # !E3_q[7]) # !E9_q[7] & (!ix2321_lc # !E3_q[7])) & CASCADE(A1L348);


--P1_ad_dat_out[7] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[7]
--operation mode is normal

P1_ad_dat_out[7] = AMPP_FUNCTION(R1_decR[3], P1_cache_line[7], pci_rstn, GLOBAL(pci_clk));

--P1L63Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[7]~8
--operation mode is normal

P1L63Q = AMPP_FUNCTION(R1_decR[3], P1_cache_line[7], pci_rstn, GLOBAL(pci_clk));


--dpm_dec_reg_rdata_LED_8 is dpm_dec_reg_rdata_LED_8
--operation mode is normal

dpm_dec_reg_rdata_LED_8_lut_out = A1L868 & G1_low_ad_IR_data[8] # !A1L868 & (dpm_dec_reg_rdata_LED_8);
dpm_dec_reg_rdata_LED_8 = DFFEA(dpm_dec_reg_rdata_LED_8_lut_out, GLOBAL(pci_clk), pci_rstn, , , , );

--A1L75Q is dpm_dec_reg_rdata_LED_8~0
--operation mode is normal

A1L75Q = dpm_dec_reg_rdata_LED_8;


--ix2406 is ix2406
--operation mode is normal

ix2406 = M1_lt_adr[19] # M1_lt_adr[5] # !dpm_dec_reg_rdata_LED_8 # !M1_lt_adr[4];

--A1L9101 is ix2406~1
--operation mode is normal

A1L9101 = M1_lt_adr[19] # M1_lt_adr[5] # !dpm_dec_reg_rdata_LED_8 # !M1_lt_adr[4];

--A1L0201 is ix2406~2
--operation mode is normal

A1L0201 = M1_lt_adr[19] # M1_lt_adr[5] # !dpm_dec_reg_rdata_LED_8 # !M1_lt_adr[4];


--dpm_ni2f_reg_sram_qL_8 is dpm_ni2f_reg_sram_qL_8
--operation mode is normal

dpm_ni2f_reg_sram_qL_8_lut_out = dpm_ni2f_reg_sm_8 & (SRAM_IO_8) # !dpm_ni2f_reg_sm_8 & dpm_ni2f_reg_sram_qL_8;
dpm_ni2f_reg_sram_qL_8 = DFFEA(dpm_ni2f_reg_sram_qL_8_lut_out, lcst, , , , , );

--A1L394Q is dpm_ni2f_reg_sram_qL_8~0
--operation mode is normal

A1L394Q = dpm_ni2f_reg_sram_qL_8;


--E2_q[8] is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[8]
--operation mode is clrb_cntr

E2_q[8]_lut_out = (E2_q[8] $ (ix2253_lc & E2L71)) & VCC;
E2_q[8] = DFFEA(E2_q[8]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E2L38Q is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[8]~8
--operation mode is clrb_cntr

E2L38Q = E2_q[8];

--E2L91 is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[8]~COUT
--operation mode is clrb_cntr

E2L91 = CARRY(E2_q[8] & (E2L71));


--A1L5101 is ix2405~0
--operation mode is normal

A1L5101 = (dpm_ni2f_reg_sram_qL_8 & !M1_lt_adr[19] & (!A1L877 # !E2_q[8]) # !dpm_ni2f_reg_sram_qL_8 & (!A1L877 # !E2_q[8])) & CASCADE(A1L0201);

--A1L6101 is ix2405~2
--operation mode is normal

A1L6101 = (dpm_ni2f_reg_sram_qL_8 & !M1_lt_adr[19] & (!A1L877 # !E2_q[8]) # !dpm_ni2f_reg_sram_qL_8 & (!A1L877 # !E2_q[8])) & CASCADE(A1L0201);

--A1L7101 is ix2405~3
--operation mode is normal

A1L7101 = (dpm_ni2f_reg_sram_qL_8 & !M1_lt_adr[19] & (!A1L877 # !E2_q[8]) # !dpm_ni2f_reg_sram_qL_8 & (!A1L877 # !E2_q[8])) & CASCADE(A1L0201);


--ix2311_lc is ix2311_lc
--operation mode is normal

ix2311_lc = M1_lt_adr[5] & M1_lt_adr[4];

--A1L257 is ix2311_lc~0
--operation mode is normal

A1L257 = M1_lt_adr[5] & M1_lt_adr[4];

--A1L357 is ix2311~0
--operation mode is normal

A1L357 = M1_lt_adr[5] & M1_lt_adr[4];


--ix2433 is ix2433
--operation mode is normal

ix2433 = !M1_lt_adr[19] & M1_lt_adr[3] & !M1_lt_adr[2];

--A1L7901 is ix2433~0
--operation mode is normal

A1L7901 = !M1_lt_adr[19] & M1_lt_adr[3] & !M1_lt_adr[2];


--ix2321_lc is ix2321_lc
--operation mode is normal

ix2321_lc = ix2311_lc & ix2433;

--A1L287 is ix2321_lc~0
--operation mode is normal

A1L287 = ix2311_lc & ix2433;


--ix2322_lc is ix2322_lc
--operation mode is normal

ix2322_lc = !M1_lt_adr[19] & M1_lt_adr[5] & M1_lt_adr[4] & !M1_lt_adr[3];

--A1L587 is ix2322_lc~0
--operation mode is normal

A1L587 = !M1_lt_adr[19] & M1_lt_adr[5] & M1_lt_adr[4] & !M1_lt_adr[3];


--P1_ad_dat_out[8] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[8]
--operation mode is normal

P1_ad_dat_out[8] = AMPP_FUNCTION(R1_decR[0], P1_cmd_reg[8], R1_decR[1], pci_rstn, GLOBAL(pci_clk));

--P1L83Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[8]~9
--operation mode is normal

P1L83Q = AMPP_FUNCTION(R1_decR[0], P1_cmd_reg[8], R1_decR[1], pci_rstn, GLOBAL(pci_clk));


--dpm_dec_reg_rdata_LED_9 is dpm_dec_reg_rdata_LED_9
--operation mode is normal

dpm_dec_reg_rdata_LED_9_lut_out = A1L868 & G1_low_ad_IR_data[9] # !A1L868 & (dpm_dec_reg_rdata_LED_9);
dpm_dec_reg_rdata_LED_9 = DFFEA(dpm_dec_reg_rdata_LED_9_lut_out, GLOBAL(pci_clk), pci_rstn, , , , );

--A1L95Q is dpm_dec_reg_rdata_LED_9~0
--operation mode is normal

A1L95Q = dpm_dec_reg_rdata_LED_9;


--ix2408 is ix2408
--operation mode is normal

ix2408 = M1_lt_adr[19] # M1_lt_adr[5] # !dpm_dec_reg_rdata_LED_9 # !M1_lt_adr[4];

--A1L5201 is ix2408~1
--operation mode is normal

A1L5201 = M1_lt_adr[19] # M1_lt_adr[5] # !dpm_dec_reg_rdata_LED_9 # !M1_lt_adr[4];

--A1L6201 is ix2408~2
--operation mode is normal

A1L6201 = M1_lt_adr[19] # M1_lt_adr[5] # !dpm_dec_reg_rdata_LED_9 # !M1_lt_adr[4];


--dpm_ni2f_reg_sram_qL_9 is dpm_ni2f_reg_sram_qL_9
--operation mode is normal

dpm_ni2f_reg_sram_qL_9_lut_out = dpm_ni2f_reg_sm_8 & (SRAM_IO_9) # !dpm_ni2f_reg_sm_8 & dpm_ni2f_reg_sram_qL_9;
dpm_ni2f_reg_sram_qL_9 = DFFEA(dpm_ni2f_reg_sram_qL_9_lut_out, lcst, , , , , );

--A1L594Q is dpm_ni2f_reg_sram_qL_9~0
--operation mode is normal

A1L594Q = dpm_ni2f_reg_sram_qL_9;


--E2_q[9] is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[9]
--operation mode is clrb_cntr

E2_q[9]_lut_out = (E2_q[9] $ (ix2253_lc & E2L91)) & VCC;
E2_q[9] = DFFEA(E2_q[9]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E2L58Q is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[9]~9
--operation mode is clrb_cntr

E2L58Q = E2_q[9];

--E2L12 is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[9]~COUT
--operation mode is clrb_cntr

E2L12 = CARRY(E2_q[9] & (E2L91));


--A1L1201 is ix2407~0
--operation mode is normal

A1L1201 = (dpm_ni2f_reg_sram_qL_9 & !M1_lt_adr[19] & (!A1L877 # !E2_q[9]) # !dpm_ni2f_reg_sram_qL_9 & (!A1L877 # !E2_q[9])) & CASCADE(A1L6201);

--A1L2201 is ix2407~2
--operation mode is normal

A1L2201 = (dpm_ni2f_reg_sram_qL_9 & !M1_lt_adr[19] & (!A1L877 # !E2_q[9]) # !dpm_ni2f_reg_sram_qL_9 & (!A1L877 # !E2_q[9])) & CASCADE(A1L6201);

--A1L3201 is ix2407~3
--operation mode is normal

A1L3201 = (dpm_ni2f_reg_sram_qL_9 & !M1_lt_adr[19] & (!A1L877 # !E2_q[9]) # !dpm_ni2f_reg_sram_qL_9 & (!A1L877 # !E2_q[9])) & CASCADE(A1L6201);


--dpm_ni2f_reg_sram_qL_10 is dpm_ni2f_reg_sram_qL_10
--operation mode is normal

dpm_ni2f_reg_sram_qL_10_lut_out = dpm_ni2f_reg_sm_8 & (SRAM_IO_10) # !dpm_ni2f_reg_sm_8 & dpm_ni2f_reg_sram_qL_10;
dpm_ni2f_reg_sram_qL_10 = DFFEA(dpm_ni2f_reg_sram_qL_10_lut_out, lcst, , , , , );

--A1L794Q is dpm_ni2f_reg_sram_qL_10~0
--operation mode is normal

A1L794Q = dpm_ni2f_reg_sram_qL_10;


--ix2409 is ix2409
--operation mode is normal

ix2409 = !dpm_ni2f_reg_sram_qL_10 # !M1_lt_adr[19];

--A1L8201 is ix2409~1
--operation mode is normal

A1L8201 = !dpm_ni2f_reg_sram_qL_10 # !M1_lt_adr[19];

--A1L9201 is ix2409~2
--operation mode is normal

A1L9201 = !dpm_ni2f_reg_sram_qL_10 # !M1_lt_adr[19];


--E2_q[10] is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[10]
--operation mode is clrb_cntr

E2_q[10]_lut_out = (E2_q[10] $ (ix2253_lc & E2L12)) & VCC;
E2_q[10] = DFFEA(E2_q[10]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E2L78Q is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[10]~10
--operation mode is clrb_cntr

E2L78Q = E2_q[10];

--E2L32 is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[10]~COUT
--operation mode is clrb_cntr

E2L32 = CARRY(E2_q[10] & (E2L12));


--A1L838 is ix2340~0
--operation mode is normal

A1L838 = (!ix2431_lc # !ix2311_lc # !E2_q[10] # !M1_lt_adr[2]) & CASCADE(A1L9201);

--A1L938 is ix2340~2
--operation mode is normal

A1L938 = (!ix2431_lc # !ix2311_lc # !E2_q[10] # !M1_lt_adr[2]) & CASCADE(A1L9201);

--A1L048 is ix2340~3
--operation mode is normal

A1L048 = (!ix2431_lc # !ix2311_lc # !E2_q[10] # !M1_lt_adr[2]) & CASCADE(A1L9201);


--dpm_ni2f_reg_sram_qL_11 is dpm_ni2f_reg_sram_qL_11
--operation mode is normal

dpm_ni2f_reg_sram_qL_11_lut_out = dpm_ni2f_reg_sm_8 & (SRAM_IO_11) # !dpm_ni2f_reg_sm_8 & dpm_ni2f_reg_sram_qL_11;
dpm_ni2f_reg_sram_qL_11 = DFFEA(dpm_ni2f_reg_sram_qL_11_lut_out, lcst, , , , , );

--A1L994Q is dpm_ni2f_reg_sram_qL_11~0
--operation mode is normal

A1L994Q = dpm_ni2f_reg_sram_qL_11;


--ix2410 is ix2410
--operation mode is normal

ix2410 = !dpm_ni2f_reg_sram_qL_11 # !M1_lt_adr[19];

--A1L1301 is ix2410~1
--operation mode is normal

A1L1301 = !dpm_ni2f_reg_sram_qL_11 # !M1_lt_adr[19];

--A1L2301 is ix2410~2
--operation mode is normal

A1L2301 = !dpm_ni2f_reg_sram_qL_11 # !M1_lt_adr[19];


--E2_q[11] is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[11]
--operation mode is clrb_cntr

E2_q[11]_lut_out = (E2_q[11] $ (ix2253_lc & E2L32)) & VCC;
E2_q[11] = DFFEA(E2_q[11]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E2L98Q is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[11]~11
--operation mode is clrb_cntr

E2L98Q = E2_q[11];

--E2L52 is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[11]~COUT
--operation mode is clrb_cntr

E2L52 = CARRY(E2_q[11] & (E2L32));


--A1L538 is ix2339~0
--operation mode is normal

A1L538 = (!ix2431_lc # !ix2311_lc # !E2_q[11] # !M1_lt_adr[2]) & CASCADE(A1L2301);

--A1L638 is ix2339~2
--operation mode is normal

A1L638 = (!ix2431_lc # !ix2311_lc # !E2_q[11] # !M1_lt_adr[2]) & CASCADE(A1L2301);

--A1L738 is ix2339~3
--operation mode is normal

A1L738 = (!ix2431_lc # !ix2311_lc # !E2_q[11] # !M1_lt_adr[2]) & CASCADE(A1L2301);


--P1_ad_dat_out[11] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[11]
--operation mode is normal

P1_ad_dat_out[11] = AMPP_FUNCTION(R1_decR[3], P1_lat_tmr_reg[0], pci_rstn, GLOBAL(pci_clk));

--P1L04Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[11]~10
--operation mode is normal

P1L04Q = AMPP_FUNCTION(R1_decR[3], P1_lat_tmr_reg[0], pci_rstn, GLOBAL(pci_clk));


--dpm_ni2f_reg_sram_qL_12 is dpm_ni2f_reg_sram_qL_12
--operation mode is normal

dpm_ni2f_reg_sram_qL_12_lut_out = dpm_ni2f_reg_sm_8 & (SRAM_IO_12) # !dpm_ni2f_reg_sm_8 & dpm_ni2f_reg_sram_qL_12;
dpm_ni2f_reg_sram_qL_12 = DFFEA(dpm_ni2f_reg_sram_qL_12_lut_out, lcst, , , , , );

--A1L105Q is dpm_ni2f_reg_sram_qL_12~0
--operation mode is normal

A1L105Q = dpm_ni2f_reg_sram_qL_12;


--ix2411 is ix2411
--operation mode is normal

ix2411 = !dpm_ni2f_reg_sram_qL_12 # !M1_lt_adr[19];

--A1L4301 is ix2411~1
--operation mode is normal

A1L4301 = !dpm_ni2f_reg_sram_qL_12 # !M1_lt_adr[19];

--A1L5301 is ix2411~2
--operation mode is normal

A1L5301 = !dpm_ni2f_reg_sram_qL_12 # !M1_lt_adr[19];


--E2_q[12] is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[12]
--operation mode is clrb_cntr

E2_q[12]_lut_out = (E2_q[12] $ (ix2253_lc & E2L52)) & VCC;
E2_q[12] = DFFEA(E2_q[12]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E2L19Q is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[12]~12
--operation mode is clrb_cntr

E2L19Q = E2_q[12];

--E2L72 is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[12]~COUT
--operation mode is clrb_cntr

E2L72 = CARRY(E2_q[12] & (E2L52));


--A1L238 is ix2338~0
--operation mode is normal

A1L238 = (!ix2431_lc # !ix2311_lc # !E2_q[12] # !M1_lt_adr[2]) & CASCADE(A1L5301);

--A1L338 is ix2338~2
--operation mode is normal

A1L338 = (!ix2431_lc # !ix2311_lc # !E2_q[12] # !M1_lt_adr[2]) & CASCADE(A1L5301);

--A1L438 is ix2338~3
--operation mode is normal

A1L438 = (!ix2431_lc # !ix2311_lc # !E2_q[12] # !M1_lt_adr[2]) & CASCADE(A1L5301);


--P1_ad_dat_out[12] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[12]
--operation mode is normal

P1_ad_dat_out[12] = AMPP_FUNCTION(R1_decR[0], R1_decR[3], P1_lat_tmr_reg[1], pci_rstn, GLOBAL(pci_clk));

--P1L24Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[12]~11
--operation mode is normal

P1L24Q = AMPP_FUNCTION(R1_decR[0], R1_decR[3], P1_lat_tmr_reg[1], pci_rstn, GLOBAL(pci_clk));


--dpm_ni2f_reg_sram_qL_13 is dpm_ni2f_reg_sram_qL_13
--operation mode is normal

dpm_ni2f_reg_sram_qL_13_lut_out = dpm_ni2f_reg_sm_8 & (SRAM_IO_13) # !dpm_ni2f_reg_sm_8 & dpm_ni2f_reg_sram_qL_13;
dpm_ni2f_reg_sram_qL_13 = DFFEA(dpm_ni2f_reg_sram_qL_13_lut_out, lcst, , , , , );

--A1L305Q is dpm_ni2f_reg_sram_qL_13~0
--operation mode is normal

A1L305Q = dpm_ni2f_reg_sram_qL_13;


--ix2412 is ix2412
--operation mode is normal

ix2412 = !dpm_ni2f_reg_sram_qL_13 # !M1_lt_adr[19];

--A1L7301 is ix2412~1
--operation mode is normal

A1L7301 = !dpm_ni2f_reg_sram_qL_13 # !M1_lt_adr[19];

--A1L8301 is ix2412~2
--operation mode is normal

A1L8301 = !dpm_ni2f_reg_sram_qL_13 # !M1_lt_adr[19];


--E2_q[13] is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[13]
--operation mode is clrb_cntr

E2_q[13]_lut_out = (E2_q[13] $ (ix2253_lc & E2L72)) & VCC;
E2_q[13] = DFFEA(E2_q[13]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E2L39Q is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[13]~13
--operation mode is clrb_cntr

E2L39Q = E2_q[13];

--E2L92 is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[13]~COUT
--operation mode is clrb_cntr

E2L92 = CARRY(E2_q[13] & (E2L72));


--A1L928 is ix2337~0
--operation mode is normal

A1L928 = (!ix2431_lc # !ix2311_lc # !E2_q[13] # !M1_lt_adr[2]) & CASCADE(A1L8301);

--A1L038 is ix2337~2
--operation mode is normal

A1L038 = (!ix2431_lc # !ix2311_lc # !E2_q[13] # !M1_lt_adr[2]) & CASCADE(A1L8301);

--A1L138 is ix2337~3
--operation mode is normal

A1L138 = (!ix2431_lc # !ix2311_lc # !E2_q[13] # !M1_lt_adr[2]) & CASCADE(A1L8301);


--P1_ad_dat_out[13] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[13]
--operation mode is normal

P1_ad_dat_out[13] = AMPP_FUNCTION(R1_decR[3], P1_lat_tmr_reg[2], pci_rstn, GLOBAL(pci_clk));

--P1L44Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[13]~12
--operation mode is normal

P1L44Q = AMPP_FUNCTION(R1_decR[3], P1_lat_tmr_reg[2], pci_rstn, GLOBAL(pci_clk));


--dpm_ni2f_reg_sram_qL_14 is dpm_ni2f_reg_sram_qL_14
--operation mode is normal

dpm_ni2f_reg_sram_qL_14_lut_out = dpm_ni2f_reg_sm_8 & (SRAM_IO_14) # !dpm_ni2f_reg_sm_8 & dpm_ni2f_reg_sram_qL_14;
dpm_ni2f_reg_sram_qL_14 = DFFEA(dpm_ni2f_reg_sram_qL_14_lut_out, lcst, , , , , );

--A1L505Q is dpm_ni2f_reg_sram_qL_14~0
--operation mode is normal

A1L505Q = dpm_ni2f_reg_sram_qL_14;


--ix2413 is ix2413
--operation mode is normal

ix2413 = !dpm_ni2f_reg_sram_qL_14 # !M1_lt_adr[19];

--A1L0401 is ix2413~1
--operation mode is normal

A1L0401 = !dpm_ni2f_reg_sram_qL_14 # !M1_lt_adr[19];

--A1L1401 is ix2413~2
--operation mode is normal

A1L1401 = !dpm_ni2f_reg_sram_qL_14 # !M1_lt_adr[19];


--E2_q[14] is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[14]
--operation mode is clrb_cntr

E2_q[14]_lut_out = (E2_q[14] $ (ix2253_lc & E2L92)) & VCC;
E2_q[14] = DFFEA(E2_q[14]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E2L59Q is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[14]~14
--operation mode is clrb_cntr

E2L59Q = E2_q[14];

--E2L13 is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[14]~COUT
--operation mode is clrb_cntr

E2L13 = CARRY(E2_q[14] & (E2L92));


--A1L628 is ix2336~0
--operation mode is normal

A1L628 = (!ix2431_lc # !ix2311_lc # !E2_q[14] # !M1_lt_adr[2]) & CASCADE(A1L1401);

--A1L728 is ix2336~2
--operation mode is normal

A1L728 = (!ix2431_lc # !ix2311_lc # !E2_q[14] # !M1_lt_adr[2]) & CASCADE(A1L1401);

--A1L828 is ix2336~3
--operation mode is normal

A1L828 = (!ix2431_lc # !ix2311_lc # !E2_q[14] # !M1_lt_adr[2]) & CASCADE(A1L1401);


--P1_ad_dat_out[14] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[14]
--operation mode is normal

P1_ad_dat_out[14] = AMPP_FUNCTION(R1_decR[3], P1_lat_tmr_reg[3], pci_rstn, GLOBAL(pci_clk));

--P1L64Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[14]~13
--operation mode is normal

P1L64Q = AMPP_FUNCTION(R1_decR[3], P1_lat_tmr_reg[3], pci_rstn, GLOBAL(pci_clk));


--dpm_ni2f_reg_sram_qL_15 is dpm_ni2f_reg_sram_qL_15
--operation mode is normal

dpm_ni2f_reg_sram_qL_15_lut_out = dpm_ni2f_reg_sm_8 & (SRAM_IO_15) # !dpm_ni2f_reg_sm_8 & dpm_ni2f_reg_sram_qL_15;
dpm_ni2f_reg_sram_qL_15 = DFFEA(dpm_ni2f_reg_sram_qL_15_lut_out, lcst, , , , , );

--A1L705Q is dpm_ni2f_reg_sram_qL_15~0
--operation mode is normal

A1L705Q = dpm_ni2f_reg_sram_qL_15;


--ix2414 is ix2414
--operation mode is normal

ix2414 = !dpm_ni2f_reg_sram_qL_15 # !M1_lt_adr[19];

--A1L3401 is ix2414~1
--operation mode is normal

A1L3401 = !dpm_ni2f_reg_sram_qL_15 # !M1_lt_adr[19];

--A1L4401 is ix2414~2
--operation mode is normal

A1L4401 = !dpm_ni2f_reg_sram_qL_15 # !M1_lt_adr[19];


--E2_q[15] is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[15]
--operation mode is clrb_cntr

E2_q[15]_lut_out = (E2_q[15] $ (ix2253_lc & E2L13)) & VCC;
E2_q[15] = DFFEA(E2_q[15]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E2L79Q is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[15]~15
--operation mode is clrb_cntr

E2L79Q = E2_q[15];

--E2L33 is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[15]~COUT
--operation mode is clrb_cntr

E2L33 = CARRY(E2_q[15] & (E2L13));


--A1L328 is ix2335~0
--operation mode is normal

A1L328 = (!ix2431_lc # !ix2311_lc # !E2_q[15] # !M1_lt_adr[2]) & CASCADE(A1L4401);

--A1L428 is ix2335~2
--operation mode is normal

A1L428 = (!ix2431_lc # !ix2311_lc # !E2_q[15] # !M1_lt_adr[2]) & CASCADE(A1L4401);

--A1L528 is ix2335~3
--operation mode is normal

A1L528 = (!ix2431_lc # !ix2311_lc # !E2_q[15] # !M1_lt_adr[2]) & CASCADE(A1L4401);


--P1_ad_dat_out[15] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[15]
--operation mode is normal

P1_ad_dat_out[15] = AMPP_FUNCTION(R1_decR[3], P1_lat_tmr_reg[4], pci_rstn, GLOBAL(pci_clk));

--P1L84Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[15]~14
--operation mode is normal

P1L84Q = AMPP_FUNCTION(R1_decR[3], P1_lat_tmr_reg[4], pci_rstn, GLOBAL(pci_clk));


--dpm_ni2f_reg_sram_qH_0 is dpm_ni2f_reg_sram_qH_0
--operation mode is normal

dpm_ni2f_reg_sram_qH_0_lut_out = dpm_ni2f_reg_sm_10 & (SRAM_IO_0) # !dpm_ni2f_reg_sm_10 & dpm_ni2f_reg_sram_qH_0;
dpm_ni2f_reg_sram_qH_0 = DFFEA(dpm_ni2f_reg_sram_qH_0_lut_out, lcst, , , , , );

--A1L544Q is dpm_ni2f_reg_sram_qH_0~0
--operation mode is normal

A1L544Q = dpm_ni2f_reg_sram_qH_0;


--ix2415 is ix2415
--operation mode is normal

ix2415 = !dpm_ni2f_reg_sram_qH_0 # !M1_lt_adr[19];

--A1L6401 is ix2415~1
--operation mode is normal

A1L6401 = !dpm_ni2f_reg_sram_qH_0 # !M1_lt_adr[19];

--A1L7401 is ix2415~2
--operation mode is normal

A1L7401 = !dpm_ni2f_reg_sram_qH_0 # !M1_lt_adr[19];


--E2_q[16] is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[16]
--operation mode is clrb_cntr

E2_q[16]_lut_out = (E2_q[16] $ (ix2253_lc & E2L33)) & VCC;
E2_q[16] = DFFEA(E2_q[16]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E2L99Q is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[16]~16
--operation mode is clrb_cntr

E2L99Q = E2_q[16];

--E2L53 is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[16]~COUT
--operation mode is clrb_cntr

E2L53 = CARRY(E2_q[16] & (E2L33));


--A1L028 is ix2334~0
--operation mode is normal

A1L028 = (!ix2431_lc # !ix2311_lc # !E2_q[16] # !M1_lt_adr[2]) & CASCADE(A1L7401);

--A1L128 is ix2334~2
--operation mode is normal

A1L128 = (!ix2431_lc # !ix2311_lc # !E2_q[16] # !M1_lt_adr[2]) & CASCADE(A1L7401);

--A1L228 is ix2334~3
--operation mode is normal

A1L228 = (!ix2431_lc # !ix2311_lc # !E2_q[16] # !M1_lt_adr[2]) & CASCADE(A1L7401);


--dpm_ni2f_reg_sram_qH_1 is dpm_ni2f_reg_sram_qH_1
--operation mode is normal

dpm_ni2f_reg_sram_qH_1_lut_out = dpm_ni2f_reg_sm_10 & (SRAM_IO_1) # !dpm_ni2f_reg_sm_10 & dpm_ni2f_reg_sram_qH_1;
dpm_ni2f_reg_sram_qH_1 = DFFEA(dpm_ni2f_reg_sram_qH_1_lut_out, lcst, , , , , );

--A1L744Q is dpm_ni2f_reg_sram_qH_1~0
--operation mode is normal

A1L744Q = dpm_ni2f_reg_sram_qH_1;


--ix2416 is ix2416
--operation mode is normal

ix2416 = !dpm_ni2f_reg_sram_qH_1 # !M1_lt_adr[19];

--A1L9401 is ix2416~1
--operation mode is normal

A1L9401 = !dpm_ni2f_reg_sram_qH_1 # !M1_lt_adr[19];

--A1L0501 is ix2416~2
--operation mode is normal

A1L0501 = !dpm_ni2f_reg_sram_qH_1 # !M1_lt_adr[19];


--E2_q[17] is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[17]
--operation mode is clrb_cntr

E2_q[17]_lut_out = (E2_q[17] $ (ix2253_lc & E2L53)) & VCC;
E2_q[17] = DFFEA(E2_q[17]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E2L101Q is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[17]~17
--operation mode is clrb_cntr

E2L101Q = E2_q[17];

--E2L73 is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[17]~COUT
--operation mode is clrb_cntr

E2L73 = CARRY(E2_q[17] & (E2L53));


--A1L718 is ix2333~0
--operation mode is normal

A1L718 = (!ix2431_lc # !ix2311_lc # !E2_q[17] # !M1_lt_adr[2]) & CASCADE(A1L0501);

--A1L818 is ix2333~2
--operation mode is normal

A1L818 = (!ix2431_lc # !ix2311_lc # !E2_q[17] # !M1_lt_adr[2]) & CASCADE(A1L0501);

--A1L918 is ix2333~3
--operation mode is normal

A1L918 = (!ix2431_lc # !ix2311_lc # !E2_q[17] # !M1_lt_adr[2]) & CASCADE(A1L0501);


--dpm_ni2f_reg_sram_qH_2 is dpm_ni2f_reg_sram_qH_2
--operation mode is normal

dpm_ni2f_reg_sram_qH_2_lut_out = dpm_ni2f_reg_sm_10 & (SRAM_IO_2) # !dpm_ni2f_reg_sm_10 & dpm_ni2f_reg_sram_qH_2;
dpm_ni2f_reg_sram_qH_2 = DFFEA(dpm_ni2f_reg_sram_qH_2_lut_out, lcst, , , , , );

--A1L944Q is dpm_ni2f_reg_sram_qH_2~0
--operation mode is normal

A1L944Q = dpm_ni2f_reg_sram_qH_2;


--ix2417 is ix2417
--operation mode is normal

ix2417 = !dpm_ni2f_reg_sram_qH_2 # !M1_lt_adr[19];

--A1L2501 is ix2417~1
--operation mode is normal

A1L2501 = !dpm_ni2f_reg_sram_qH_2 # !M1_lt_adr[19];

--A1L3501 is ix2417~2
--operation mode is normal

A1L3501 = !dpm_ni2f_reg_sram_qH_2 # !M1_lt_adr[19];


--E2_q[18] is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[18]
--operation mode is clrb_cntr

E2_q[18]_lut_out = (E2_q[18] $ (ix2253_lc & E2L73)) & VCC;
E2_q[18] = DFFEA(E2_q[18]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E2L301Q is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[18]~18
--operation mode is clrb_cntr

E2L301Q = E2_q[18];

--E2L93 is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[18]~COUT
--operation mode is clrb_cntr

E2L93 = CARRY(E2_q[18] & (E2L73));


--A1L418 is ix2332~0
--operation mode is normal

A1L418 = (!ix2431_lc # !ix2311_lc # !E2_q[18] # !M1_lt_adr[2]) & CASCADE(A1L3501);

--A1L518 is ix2332~2
--operation mode is normal

A1L518 = (!ix2431_lc # !ix2311_lc # !E2_q[18] # !M1_lt_adr[2]) & CASCADE(A1L3501);

--A1L618 is ix2332~3
--operation mode is normal

A1L618 = (!ix2431_lc # !ix2311_lc # !E2_q[18] # !M1_lt_adr[2]) & CASCADE(A1L3501);


--P1_ad_dat_out[18] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[18]
--operation mode is normal

P1_ad_dat_out[18] = AMPP_FUNCTION(R1_decR[0], pci_rstn, GLOBAL(pci_clk));

--P1L05Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[18]~15
--operation mode is normal

P1L05Q = AMPP_FUNCTION(R1_decR[0], pci_rstn, GLOBAL(pci_clk));


--dpm_ni2f_reg_sram_qH_3 is dpm_ni2f_reg_sram_qH_3
--operation mode is normal

dpm_ni2f_reg_sram_qH_3_lut_out = dpm_ni2f_reg_sm_10 & (SRAM_IO_3) # !dpm_ni2f_reg_sm_10 & dpm_ni2f_reg_sram_qH_3;
dpm_ni2f_reg_sram_qH_3 = DFFEA(dpm_ni2f_reg_sram_qH_3_lut_out, lcst, , , , , );

--A1L154Q is dpm_ni2f_reg_sram_qH_3~0
--operation mode is normal

A1L154Q = dpm_ni2f_reg_sram_qH_3;


--ix2418 is ix2418
--operation mode is normal

ix2418 = !dpm_ni2f_reg_sram_qH_3 # !M1_lt_adr[19];

--A1L5501 is ix2418~1
--operation mode is normal

A1L5501 = !dpm_ni2f_reg_sram_qH_3 # !M1_lt_adr[19];

--A1L6501 is ix2418~2
--operation mode is normal

A1L6501 = !dpm_ni2f_reg_sram_qH_3 # !M1_lt_adr[19];


--E2_q[19] is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[19]
--operation mode is clrb_cntr

E2_q[19]_lut_out = (E2_q[19] $ (ix2253_lc & E2L93)) & VCC;
E2_q[19] = DFFEA(E2_q[19]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E2L501Q is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[19]~19
--operation mode is clrb_cntr

E2L501Q = E2_q[19];

--E2L14 is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[19]~COUT
--operation mode is clrb_cntr

E2L14 = CARRY(E2_q[19] & (E2L93));


--A1L118 is ix2331~0
--operation mode is normal

A1L118 = (!ix2431_lc # !ix2311_lc # !E2_q[19] # !M1_lt_adr[2]) & CASCADE(A1L6501);

--A1L218 is ix2331~2
--operation mode is normal

A1L218 = (!ix2431_lc # !ix2311_lc # !E2_q[19] # !M1_lt_adr[2]) & CASCADE(A1L6501);

--A1L318 is ix2331~3
--operation mode is normal

A1L318 = (!ix2431_lc # !ix2311_lc # !E2_q[19] # !M1_lt_adr[2]) & CASCADE(A1L6501);


--dpm_ni2f_reg_sram_qH_4 is dpm_ni2f_reg_sram_qH_4
--operation mode is normal

dpm_ni2f_reg_sram_qH_4_lut_out = dpm_ni2f_reg_sm_10 & (SRAM_IO_4) # !dpm_ni2f_reg_sm_10 & dpm_ni2f_reg_sram_qH_4;
dpm_ni2f_reg_sram_qH_4 = DFFEA(dpm_ni2f_reg_sram_qH_4_lut_out, lcst, , , , , );

--A1L354Q is dpm_ni2f_reg_sram_qH_4~0
--operation mode is normal

A1L354Q = dpm_ni2f_reg_sram_qH_4;


--ix2419 is ix2419
--operation mode is normal

ix2419 = !dpm_ni2f_reg_sram_qH_4 # !M1_lt_adr[19];

--A1L8501 is ix2419~1
--operation mode is normal

A1L8501 = !dpm_ni2f_reg_sram_qH_4 # !M1_lt_adr[19];

--A1L9501 is ix2419~2
--operation mode is normal

A1L9501 = !dpm_ni2f_reg_sram_qH_4 # !M1_lt_adr[19];


--E2_q[20] is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[20]
--operation mode is clrb_cntr

E2_q[20]_lut_out = (E2_q[20] $ (ix2253_lc & E2L14)) & VCC;
E2_q[20] = DFFEA(E2_q[20]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E2L701Q is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[20]~20
--operation mode is clrb_cntr

E2L701Q = E2_q[20];

--E2L34 is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[20]~COUT
--operation mode is clrb_cntr

E2L34 = CARRY(E2_q[20] & (E2L14));


--A1L808 is ix2330~0
--operation mode is normal

A1L808 = (!ix2431_lc # !ix2311_lc # !E2_q[20] # !M1_lt_adr[2]) & CASCADE(A1L9501);

--A1L908 is ix2330~2
--operation mode is normal

A1L908 = (!ix2431_lc # !ix2311_lc # !E2_q[20] # !M1_lt_adr[2]) & CASCADE(A1L9501);

--A1L018 is ix2330~3
--operation mode is normal

A1L018 = (!ix2431_lc # !ix2311_lc # !E2_q[20] # !M1_lt_adr[2]) & CASCADE(A1L9501);


--P1_ad_dat_out[20] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[20]
--operation mode is normal

P1_ad_dat_out[20] = AMPP_FUNCTION(P1_bar0_reg[20], R1_decR[4], pci_rstn, GLOBAL(pci_clk));

--P1L25Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[20]~16
--operation mode is normal

P1L25Q = AMPP_FUNCTION(P1_bar0_reg[20], R1_decR[4], pci_rstn, GLOBAL(pci_clk));


--dpm_ni2f_reg_sram_qH_5 is dpm_ni2f_reg_sram_qH_5
--operation mode is normal

dpm_ni2f_reg_sram_qH_5_lut_out = dpm_ni2f_reg_sm_10 & (SRAM_IO_5) # !dpm_ni2f_reg_sm_10 & dpm_ni2f_reg_sram_qH_5;
dpm_ni2f_reg_sram_qH_5 = DFFEA(dpm_ni2f_reg_sram_qH_5_lut_out, lcst, , , , , );

--A1L554Q is dpm_ni2f_reg_sram_qH_5~0
--operation mode is normal

A1L554Q = dpm_ni2f_reg_sram_qH_5;


--ix2420 is ix2420
--operation mode is normal

ix2420 = !dpm_ni2f_reg_sram_qH_5 # !M1_lt_adr[19];

--A1L1601 is ix2420~1
--operation mode is normal

A1L1601 = !dpm_ni2f_reg_sram_qH_5 # !M1_lt_adr[19];

--A1L2601 is ix2420~2
--operation mode is normal

A1L2601 = !dpm_ni2f_reg_sram_qH_5 # !M1_lt_adr[19];


--E2_q[21] is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[21]
--operation mode is clrb_cntr

E2_q[21]_lut_out = (E2_q[21] $ (ix2253_lc & E2L34)) & VCC;
E2_q[21] = DFFEA(E2_q[21]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E2L901Q is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[21]~21
--operation mode is clrb_cntr

E2L901Q = E2_q[21];

--E2L54 is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[21]~COUT
--operation mode is clrb_cntr

E2L54 = CARRY(E2_q[21] & (E2L34));


--A1L508 is ix2329~0
--operation mode is normal

A1L508 = (!ix2431_lc # !ix2311_lc # !E2_q[21] # !M1_lt_adr[2]) & CASCADE(A1L2601);

--A1L608 is ix2329~2
--operation mode is normal

A1L608 = (!ix2431_lc # !ix2311_lc # !E2_q[21] # !M1_lt_adr[2]) & CASCADE(A1L2601);

--A1L708 is ix2329~3
--operation mode is normal

A1L708 = (!ix2431_lc # !ix2311_lc # !E2_q[21] # !M1_lt_adr[2]) & CASCADE(A1L2601);


--P1_ad_dat_out[21] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[21]
--operation mode is normal

P1_ad_dat_out[21] = AMPP_FUNCTION(R1_decR[4], P1_bar0_reg[21], pci_rstn, GLOBAL(pci_clk));

--P1L45Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[21]~17
--operation mode is normal

P1L45Q = AMPP_FUNCTION(R1_decR[4], P1_bar0_reg[21], pci_rstn, GLOBAL(pci_clk));


--dpm_ni2f_reg_sram_qH_6 is dpm_ni2f_reg_sram_qH_6
--operation mode is normal

dpm_ni2f_reg_sram_qH_6_lut_out = dpm_ni2f_reg_sm_10 & (SRAM_IO_6) # !dpm_ni2f_reg_sm_10 & dpm_ni2f_reg_sram_qH_6;
dpm_ni2f_reg_sram_qH_6 = DFFEA(dpm_ni2f_reg_sram_qH_6_lut_out, lcst, , , , , );

--A1L754Q is dpm_ni2f_reg_sram_qH_6~0
--operation mode is normal

A1L754Q = dpm_ni2f_reg_sram_qH_6;


--ix2421 is ix2421
--operation mode is normal

ix2421 = !dpm_ni2f_reg_sram_qH_6 # !M1_lt_adr[19];

--A1L4601 is ix2421~1
--operation mode is normal

A1L4601 = !dpm_ni2f_reg_sram_qH_6 # !M1_lt_adr[19];

--A1L5601 is ix2421~2
--operation mode is normal

A1L5601 = !dpm_ni2f_reg_sram_qH_6 # !M1_lt_adr[19];


--E2_q[22] is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[22]
--operation mode is clrb_cntr

E2_q[22]_lut_out = (E2_q[22] $ (ix2253_lc & E2L54)) & VCC;
E2_q[22] = DFFEA(E2_q[22]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E2L111Q is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[22]~22
--operation mode is clrb_cntr

E2L111Q = E2_q[22];

--E2L74 is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[22]~COUT
--operation mode is clrb_cntr

E2L74 = CARRY(E2_q[22] & (E2L54));


--A1L208 is ix2328~0
--operation mode is normal

A1L208 = (!ix2431_lc # !ix2311_lc # !E2_q[22] # !M1_lt_adr[2]) & CASCADE(A1L5601);

--A1L308 is ix2328~2
--operation mode is normal

A1L308 = (!ix2431_lc # !ix2311_lc # !E2_q[22] # !M1_lt_adr[2]) & CASCADE(A1L5601);

--A1L408 is ix2328~3
--operation mode is normal

A1L408 = (!ix2431_lc # !ix2311_lc # !E2_q[22] # !M1_lt_adr[2]) & CASCADE(A1L5601);


--P1_ad_dat_out[22] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[22]
--operation mode is normal

P1_ad_dat_out[22] = AMPP_FUNCTION(R1_decR[4], P1_bar0_reg[22], pci_rstn, GLOBAL(pci_clk));

--P1L65Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[22]~18
--operation mode is normal

P1L65Q = AMPP_FUNCTION(R1_decR[4], P1_bar0_reg[22], pci_rstn, GLOBAL(pci_clk));


--dpm_ni2f_reg_sram_qH_7 is dpm_ni2f_reg_sram_qH_7
--operation mode is normal

dpm_ni2f_reg_sram_qH_7_lut_out = dpm_ni2f_reg_sm_10 & (SRAM_IO_7) # !dpm_ni2f_reg_sm_10 & dpm_ni2f_reg_sram_qH_7;
dpm_ni2f_reg_sram_qH_7 = DFFEA(dpm_ni2f_reg_sram_qH_7_lut_out, lcst, , , , , );

--A1L954Q is dpm_ni2f_reg_sram_qH_7~0
--operation mode is normal

A1L954Q = dpm_ni2f_reg_sram_qH_7;


--ix2422 is ix2422
--operation mode is normal

ix2422 = !dpm_ni2f_reg_sram_qH_7 # !M1_lt_adr[19];

--A1L7601 is ix2422~1
--operation mode is normal

A1L7601 = !dpm_ni2f_reg_sram_qH_7 # !M1_lt_adr[19];

--A1L8601 is ix2422~2
--operation mode is normal

A1L8601 = !dpm_ni2f_reg_sram_qH_7 # !M1_lt_adr[19];


--E2_q[23] is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[23]
--operation mode is clrb_cntr

E2_q[23]_lut_out = (E2_q[23] $ (ix2253_lc & E2L74)) & VCC;
E2_q[23] = DFFEA(E2_q[23]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E2L311Q is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[23]~23
--operation mode is clrb_cntr

E2L311Q = E2_q[23];

--E2L94 is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[23]~COUT
--operation mode is clrb_cntr

E2L94 = CARRY(E2_q[23] & (E2L74));


--A1L997 is ix2327~0
--operation mode is normal

A1L997 = (!ix2431_lc # !ix2311_lc # !E2_q[23] # !M1_lt_adr[2]) & CASCADE(A1L8601);

--A1L008 is ix2327~2
--operation mode is normal

A1L008 = (!ix2431_lc # !ix2311_lc # !E2_q[23] # !M1_lt_adr[2]) & CASCADE(A1L8601);

--A1L108 is ix2327~3
--operation mode is normal

A1L108 = (!ix2431_lc # !ix2311_lc # !E2_q[23] # !M1_lt_adr[2]) & CASCADE(A1L8601);


--P1_ad_dat_out[23] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[23]
--operation mode is normal

P1_ad_dat_out[23] = AMPP_FUNCTION(R1_decR[4], P1_bar0_reg[23], pci_rstn, GLOBAL(pci_clk));

--P1L85Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[23]~19
--operation mode is normal

P1L85Q = AMPP_FUNCTION(R1_decR[4], P1_bar0_reg[23], pci_rstn, GLOBAL(pci_clk));


--P1_ad_dat_out[24] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[24]
--operation mode is normal

P1_ad_dat_out[24] = AMPP_FUNCTION(R1_decR[2], P1L9, R1_decR[1], P1_stat_reg[8], pci_rstn, GLOBAL(pci_clk));

--P1L06Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[24]~20
--operation mode is normal

P1L06Q = AMPP_FUNCTION(R1_decR[2], P1L9, R1_decR[1], P1_stat_reg[8], pci_rstn, GLOBAL(pci_clk));


--P1_ad_dat_out[25] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[25]
--operation mode is normal

P1_ad_dat_out[25] = AMPP_FUNCTION(R1_decR[2], R1_decR[4], P1_bar0_reg[25], pci_rstn, GLOBAL(pci_clk));

--P1L26Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[25]~21
--operation mode is normal

P1L26Q = AMPP_FUNCTION(R1_decR[2], R1_decR[4], P1_bar0_reg[25], pci_rstn, GLOBAL(pci_clk));


--P1_ad_dat_out[26] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[26]
--operation mode is normal

P1_ad_dat_out[26] = AMPP_FUNCTION(R1_decR[1], R1_decR[2], R1_decR[4], P1_bar0_reg[26], pci_rstn, GLOBAL(pci_clk));

--P1L46Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[26]~22
--operation mode is normal

P1L46Q = AMPP_FUNCTION(R1_decR[1], R1_decR[2], R1_decR[4], P1_bar0_reg[26], pci_rstn, GLOBAL(pci_clk));


--P1_ad_dat_out[27] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[27]
--operation mode is normal

P1_ad_dat_out[27] = AMPP_FUNCTION(R1_decR[2], R1_decR[4], P1_bar0_reg[27], pci_rstn, GLOBAL(pci_clk));

--P1L66Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[27]~23
--operation mode is normal

P1L66Q = AMPP_FUNCTION(R1_decR[2], R1_decR[4], P1_bar0_reg[27], pci_rstn, GLOBAL(pci_clk));


--P1_ad_dat_out[28] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[28]
--operation mode is normal

P1_ad_dat_out[28] = AMPP_FUNCTION(R1_decR[2], P1L8, R1_decR[1], N5_REG, pci_rstn, GLOBAL(pci_clk));

--P1L86Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[28]~24
--operation mode is normal

P1L86Q = AMPP_FUNCTION(R1_decR[2], P1L8, R1_decR[1], N5_REG, pci_rstn, GLOBAL(pci_clk));


--P1_ad_dat_out[29] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[29]
--operation mode is normal

P1_ad_dat_out[29] = AMPP_FUNCTION(R1_decR[2], P1L7, R1_decR[1], N6_REG, pci_rstn, GLOBAL(pci_clk));

--P1L07Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[29]~25
--operation mode is normal

P1L07Q = AMPP_FUNCTION(R1_decR[2], P1L7, R1_decR[1], N6_REG, pci_rstn, GLOBAL(pci_clk));


--P1_ad_dat_out[30] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[30]
--operation mode is normal

P1_ad_dat_out[30] = AMPP_FUNCTION(R1_decR[2], P1L6, R1_decR[1], N7_REG, pci_rstn, GLOBAL(pci_clk));

--P1L27Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[30]~26
--operation mode is normal

P1L27Q = AMPP_FUNCTION(R1_decR[2], P1L6, R1_decR[1], N7_REG, pci_rstn, GLOBAL(pci_clk));


--P1_ad_dat_out[31] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[31]
--operation mode is normal

P1_ad_dat_out[31] = AMPP_FUNCTION(R1_decR[2], P1L5, R1_decR[1], N8_REG, pci_rstn, GLOBAL(pci_clk));

--P1L47Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|ad_dat_out[31]~27
--operation mode is normal

P1L47Q = AMPP_FUNCTION(R1_decR[2], P1L5, R1_decR[1], N8_REG, pci_rstn, GLOBAL(pci_clk));


--J1_cbe_oer_r1_lc2 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|cbe_oer_r1_lc2
--operation mode is normal

J1_cbe_oer_r1_lc2 = AMPP_FUNCTION(J1_MS_DXFR, J1_irdy_or_not, J1_frame_or_not);

--J1L631 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|cbe_oer_r1_lc2~24
--operation mode is normal

J1L631 = AMPP_FUNCTION(J1_MS_DXFR, J1_irdy_or_not, J1_frame_or_not);


--M1_TS_ADR_CLMD is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|TS_ADR_CLMD
--operation mode is normal

M1_TS_ADR_CLMD = AMPP_FUNCTION(M1L905, M1_TS_ADR_VLD, M1_retry, K1_serr_or, pci_rstn, GLOBAL(pci_clk));

--M1L115Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|TS_ADR_CLMD~17
--operation mode is normal

M1L115Q = AMPP_FUNCTION(M1L905, M1_TS_ADR_VLD, M1_retry, K1_serr_or, pci_rstn, GLOBAL(pci_clk));


--P1_cmd_reg[1] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|cmd_reg[1]
--operation mode is normal

P1_cmd_reg[1] = AMPP_FUNCTION(P1L771, G1_low_ad_IR_data[1], pci_rstn, GLOBAL(pci_clk));

--P1L231Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|cmd_reg[1]~9
--operation mode is normal

P1L231Q = AMPP_FUNCTION(P1L771, G1_low_ad_IR_data[1], pci_rstn, GLOBAL(pci_clk));


--P1_cyc_vld[0] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|cyc_vld[0]
--operation mode is normal

P1_cyc_vld[0] = AMPP_FUNCTION(P1_cmd_reg[1], P1_mem_cyc);

--P1L341 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|cyc_vld[0]~1
--operation mode is normal

P1L341 = AMPP_FUNCTION(P1_cmd_reg[1], P1_mem_cyc);


--U41_aeb_out is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|lpm_compare:bar0_comp|comptree:comparator|comptree:sub_comptree|cmpchain:cmp_end|aeb_out
--operation mode is normal

U41_aeb_out = AMPP_FUNCTION(U31_aeb_out, U9_aeb_out);

--U41L3 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|lpm_compare:bar0_comp|comptree:comparator|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~8
--operation mode is normal

U41L3 = AMPP_FUNCTION(U31_aeb_out, U9_aeb_out);


--J1L01 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|$00118~0
--operation mode is normal

J1L01 = AMPP_FUNCTION(J1_MS_IDLE_not, J1_frame_or_not);

--J1L11 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|$00118~10
--operation mode is normal

J1L11 = AMPP_FUNCTION(J1_MS_IDLE_not, J1_frame_or_not);

--J1L21 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|$00118~11
--operation mode is normal

J1L21 = AMPP_FUNCTION(J1_MS_IDLE_not, J1_frame_or_not);


--J1L191 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|frame_or_lc1~9
--operation mode is normal

J1L191 = AMPP_FUNCTION(J1_frame_or_lc1a, J1_last_xfr, J1_frame_or_lc1b, J1_frame_or_lc1c, J1L21);

--J1L291 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|frame_or_lc1~10
--operation mode is normal

J1L291 = AMPP_FUNCTION(J1_frame_or_lc1a, J1_last_xfr, J1_frame_or_lc1b, J1_frame_or_lc1c, J1L21);


--J1_frame_or_lc2a is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|frame_or_lc2a
--operation mode is normal

J1_frame_or_lc2a = AMPP_FUNCTION(J1_MS_DXFR, J1_wr_rdn, J1_MW_LXFR);

--J1L691 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|frame_or_lc2a~30
--operation mode is normal

J1L691 = AMPP_FUNCTION(J1_MS_DXFR, J1_wr_rdn, J1_MW_LXFR);


--J1_irdy_or_lc[7] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|irdy_or_lc[7]
--operation mode is normal

J1_irdy_or_lc[7] = AMPP_FUNCTION(J1_MR_PXFR, J1_MW_DXFR);

--J1L642 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|irdy_or_lc[7]~51
--operation mode is normal

J1L642 = AMPP_FUNCTION(J1_MR_PXFR, J1_MW_DXFR);


--J1_irdy_or_lc[8] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|irdy_or_lc[8]
--operation mode is normal

J1_irdy_or_lc[8] = AMPP_FUNCTION(J1_MW_LAST, J1_MR_LPXFR);

--J1L942 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|irdy_or_lc[8]~52
--operation mode is normal

J1L942 = AMPP_FUNCTION(J1_MW_LAST, J1_MR_LPXFR);


--J1_lm_rdynR is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lm_rdynR
--operation mode is normal

J1_lm_rdynR = AMPP_FUNCTION(pci_rstn, GLOBAL(pci_clk));

--J1L282Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lm_rdynR~13
--operation mode is normal

J1L282Q = AMPP_FUNCTION(pci_rstn, GLOBAL(pci_clk));


--J1_irdy_or_lc[6] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|irdy_or_lc[6]
--operation mode is normal

J1_irdy_or_lc[6] = AMPP_FUNCTION(J1_MW_DXFR, J1_irdy_or_lc6a, J1_MW_LXFR, J1_lm_rdynR);

--J1L342 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|irdy_or_lc[6]~53
--operation mode is normal

J1L342 = AMPP_FUNCTION(J1_MW_DXFR, J1_irdy_or_lc6a, J1_MW_LXFR, J1_lm_rdynR);


--J1_frame_or_lc1b is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|frame_or_lc1b
--operation mode is normal

J1_frame_or_lc1b = AMPP_FUNCTION(J1_MW_LXFR, J1_lm_rdynR);

--J1L881 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|frame_or_lc1b~4
--operation mode is normal

J1L881 = AMPP_FUNCTION(J1_MW_LXFR, J1_lm_rdynR);


--J1_ms_dxfr_lc1 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|ms_dxfr_lc1
--operation mode is normal

J1_ms_dxfr_lc1 = AMPP_FUNCTION(J1_ms_dxfr_lc1c, J1_ms_dxfr_lc1a, J1_ms_dxfr_lc1b);

--J1L783 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|ms_dxfr_lc1~22
--operation mode is normal

J1L783 = AMPP_FUNCTION(J1_ms_dxfr_lc1c, J1_ms_dxfr_lc1a, J1_ms_dxfr_lc1b);


--J1_ms_dxfr_lc2 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|ms_dxfr_lc2
--operation mode is normal

J1_ms_dxfr_lc2 = AMPP_FUNCTION(J1_MS_DXFR, J1_irdy_or_not, J1_frame_or_not, J1_mstr_abrt);

--J1L193 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|ms_dxfr_lc2~35
--operation mode is normal

J1L193 = AMPP_FUNCTION(J1_MS_DXFR, J1_irdy_or_not, J1_frame_or_not, J1_mstr_abrt);


--J1_park_d_carry is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|park_d_carry
--operation mode is arithmetic

J1_park_d_carry = AMPP_FUNCTION();

--J1L285 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|park_d_carry~18
--operation mode is arithmetic

J1L285 = AMPP_FUNCTION();

--J1L385 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|park_d_carry~COUT
--operation mode is arithmetic

J1L385 = AMPP_FUNCTION(A1L5321, J1_no_op_reg[7]);


--J1_MR_END is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_END
--operation mode is normal

J1_MR_END = AMPP_FUNCTION(J1_MR_END_d_lc1, J1_no_op_reg[6], A1L5421, pci_rstn, GLOBAL(pci_clk), J1L682);

--J1L292Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_END~7
--operation mode is normal

J1L292Q = AMPP_FUNCTION(J1_MR_END_d_lc1, J1_no_op_reg[6], A1L5421, pci_rstn, GLOBAL(pci_clk), J1L682);


--M1_no_op_reg[12] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[12]
--operation mode is normal

M1_no_op_reg[12] = AMPP_FUNCTION(pci_rstn, GLOBAL(pci_clk));

--M1L724Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[12]~10
--operation mode is normal

M1L724Q = AMPP_FUNCTION(pci_rstn, GLOBAL(pci_clk));


--M1L61 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|$00130~0
--operation mode is normal

M1L61 = AMPP_FUNCTION(M1_no_op_reg[12], M1_TS_IDLE_NOT, A1L5321);

--M1L71 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|$00130~10
--operation mode is normal

M1L71 = AMPP_FUNCTION(M1_no_op_reg[12], M1_TS_IDLE_NOT, A1L5321);

--M1L81 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|$00130~11
--operation mode is normal

M1L81 = AMPP_FUNCTION(M1_no_op_reg[12], M1_TS_IDLE_NOT, A1L5321);


--G1_low_ad_IR_data[28] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[28]
--operation mode is normal

G1_low_ad_IR_data[28] = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_28, pci_rstn, GLOBAL(pci_clk));

--G1L872Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[28]~41
--operation mode is normal

G1L872Q = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_28, pci_rstn, GLOBAL(pci_clk));


--G1_low_ad_IR_data[29] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[29]
--operation mode is normal

G1_low_ad_IR_data[29] = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_29, pci_rstn, GLOBAL(pci_clk));

--G1L082Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[29]~42
--operation mode is normal

G1L082Q = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_29, pci_rstn, GLOBAL(pci_clk));


--G1_low_ad_IR_data[30] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[30]
--operation mode is normal

G1_low_ad_IR_data[30] = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_30, pci_rstn, GLOBAL(pci_clk));

--G1L282Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[30]~43
--operation mode is normal

G1L282Q = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_30, pci_rstn, GLOBAL(pci_clk));


--G1_low_ad_IR_data[31] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[31]
--operation mode is normal

G1_low_ad_IR_data[31] = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_31, pci_rstn, GLOBAL(pci_clk));

--G1L482Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[31]~44
--operation mode is normal

G1L482Q = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_31, pci_rstn, GLOBAL(pci_clk));


--K1_xxl[7] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|xxl[7]
--operation mode is normal

K1_xxl[7] = AMPP_FUNCTION(G1_low_ad_IR_data[28], G1_low_ad_IR_data[29], G1_low_ad_IR_data[30], G1_low_ad_IR_data[31]);

--K1L93 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|xxl[7]~228
--operation mode is normal

K1L93 = AMPP_FUNCTION(G1_low_ad_IR_data[28], G1_low_ad_IR_data[29], G1_low_ad_IR_data[30], G1_low_ad_IR_data[31]);


--G1_low_ad_IR_data[24] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[24]
--operation mode is normal

G1_low_ad_IR_data[24] = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_24, pci_rstn, GLOBAL(pci_clk));

--G1L072Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[24]~45
--operation mode is normal

G1L072Q = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_24, pci_rstn, GLOBAL(pci_clk));


--G1_low_ad_IR_data[25] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[25]
--operation mode is normal

G1_low_ad_IR_data[25] = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_25, pci_rstn, GLOBAL(pci_clk));

--G1L272Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[25]~46
--operation mode is normal

G1L272Q = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_25, pci_rstn, GLOBAL(pci_clk));


--G1_low_ad_IR_data[26] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[26]
--operation mode is normal

G1_low_ad_IR_data[26] = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_26, pci_rstn, GLOBAL(pci_clk));

--G1L472Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[26]~47
--operation mode is normal

G1L472Q = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_26, pci_rstn, GLOBAL(pci_clk));


--G1_low_ad_IR_data[27] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[27]
--operation mode is normal

G1_low_ad_IR_data[27] = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_27, pci_rstn, GLOBAL(pci_clk));

--G1L672Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[27]~48
--operation mode is normal

G1L672Q = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_27, pci_rstn, GLOBAL(pci_clk));


--K1_xxl[6] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|xxl[6]
--operation mode is normal

K1_xxl[6] = AMPP_FUNCTION(G1_low_ad_IR_data[24], G1_low_ad_IR_data[25], G1_low_ad_IR_data[26], G1_low_ad_IR_data[27]);

--K1L63 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|xxl[6]~229
--operation mode is normal

K1L63 = AMPP_FUNCTION(G1_low_ad_IR_data[24], G1_low_ad_IR_data[25], G1_low_ad_IR_data[26], G1_low_ad_IR_data[27]);


--G1_low_ad_IR_data[20] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[20]
--operation mode is normal

G1_low_ad_IR_data[20] = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_20, pci_rstn, GLOBAL(pci_clk));

--G1L262Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[20]~49
--operation mode is normal

G1L262Q = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_20, pci_rstn, GLOBAL(pci_clk));


--G1_low_ad_IR_data[21] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[21]
--operation mode is normal

G1_low_ad_IR_data[21] = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_21, pci_rstn, GLOBAL(pci_clk));

--G1L462Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[21]~50
--operation mode is normal

G1L462Q = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_21, pci_rstn, GLOBAL(pci_clk));


--G1_low_ad_IR_data[22] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[22]
--operation mode is normal

G1_low_ad_IR_data[22] = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_22, pci_rstn, GLOBAL(pci_clk));

--G1L662Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[22]~51
--operation mode is normal

G1L662Q = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_22, pci_rstn, GLOBAL(pci_clk));


--G1_low_ad_IR_data[23] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[23]
--operation mode is normal

G1_low_ad_IR_data[23] = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_23, pci_rstn, GLOBAL(pci_clk));

--G1L862Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[23]~52
--operation mode is normal

G1L862Q = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_23, pci_rstn, GLOBAL(pci_clk));


--K1_xxl[5] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|xxl[5]
--operation mode is normal

K1_xxl[5] = AMPP_FUNCTION(G1_low_ad_IR_data[20], G1_low_ad_IR_data[21], G1_low_ad_IR_data[22], G1_low_ad_IR_data[23]);

--K1L33 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|xxl[5]~230
--operation mode is normal

K1L33 = AMPP_FUNCTION(G1_low_ad_IR_data[20], G1_low_ad_IR_data[21], G1_low_ad_IR_data[22], G1_low_ad_IR_data[23]);


--G1_low_ad_IR_data[19] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[19]
--operation mode is normal

G1_low_ad_IR_data[19] = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_19, pci_rstn, GLOBAL(pci_clk));

--G1L062Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[19]~53
--operation mode is normal

G1L062Q = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_19, pci_rstn, GLOBAL(pci_clk));


--G1_low_ad_IR_data[18] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[18]
--operation mode is normal

G1_low_ad_IR_data[18] = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_18, pci_rstn, GLOBAL(pci_clk));

--G1L852Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[18]~54
--operation mode is normal

G1L852Q = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_18, pci_rstn, GLOBAL(pci_clk));


--G1_low_ad_IR_data[17] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[17]
--operation mode is normal

G1_low_ad_IR_data[17] = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_17, pci_rstn, GLOBAL(pci_clk));

--G1L652Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[17]~55
--operation mode is normal

G1L652Q = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_17, pci_rstn, GLOBAL(pci_clk));


--G1_low_ad_IR_data[16] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[16]
--operation mode is normal

G1_low_ad_IR_data[16] = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_16, pci_rstn, GLOBAL(pci_clk));

--G1L452Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[16]~56
--operation mode is normal

G1L452Q = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_16, pci_rstn, GLOBAL(pci_clk));


--K1_xxl[4] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|xxl[4]
--operation mode is normal

K1_xxl[4] = AMPP_FUNCTION(G1_low_ad_IR_data[19], G1_low_ad_IR_data[18], G1_low_ad_IR_data[17], G1_low_ad_IR_data[16]);

--K1L03 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|xxl[4]~231
--operation mode is normal

K1L03 = AMPP_FUNCTION(G1_low_ad_IR_data[19], G1_low_ad_IR_data[18], G1_low_ad_IR_data[17], G1_low_ad_IR_data[16]);


--G1_low_ad_IR_data[12] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[12]
--operation mode is normal

G1_low_ad_IR_data[12] = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_12, pci_rstn, GLOBAL(pci_clk));

--G1L642Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[12]~57
--operation mode is normal

G1L642Q = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_12, pci_rstn, GLOBAL(pci_clk));


--G1_low_ad_IR_data[13] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[13]
--operation mode is normal

G1_low_ad_IR_data[13] = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_13, pci_rstn, GLOBAL(pci_clk));

--G1L842Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[13]~58
--operation mode is normal

G1L842Q = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_13, pci_rstn, GLOBAL(pci_clk));


--G1_low_ad_IR_data[14] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[14]
--operation mode is normal

G1_low_ad_IR_data[14] = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_14, pci_rstn, GLOBAL(pci_clk));

--G1L052Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[14]~59
--operation mode is normal

G1L052Q = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_14, pci_rstn, GLOBAL(pci_clk));


--G1_low_ad_IR_data[15] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[15]
--operation mode is normal

G1_low_ad_IR_data[15] = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_15, pci_rstn, GLOBAL(pci_clk));

--G1L252Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[15]~60
--operation mode is normal

G1L252Q = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_15, pci_rstn, GLOBAL(pci_clk));


--K1_xxl[3] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|xxl[3]
--operation mode is normal

K1_xxl[3] = AMPP_FUNCTION(G1_low_ad_IR_data[12], G1_low_ad_IR_data[13], G1_low_ad_IR_data[14], G1_low_ad_IR_data[15]);

--K1L72 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|xxl[3]~232
--operation mode is normal

K1L72 = AMPP_FUNCTION(G1_low_ad_IR_data[12], G1_low_ad_IR_data[13], G1_low_ad_IR_data[14], G1_low_ad_IR_data[15]);


--G1_low_ad_IR_data[11] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[11]
--operation mode is normal

G1_low_ad_IR_data[11] = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_11, pci_rstn, GLOBAL(pci_clk));

--G1L442Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[11]~61
--operation mode is normal

G1L442Q = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_11, pci_rstn, GLOBAL(pci_clk));


--G1_low_ad_IR_data[10] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[10]
--operation mode is normal

G1_low_ad_IR_data[10] = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_10, pci_rstn, GLOBAL(pci_clk));

--G1L242Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[10]~62
--operation mode is normal

G1L242Q = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_10, pci_rstn, GLOBAL(pci_clk));


--G1_low_ad_IR_data[9] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[9]
--operation mode is normal

G1_low_ad_IR_data[9] = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_9, pci_rstn, GLOBAL(pci_clk));

--G1L042Q is pci_contr:pci|pci_mt32:pci_mt32_inst|low_ad_IR_data[9]~63
--operation mode is normal

G1L042Q = AMPP_FUNCTION(G1_ad_IR_ce_data, pci_ad_9, pci_rstn, GLOBAL(pci_clk));


--K1_xxl[2] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|xxl[2]
--operation mode is normal

K1_xxl[2] = AMPP_FUNCTION(G1_low_ad_IR_data[8], G1_low_ad_IR_data[11], G1_low_ad_IR_data[10], G1_low_ad_IR_data[9]);

--K1L42 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|xxl[2]~233
--operation mode is normal

K1L42 = AMPP_FUNCTION(G1_low_ad_IR_data[8], G1_low_ad_IR_data[11], G1_low_ad_IR_data[10], G1_low_ad_IR_data[9]);


--K1_xxl[1] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|xxl[1]
--operation mode is normal

K1_xxl[1] = AMPP_FUNCTION(G1_low_ad_IR_data[6], G1_low_ad_IR_data[4], G1_low_ad_IR_data[7], G1_low_ad_IR_data[5]);

--K1L12 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|xxl[1]~234
--operation mode is normal

K1L12 = AMPP_FUNCTION(G1_low_ad_IR_data[6], G1_low_ad_IR_data[4], G1_low_ad_IR_data[7], G1_low_ad_IR_data[5]);


--K1_xxl[0] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|xxl[0]
--operation mode is normal

K1_xxl[0] = AMPP_FUNCTION(G1_low_ad_IR_data[2], G1_low_ad_IR_data[0], G1_low_ad_IR_data[3], G1_low_ad_IR_data[1]);

--K1L81 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|xxl[0]~235
--operation mode is normal

K1L81 = AMPP_FUNCTION(G1_low_ad_IR_data[2], G1_low_ad_IR_data[0], G1_low_ad_IR_data[3], G1_low_ad_IR_data[1]);


--J1_$00173 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|$00173
--operation mode is normal

J1_$00173 = AMPP_FUNCTION(J1_frame_or_not, J1_MS_DXFR, J1_mstr_abrt, J1_irdy_or_not);

--J1L62 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|$00173~33
--operation mode is normal

J1L62 = AMPP_FUNCTION(J1_frame_or_not, J1_MS_DXFR, J1_mstr_abrt, J1_irdy_or_not);


--J1_$00174 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|$00174
--operation mode is normal

J1_$00174 = AMPP_FUNCTION(J1_frame_or_not, J1_MS_DXFR, J1_irdy_or_not);

--J1L92 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|$00174~22
--operation mode is normal

J1L92 = AMPP_FUNCTION(J1_frame_or_not, J1_MS_DXFR, J1_irdy_or_not);


--M1_LW_DONE_carry is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LW_DONE_carry
--operation mode is arithmetic

M1_LW_DONE_carry = AMPP_FUNCTION();

--M1L773 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LW_DONE_carry~18
--operation mode is arithmetic

M1L773 = AMPP_FUNCTION();

--M1L873 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LW_DONE_carry~COUT
--operation mode is arithmetic

M1L873 = AMPP_FUNCTION(A1L5321, M1_LW_DONE_lc[1]);


--M1_LW_IDLE_lc1 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LW_IDLE_lc1
--operation mode is normal

M1_LW_IDLE_lc1 = AMPP_FUNCTION(M1L983, N3_REG, M1_cfg_cyc);

--M1L093 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LW_IDLE_lc1~39
--operation mode is normal

M1L093 = AMPP_FUNCTION(M1L983, N3_REG, M1_cfg_cyc);


--M1L154 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|stop_or_cc4~0
--operation mode is normal

M1L154 = AMPP_FUNCTION(M1_TS_DISC, M1_LW_LXFR, M1_$00153, N3_REG);

--M1L254 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|stop_or_cc4~3
--operation mode is normal

M1L254 = AMPP_FUNCTION(M1_TS_DISC, M1_LW_LXFR, M1_$00153, N3_REG);

--M1L354 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|stop_or_cc4~4
--operation mode is normal

M1L354 = AMPP_FUNCTION(M1_TS_DISC, M1_LW_LXFR, M1_$00153, N3_REG);


--M1L68 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|_~1478
--operation mode is normal

M1L68 = AMPP_FUNCTION(M1_TS_DISC, M1_LR_PXFR, M1L354);

--M1L79 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|_~1506
--operation mode is normal

M1L79 = AMPP_FUNCTION(M1_TS_DISC, M1_LR_PXFR, M1L354);


--M1L36 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|_~91
--operation mode is normal

M1L36 = AMPP_FUNCTION(M1L754, J1_mstr_actv_lc, M1_TS_ADR_CLMD, M1_cfg_cyc);

--M1L89 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|_~1507
--operation mode is normal

M1L89 = AMPP_FUNCTION(M1L754, J1_mstr_actv_lc, M1_TS_ADR_CLMD, M1_cfg_cyc);

--M1L99 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|_~1508
--operation mode is normal

M1L99 = AMPP_FUNCTION(M1L754, J1_mstr_actv_lc, M1_TS_ADR_CLMD, M1_cfg_cyc);


--N1_REG is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_sr:burst_trans|REG
--operation mode is normal

N1_REG = AMPP_FUNCTION(N1_REG, M1_burst_trans_r, A1L0321, pci_rstn, GLOBAL(pci_clk), M1L641);

--N1L2Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_sr:burst_trans|REG~1
--operation mode is normal

N1L2Q = AMPP_FUNCTION(N1_REG, M1_burst_trans_r, A1L0321, pci_rstn, GLOBAL(pci_clk), M1L641);


--M1_targ_burst_lc is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|targ_burst_lc
--operation mode is normal

M1_targ_burst_lc = AMPP_FUNCTION(M1_TS_IDLE_NOT, N1_REG);

--M1L174 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|targ_burst_lc~8
--operation mode is normal

M1L174 = AMPP_FUNCTION(M1_TS_IDLE_NOT, N1_REG);


--dpm_dec_reg_LT_RDY_n_pci is dpm_dec_reg_LT_RDY_n_pci
--operation mode is normal

dpm_dec_reg_LT_RDY_n_pci_lut_out = dpm_dec_reg_tmp3;
dpm_dec_reg_LT_RDY_n_pci = DFFEA(dpm_dec_reg_LT_RDY_n_pci_lut_out, GLOBAL(pci_clk), pci_rstn, , , , );

--A1L32Q is dpm_dec_reg_LT_RDY_n_pci~10
--operation mode is normal

A1L32Q = dpm_dec_reg_LT_RDY_n_pci;


--M1L205 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|trdy_OR_lc[5]~82
--operation mode is normal

M1L205 = AMPP_FUNCTION(M1_trdy_OR_lc[3], M1_TS_DXFR, M1_LW_WAIT, dpm_dec_reg_LT_RDY_n_pci, M1L42);

--M1L305 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|trdy_OR_lc[5]~83
--operation mode is normal

M1L305 = AMPP_FUNCTION(M1_trdy_OR_lc[3], M1_TS_DXFR, M1_LW_WAIT, dpm_dec_reg_LT_RDY_n_pci, M1L42);


--M1_LW_LXFR_lc[2] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LW_LXFR_lc[2]
--operation mode is normal

M1_LW_LXFR_lc[2] = AMPP_FUNCTION(M1_LW_LXFR, M1_TS_DXFR, dpm_dec_reg_LT_RDY_n_pci);

--M1L904 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LW_LXFR_lc[2]~77
--operation mode is normal

M1L904 = AMPP_FUNCTION(M1_LW_LXFR, M1_TS_DXFR, dpm_dec_reg_LT_RDY_n_pci);


--dpm_ni2f_fifo_h_result_dec_80_ix35_carry_sum is dpm_ni2f_fifo_h_result_dec_80_ix35_carry_sum
--operation mode is arithmetic

dpm_ni2f_fifo_h_result_dec_80_ix35_carry_sum = dpm_ni2f_fifo_h_reg_nwords_2 $ (!A1L021);

--A1L221 is dpm_ni2f_fifo_h_result_dec_80_ix35_carry_sum~12
--operation mode is arithmetic

A1L221 = dpm_ni2f_fifo_h_reg_nwords_2 $ (!A1L021);

--A1L321 is dpm_ni2f_fifo_h_result_dec_80_ix35_carry_sum~COUT
--operation mode is arithmetic

A1L321 = CARRY(dpm_ni2f_fifo_h_reg_nwords_2 # A1L021);


--ix2359 is ix2359
--operation mode is normal

ix2359 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_h_reg_fifo_full # !dpm_ni2f_fifo_h_result_dec_80_ix35_carry_sum # !dpm_ni2f_reg_rdreq_fifo;

--A1L288 is ix2359~1
--operation mode is normal

A1L288 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_h_reg_fifo_full # !dpm_ni2f_fifo_h_result_dec_80_ix35_carry_sum # !dpm_ni2f_reg_rdreq_fifo;

--A1L388 is ix2359~2
--operation mode is normal

A1L388 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_h_reg_fifo_full # !dpm_ni2f_fifo_h_result_dec_80_ix35_carry_sum # !dpm_ni2f_reg_rdreq_fifo;


--dpm_ni2f_fifo_h_result_inc_82_ix35_carry_sum is dpm_ni2f_fifo_h_result_inc_82_ix35_carry_sum
--operation mode is arithmetic

dpm_ni2f_fifo_h_result_inc_82_ix35_carry_sum = dpm_ni2f_fifo_h_reg_nwords_2 $ (A1L651);

--A1L851 is dpm_ni2f_fifo_h_result_inc_82_ix35_carry_sum~12
--operation mode is arithmetic

A1L851 = dpm_ni2f_fifo_h_reg_nwords_2 $ (A1L651);

--A1L951 is dpm_ni2f_fifo_h_result_inc_82_ix35_carry_sum~COUT
--operation mode is arithmetic

A1L951 = CARRY(dpm_ni2f_fifo_h_reg_nwords_2 & (A1L651));


--A1L907 is ix2297~0
--operation mode is normal

A1L907 = (!ix2319_lc # !dpm_ni2f_fifo_h_result_inc_82_ix35_carry_sum) & CASCADE(A1L388);

--A1L017 is ix2297~1
--operation mode is normal

A1L017 = (!ix2319_lc # !dpm_ni2f_fifo_h_result_inc_82_ix35_carry_sum) & CASCADE(A1L388);


--dpm_ni2f_fifo_h_result_dec_80_ix31_carry_sum is dpm_ni2f_fifo_h_result_dec_80_ix31_carry_sum
--operation mode is arithmetic

dpm_ni2f_fifo_h_result_dec_80_ix31_carry_sum = dpm_ni2f_fifo_h_reg_nwords_1 $ (!A1L711);

--A1L911 is dpm_ni2f_fifo_h_result_dec_80_ix31_carry_sum~12
--operation mode is arithmetic

A1L911 = dpm_ni2f_fifo_h_reg_nwords_1 $ (!A1L711);

--A1L021 is dpm_ni2f_fifo_h_result_dec_80_ix31_carry_sum~COUT
--operation mode is arithmetic

A1L021 = CARRY(dpm_ni2f_fifo_h_reg_nwords_1 # A1L711);


--ix2358 is ix2358
--operation mode is normal

ix2358 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_h_reg_fifo_full # !dpm_ni2f_fifo_h_result_dec_80_ix31_carry_sum # !dpm_ni2f_reg_rdreq_fifo;

--A1L978 is ix2358~1
--operation mode is normal

A1L978 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_h_reg_fifo_full # !dpm_ni2f_fifo_h_result_dec_80_ix31_carry_sum # !dpm_ni2f_reg_rdreq_fifo;

--A1L088 is ix2358~2
--operation mode is normal

A1L088 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_h_reg_fifo_full # !dpm_ni2f_fifo_h_result_dec_80_ix31_carry_sum # !dpm_ni2f_reg_rdreq_fifo;


--dpm_ni2f_fifo_h_result_inc_82_ix31_carry_sum is dpm_ni2f_fifo_h_result_inc_82_ix31_carry_sum
--operation mode is arithmetic

dpm_ni2f_fifo_h_result_inc_82_ix31_carry_sum = dpm_ni2f_fifo_h_reg_nwords_1 $ (A1L351);

--A1L551 is dpm_ni2f_fifo_h_result_inc_82_ix31_carry_sum~12
--operation mode is arithmetic

A1L551 = dpm_ni2f_fifo_h_reg_nwords_1 $ (A1L351);

--A1L651 is dpm_ni2f_fifo_h_result_inc_82_ix31_carry_sum~COUT
--operation mode is arithmetic

A1L651 = CARRY(dpm_ni2f_fifo_h_reg_nwords_1 & (A1L351));


--A1L117 is ix2298~0
--operation mode is normal

A1L117 = (!ix2319_lc # !dpm_ni2f_fifo_h_result_inc_82_ix31_carry_sum) & CASCADE(A1L088);

--A1L217 is ix2298~1
--operation mode is normal

A1L217 = (!ix2319_lc # !dpm_ni2f_fifo_h_result_inc_82_ix31_carry_sum) & CASCADE(A1L088);


--ix2357 is ix2357
--operation mode is normal

ix2357 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_h_reg_fifo_full # !dpm_ni2f_fifo_h_result_dec_80_ix27_lc # !dpm_ni2f_reg_rdreq_fifo;

--A1L678 is ix2357~1
--operation mode is normal

A1L678 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_h_reg_fifo_full # !dpm_ni2f_fifo_h_result_dec_80_ix27_lc # !dpm_ni2f_reg_rdreq_fifo;

--A1L778 is ix2357~2
--operation mode is normal

A1L778 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_h_reg_fifo_full # !dpm_ni2f_fifo_h_result_dec_80_ix27_lc # !dpm_ni2f_reg_rdreq_fifo;


--A1L317 is ix2299~0
--operation mode is normal

A1L317 = (!ix2319_lc # !dpm_ni2f_fifo_h_result_inc_82_ix27_lc) & CASCADE(A1L778);

--A1L417 is ix2299~1
--operation mode is normal

A1L417 = (!ix2319_lc # !dpm_ni2f_fifo_h_result_inc_82_ix27_lc) & CASCADE(A1L778);


--dpm_ni2f_fifo_h_modgen_eq_69_ix17 is dpm_ni2f_fifo_h_modgen_eq_69_ix17
--operation mode is normal

dpm_ni2f_fifo_h_modgen_eq_69_ix17 = dpm_ni2f_fifo_h_reg_nwords_10 & dpm_ni2f_fifo_h_reg_nwords_9 & dpm_ni2f_fifo_h_reg_nwords_8 & dpm_ni2f_fifo_h_reg_nwords_7;

--A1L17 is dpm_ni2f_fifo_h_modgen_eq_69_ix17~1
--operation mode is normal

A1L17 = dpm_ni2f_fifo_h_reg_nwords_10 & dpm_ni2f_fifo_h_reg_nwords_9 & dpm_ni2f_fifo_h_reg_nwords_8 & dpm_ni2f_fifo_h_reg_nwords_7;

--A1L27 is dpm_ni2f_fifo_h_modgen_eq_69_ix17~2
--operation mode is normal

A1L27 = dpm_ni2f_fifo_h_reg_nwords_10 & dpm_ni2f_fifo_h_reg_nwords_9 & dpm_ni2f_fifo_h_reg_nwords_8 & dpm_ni2f_fifo_h_reg_nwords_7;


--A1L37 is dpm_ni2f_fifo_h_modgen_eq_69_ix21~0
--operation mode is normal

A1L37 = (dpm_ni2f_fifo_h_reg_nwords_6 & dpm_ni2f_fifo_h_reg_nwords_5 & dpm_ni2f_fifo_h_reg_nwords_4 & dpm_ni2f_fifo_h_reg_nwords_3) & CASCADE(A1L27);

--A1L47 is dpm_ni2f_fifo_h_modgen_eq_69_ix21~2
--operation mode is normal

A1L47 = (dpm_ni2f_fifo_h_reg_nwords_6 & dpm_ni2f_fifo_h_reg_nwords_5 & dpm_ni2f_fifo_h_reg_nwords_4 & dpm_ni2f_fifo_h_reg_nwords_3) & CASCADE(A1L27);

--A1L57 is dpm_ni2f_fifo_h_modgen_eq_69_ix21~3
--operation mode is normal

A1L57 = (dpm_ni2f_fifo_h_reg_nwords_6 & dpm_ni2f_fifo_h_reg_nwords_5 & dpm_ni2f_fifo_h_reg_nwords_4 & dpm_ni2f_fifo_h_reg_nwords_3) & CASCADE(A1L27);


--M1_TS_DXFR_d_lc[2] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|TS_DXFR_d_lc[2]
--operation mode is normal

M1_TS_DXFR_d_lc[2] = AMPP_FUNCTION(M1_TS_DXFR, M1_TS_DISC_d_lc3);

--M1L525 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|TS_DXFR_d_lc[2]~46
--operation mode is normal

M1L525 = AMPP_FUNCTION(M1_TS_DXFR, M1_TS_DISC_d_lc3);


--M1_cfg_adr_dec_ena is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|cfg_adr_dec_ena
--operation mode is normal

M1_cfg_adr_dec_ena = AMPP_FUNCTION(M1_adr_phase_lc1, M1_cfg_adr_dec_ena_lc2, M1_cfg_adr_dec_ena_lc1);

--M1L751 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|cfg_adr_dec_ena~24
--operation mode is normal

M1L751 = AMPP_FUNCTION(M1_adr_phase_lc1, M1_cfg_adr_dec_ena_lc2, M1_cfg_adr_dec_ena_lc1);


--G1_mstr_cben_ir_ce_d is pci_contr:pci|pci_mt32:pci_mt32_inst|mstr_cben_ir_ce_d
--operation mode is normal

G1_mstr_cben_ir_ce_d = AMPP_FUNCTION(J1_MS_ENA, J1_MS_ADR, J1_MS_DXFR);

--G1L525 is pci_contr:pci|pci_mt32:pci_mt32_inst|mstr_cben_ir_ce_d~7
--operation mode is normal

G1L525 = AMPP_FUNCTION(J1_MS_ENA, J1_MS_ADR, J1_MS_DXFR);


--J1_no_op_reg[1] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|no_op_reg[1]
--operation mode is normal

J1_no_op_reg[1] = AMPP_FUNCTION(pci_rstn, GLOBAL(pci_clk));

--J1L665Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|no_op_reg[1]~19
--operation mode is normal

J1L665Q = AMPP_FUNCTION(pci_rstn, GLOBAL(pci_clk));


--J1_MR_LLWAIT_r1_carry is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LLWAIT_r1_carry
--operation mode is arithmetic

J1_MR_LLWAIT_r1_carry = AMPP_FUNCTION();

--J1L403 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LLWAIT_r1_carry~18
--operation mode is arithmetic

J1L403 = AMPP_FUNCTION();

--J1L503 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LLWAIT_r1_carry~COUT
--operation mode is arithmetic

J1L503 = AMPP_FUNCTION(A1L7421, J1_MR_LLWAIT_r1_lc1);


--J1_MR_LLWAIT_r2_carry is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LLWAIT_r2_carry
--operation mode is arithmetic

J1_MR_LLWAIT_r2_carry = AMPP_FUNCTION();

--J1L313 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LLWAIT_r2_carry~18
--operation mode is arithmetic

J1L313 = AMPP_FUNCTION();

--J1L413 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LLWAIT_r2_carry~COUT
--operation mode is arithmetic

J1L413 = AMPP_FUNCTION(A1L7421, J1_MR_LPXFR);


--J1_MR_LLXFR_r2_carry is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LLXFR_r2_carry
--operation mode is arithmetic

J1_MR_LLXFR_r2_carry = AMPP_FUNCTION();

--J1L623 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LLXFR_r2_carry~18
--operation mode is arithmetic

J1L623 = AMPP_FUNCTION();

--J1L723 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LLXFR_r2_carry~COUT
--operation mode is arithmetic

J1L723 = AMPP_FUNCTION(A1L7421, J1_MR_LLXFR_r2_d_lc1);


--J1_MR_LWAIT_carry is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LWAIT_carry
--operation mode is arithmetic

J1_MR_LWAIT_carry = AMPP_FUNCTION();

--J1L743 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LWAIT_carry~18
--operation mode is arithmetic

J1L743 = AMPP_FUNCTION();

--J1L843 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LWAIT_carry~COUT
--operation mode is arithmetic

J1L843 = AMPP_FUNCTION(A1L7421, J1_MR_LWAIT_lc1);


--M1L821 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|ad_ir_ce_D_lc1~41
--operation mode is normal

M1L821 = AMPP_FUNCTION(M1_TS_DISC, M1_TS_ADR_VLD, M1_TS_DXFR, M1_TS_ADR_CLMD);

--M1L031 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|ad_ir_ce_D_lc1~43
--operation mode is normal

M1L031 = AMPP_FUNCTION(M1_TS_DISC, M1_TS_ADR_VLD, M1_TS_DXFR, M1_TS_ADR_CLMD);


--M1_ad_ir_ce_D_lc1 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|ad_ir_ce_D_lc1
--operation mode is normal

M1_ad_ir_ce_D_lc1 = AMPP_FUNCTION(M1L821, M1_LW_WAIT);

--M1L131 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|ad_ir_ce_D_lc1~44
--operation mode is normal

M1L131 = AMPP_FUNCTION(M1L821, M1_LW_WAIT);


--J1_MW_IDLE_not is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_IDLE_not
--operation mode is normal

J1_MW_IDLE_not = AMPP_FUNCTION(J1_MW_END, J1_MW_IDLE_lc1, pci_gntn, J1_MW_IDLE_not, pci_rstn, GLOBAL(pci_clk));

--J1L884Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_IDLE_not~28
--operation mode is normal

J1L884Q = AMPP_FUNCTION(J1_MW_END, J1_MW_IDLE_lc1, pci_gntn, J1_MW_IDLE_not, pci_rstn, GLOBAL(pci_clk));


--J1_mstr_actv_lc is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|mstr_actv_lc
--operation mode is normal

J1_mstr_actv_lc = AMPP_FUNCTION(J1_MR_IDLE_not, J1_MW_IDLE_not);

--J1L424 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|mstr_actv_lc~8
--operation mode is normal

J1L424 = AMPP_FUNCTION(J1_MR_IDLE_not, J1_MW_IDLE_not);


--E1_counter_cell[9] is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[9]
--operation mode is up_dn_cntr

E1_counter_cell[9]_lut_out = E1_counter_cell[9] $ E1L82;
E1_counter_cell[9] = DFFEA(E1_counter_cell[9]_lut_out, GLOBAL(pci_clk), , , , , );

--E1L03Q is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[9]~5
--operation mode is up_dn_cntr

E1L03Q = E1_counter_cell[9];

--E1L13 is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[9]~COUT
--operation mode is up_dn_cntr

E1L13 = CARRY(E1_counter_cell[9] & (E1L82));


--M1_LR_PXFR_r1 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_PXFR_r1
--operation mode is normal

M1_LR_PXFR_r1 = AMPP_FUNCTION(M1L452, pci_rstn, GLOBAL(pci_clk), M1L962);

--M1L072Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_PXFR_r1~7
--operation mode is normal

M1L072Q = AMPP_FUNCTION(M1L452, pci_rstn, GLOBAL(pci_clk), M1L962);


--M1_LR_PXFR_r2 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_PXFR_r2
--operation mode is normal

M1_LR_PXFR_r2 = AMPP_FUNCTION(M1_LR_WAIT, M1_LR_PXFR_32, M1_LR_PXFR_lc[3], M1L35, pci_rstn, GLOBAL(pci_clk));

--M1L272Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_PXFR_r2~7
--operation mode is normal

M1L272Q = AMPP_FUNCTION(M1_LR_WAIT, M1_LR_PXFR_32, M1_LR_PXFR_lc[3], M1L35, pci_rstn, GLOBAL(pci_clk));


--M1_LR_PXFR is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_PXFR
--operation mode is normal

M1_LR_PXFR = AMPP_FUNCTION(M1_LR_PXFR_r1, M1_LR_PXFR_r2);

--M1L472 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_PXFR~15
--operation mode is normal

M1L472 = AMPP_FUNCTION(M1_LR_PXFR_r1, M1_LR_PXFR_r2);


--M1_LR_WAIT is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_WAIT
--operation mode is normal

M1_LR_WAIT = AMPP_FUNCTION(M1_LR_WAIT, M1_lt_rdynR, M1_LR_WAIT_lc[1], pci_rstn, GLOBAL(pci_clk), M1L75);

--M1L482Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_WAIT~43
--operation mode is normal

M1L482Q = AMPP_FUNCTION(M1_LR_WAIT, M1_lt_rdynR, M1_LR_WAIT_lc[1], pci_rstn, GLOBAL(pci_clk), M1L75);


--M1_lt_ack_R_r3_lc3 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_ack_R_r3_lc3
--operation mode is normal

M1_lt_ack_R_r3_lc3 = AMPP_FUNCTION(M1_LR_WAIT, M1_LR_PXFR_32, M1_lt_ack_R_r3_lc1, M1_lt_ack_R_r3_lc2);

--M1L723 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_ack_R_r3_lc3~19
--operation mode is normal

M1L723 = AMPP_FUNCTION(M1_LR_WAIT, M1_LR_PXFR_32, M1_lt_ack_R_r3_lc1, M1_lt_ack_R_r3_lc2);


--M1_retry is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|retry
--operation mode is normal

M1_retry = AMPP_FUNCTION(M1_retry_set, M1_retry, M1_retry_rst_lc2, pci_rstn, GLOBAL(pci_clk));

--M1L744Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|retry~18
--operation mode is normal

M1L744Q = AMPP_FUNCTION(M1_retry_set, M1_retry, M1_retry_rst_lc2, pci_rstn, GLOBAL(pci_clk));


--M1_lt_ack_R_r1_lc[6] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_ack_R_r1_lc[6]
--operation mode is normal

M1_lt_ack_R_r1_lc[6] = AMPP_FUNCTION(M1_lt_ack_R_r1_lc[5], K1_serr_or, M1_rd_backoff, M1_retry);

--M1L603 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_ack_R_r1_lc[6]~116
--operation mode is normal

M1L603 = AMPP_FUNCTION(M1_lt_ack_R_r1_lc[5], K1_serr_or, M1_rd_backoff, M1_retry);


--M1_LW_WAIT_carry is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LW_WAIT_carry
--operation mode is arithmetic

M1_LW_WAIT_carry = AMPP_FUNCTION();

--M1L614 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LW_WAIT_carry~23
--operation mode is arithmetic

M1L614 = AMPP_FUNCTION();

--M1L714 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LW_WAIT_carry~COUT
--operation mode is arithmetic

M1L714 = AMPP_FUNCTION(A1L5321, M1_LW_LXFR);


--M1_lt_ack_R_r1_lc[4] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_ack_R_r1_lc[4]
--operation mode is normal

M1_lt_ack_R_r1_lc[4] = AMPP_FUNCTION(M1_lt_ack_R_r1_lc[3], M1_lt_ack_R_r1_lc[1], M1_lt_ack_R_r1_lc[2]);

--M1L003 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_ack_R_r1_lc[4]~117
--operation mode is normal

M1L003 = AMPP_FUNCTION(M1_lt_ack_R_r1_lc[3], M1_lt_ack_R_r1_lc[1], M1_lt_ack_R_r1_lc[2]);


--M1_LR_LXFR_carry[2] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_LXFR_carry[2]
--operation mode is arithmetic

M1_LR_LXFR_carry[2] = AMPP_FUNCTION();

--M1L902 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_LXFR_carry[2]~38
--operation mode is arithmetic

M1L902 = AMPP_FUNCTION();

--M1L012 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_LXFR_carry[2]~COUT
--operation mode is arithmetic

M1L012 = AMPP_FUNCTION(A1L0321, A1L5321, M1L702);


--M1_LW_LXFR_lc[1] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LW_LXFR_lc[1]
--operation mode is normal

M1_LW_LXFR_lc[1] = AMPP_FUNCTION(M1L504, N3_REG, M1_cfg_cyc);

--M1L604 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LW_LXFR_lc[1]~78
--operation mode is normal

M1L604 = AMPP_FUNCTION(M1L504, N3_REG, M1_cfg_cyc);


--M1_TS_DISC_d_lc2 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|TS_DISC_d_lc2
--operation mode is normal

M1_TS_DISC_d_lc2 = AMPP_FUNCTION(M1_TS_DXFR, M1_TS_DISC_d_lc3);

--M1L715 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|TS_DISC_d_lc2~11
--operation mode is normal

M1L715 = AMPP_FUNCTION(M1_TS_DXFR, M1_TS_DISC_d_lc3);


--J1_DXFR_write_lc3 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|DXFR_write_lc3
--operation mode is normal

J1_DXFR_write_lc3 = AMPP_FUNCTION(J1_wr_rdn, J1_DXFR_write_lc1, J1_DXFR_write_lc2);

--J1L471 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|DXFR_write_lc3~23
--operation mode is normal

J1L471 = AMPP_FUNCTION(J1_wr_rdn, J1_DXFR_write_lc1, J1_DXFR_write_lc2);


--J1_DXFR_write_lc4 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|DXFR_write_lc4
--operation mode is normal

J1_DXFR_write_lc4 = AMPP_FUNCTION(J1_wr_rdn, J1_DXFR_write_lc4a);

--J1L971 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|DXFR_write_lc4~8
--operation mode is normal

J1L971 = AMPP_FUNCTION(J1_wr_rdn, J1_DXFR_write_lc4a);


--M1L7 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|$00106~0
--operation mode is normal

M1L7 = AMPP_FUNCTION(A1L5321, M1_wait_wait32_lc[4]);

--M1L8 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|$00106~10
--operation mode is normal

M1L8 = AMPP_FUNCTION(A1L5321, M1_wait_wait32_lc[4]);

--M1L9 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|$00106~11
--operation mode is normal

M1L9 = AMPP_FUNCTION(A1L5321, M1_wait_wait32_lc[4]);


--M1_no_op_reg[11] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[11]
--operation mode is normal

M1_no_op_reg[11] = AMPP_FUNCTION(pci_rstn, GLOBAL(pci_clk));

--M1L524Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|no_op_reg[11]~11
--operation mode is normal

M1L524Q = AMPP_FUNCTION(pci_rstn, GLOBAL(pci_clk));


--J1L7 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|$00109~15
--operation mode is normal

J1L7 = AMPP_FUNCTION(A1L5421, J1_WAIT_WAIT32_lc3, J1_MW_WAIT_32_d_lc_1d, A1L7421);

--J1L8 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|$00109~17
--operation mode is normal

J1L8 = AMPP_FUNCTION(A1L5421, J1_WAIT_WAIT32_lc3, J1_MW_WAIT_32_d_lc_1d, A1L7421);

--J1L9 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|$00109~18
--operation mode is normal

J1L9 = AMPP_FUNCTION(A1L5421, J1_WAIT_WAIT32_lc3, J1_MW_WAIT_32_d_lc_1d, A1L7421);


--ix2390 is ix2390
--operation mode is normal

ix2390 = M1_lt_adr[19] # M1_lt_adr[5] # !dpm_dec_reg_rdata_LED_0 # !M1_lt_adr[4];

--A1L179 is ix2390~1
--operation mode is normal

A1L179 = M1_lt_adr[19] # M1_lt_adr[5] # !dpm_dec_reg_rdata_LED_0 # !M1_lt_adr[4];

--A1L279 is ix2390~2
--operation mode is normal

A1L279 = M1_lt_adr[19] # M1_lt_adr[5] # !dpm_dec_reg_rdata_LED_0 # !M1_lt_adr[4];


--E2_q[0] is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[0]
--operation mode is clrb_cntr

E2_q[0]_lut_out = (ix2253_lc $ E2_q[0]) & VCC;
E2_q[0] = DFFEA(E2_q[0]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E2L76Q is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[0]~24
--operation mode is clrb_cntr

E2L76Q = E2_q[0];

--E2L3 is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT
--operation mode is clrb_cntr

E2L3 = CARRY(E2_q[0]);


--A1L268 is ix2348~0
--operation mode is normal

A1L268 = (!ix2431_lc # !ix2311_lc # !E2_q[0] # !M1_lt_adr[2]) & CASCADE(A1L279);

--A1L368 is ix2348~2
--operation mode is normal

A1L368 = (!ix2431_lc # !ix2311_lc # !E2_q[0] # !M1_lt_adr[2]) & CASCADE(A1L279);

--A1L468 is ix2348~3
--operation mode is normal

A1L468 = (!ix2431_lc # !ix2311_lc # !E2_q[0] # !M1_lt_adr[2]) & CASCADE(A1L279);


--G1_low_data_out_HR_lc is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR_lc
--operation mode is normal

G1_low_data_out_HR_lc = AMPP_FUNCTION(G1_trg_ad_sel, J1_MS_ENA);

--G1L205 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_HR_lc~15
--operation mode is normal

G1L205 = AMPP_FUNCTION(G1_trg_ad_sel, J1_MS_ENA);


--R1_decR[2] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|pcimt32_cd:cfg_adr_dec|decR[2]
--operation mode is normal

R1_decR[2] = AMPP_FUNCTION(M1_cfg_adr_dec_ena, R1_dec_up[0], G1_ad_ir_address[3], G1_ad_ir_address[2], pci_rstn, GLOBAL(pci_clk));

--R1L41Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|pcimt32_cd:cfg_adr_dec|decR[2]~128
--operation mode is normal

R1L41Q = AMPP_FUNCTION(M1_cfg_adr_dec_ena, R1_dec_up[0], G1_ad_ir_address[3], G1_ad_ir_address[2], pci_rstn, GLOBAL(pci_clk));


--P1_cache_line[0] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|cache_line[0]
--operation mode is normal

P1_cache_line[0] = AMPP_FUNCTION(P1L551, G1_low_ad_IR_data[0], pci_rstn, GLOBAL(pci_clk));

--P1L311Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|cache_line[0]~8
--operation mode is normal

P1L311Q = AMPP_FUNCTION(P1L551, G1_low_ad_IR_data[0], pci_rstn, GLOBAL(pci_clk));


--R1_decR[3] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|pcimt32_cd:cfg_adr_dec|decR[3]
--operation mode is normal

R1_decR[3] = AMPP_FUNCTION(M1_cfg_adr_dec_ena, G1_ad_ir_address[3], R1_dec_up[0], G1_ad_ir_address[2], pci_rstn, GLOBAL(pci_clk));

--R1L61Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|pcimt32_cd:cfg_adr_dec|decR[3]~129
--operation mode is normal

R1L61Q = AMPP_FUNCTION(M1_cfg_adr_dec_ena, G1_ad_ir_address[3], R1_dec_up[0], G1_ad_ir_address[2], pci_rstn, GLOBAL(pci_clk));


--P1L4 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|_~191
--operation mode is normal

P1L4 = AMPP_FUNCTION(P1_cache_line[0], R1_decR[3]);

--P1L11 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|_~1039
--operation mode is normal

P1L11 = AMPP_FUNCTION(P1_cache_line[0], R1_decR[3]);


--P1_cmd_reg[0] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|cmd_reg[0]
--operation mode is normal

P1_cmd_reg[0] = AMPP_FUNCTION(P1L771, G1_low_ad_IR_data[0], pci_rstn, GLOBAL(pci_clk));

--P1L031Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|cmd_reg[0]~10
--operation mode is normal

P1L031Q = AMPP_FUNCTION(P1L771, G1_low_ad_IR_data[0], pci_rstn, GLOBAL(pci_clk));


--G1_mstr_ADOR_ena is pci_contr:pci|pci_mt32:pci_mt32_inst|mstr_ADOR_ena
--operation mode is normal

G1_mstr_ADOR_ena = AMPP_FUNCTION(J1_MS_ENA, J1_wr_rdn, J1_mstr_actv_lc, J1_MW_LXFR);

--G1L125 is pci_contr:pci|pci_mt32:pci_mt32_inst|mstr_ADOR_ena~7
--operation mode is normal

G1L125 = AMPP_FUNCTION(J1_MS_ENA, J1_wr_rdn, J1_mstr_actv_lc, J1_MW_LXFR);


--M1_trg_OR_advance is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|trg_OR_advance
--operation mode is normal

M1_trg_OR_advance = AMPP_FUNCTION(M1_TS_ADR_CLMD, M1_TS_ADR_VLD, M1_cfg_cyc, N3_REG, pci_rstn, GLOBAL(pci_clk));

--M1L705Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|trg_OR_advance~23
--operation mode is normal

M1L705Q = AMPP_FUNCTION(M1_TS_ADR_CLMD, M1_TS_ADR_VLD, M1_cfg_cyc, N3_REG, pci_rstn, GLOBAL(pci_clk));


--G1_trg_ADOR_ena is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_ADOR_ena
--operation mode is normal

G1_trg_ADOR_ena = AMPP_FUNCTION(M1_LR_LXFR, M1_trg_OR_advance);

--G1L055 is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_ADOR_ena~7
--operation mode is normal

G1L055 = AMPP_FUNCTION(M1_LR_LXFR, M1_trg_OR_advance);


--J1_MS_REQ_d_lc[1] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MS_REQ_d_lc[1]
--operation mode is normal

J1_MS_REQ_d_lc[1] = AMPP_FUNCTION(J1_MS_REQ, J1_l_req_vld, J1_park, J1_MS_IDLE_not);

--J1L904 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MS_REQ_d_lc[1]~9
--operation mode is normal

J1L904 = AMPP_FUNCTION(J1_MS_REQ, J1_l_req_vld, J1_park, J1_MS_IDLE_not);


--J1_MS_REQ_d_lc[2] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MS_REQ_d_lc[2]
--operation mode is normal

J1_MS_REQ_d_lc[2] = AMPP_FUNCTION(J1_MS_ENA, J1_MS_PARK, J1_l_req_vld);

--J1L214 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MS_REQ_d_lc[2]~10
--operation mode is normal

J1L214 = AMPP_FUNCTION(J1_MS_ENA, J1_MS_PARK, J1_l_req_vld);


--J1_MS_IDLE_lc1 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MS_IDLE_lc1
--operation mode is normal

J1_MS_IDLE_lc1 = AMPP_FUNCTION(J1_MS_TAR, J1_l_req_vld, J1_MS_IDLE_not, J1_park);

--J1L004 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MS_IDLE_lc1~8
--operation mode is normal

J1L004 = AMPP_FUNCTION(J1_MS_TAR, J1_l_req_vld, J1_MS_IDLE_not, J1_park);


--ix2392 is ix2392
--operation mode is normal

ix2392 = M1_lt_adr[19] # M1_lt_adr[5] # !dpm_dec_reg_rdata_LED_1 # !M1_lt_adr[4];

--A1L779 is ix2392~1
--operation mode is normal

A1L779 = M1_lt_adr[19] # M1_lt_adr[5] # !dpm_dec_reg_rdata_LED_1 # !M1_lt_adr[4];

--A1L879 is ix2392~2
--operation mode is normal

A1L879 = M1_lt_adr[19] # M1_lt_adr[5] # !dpm_dec_reg_rdata_LED_1 # !M1_lt_adr[4];


--E2_q[1] is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[1]
--operation mode is clrb_cntr

E2_q[1]_lut_out = (E2_q[1] $ (ix2253_lc & E2L3)) & VCC;
E2_q[1] = DFFEA(E2_q[1]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E2L96Q is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[1]~25
--operation mode is clrb_cntr

E2L96Q = E2_q[1];

--E2L5 is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT
--operation mode is clrb_cntr

E2L5 = CARRY(E2_q[1] & (E2L3));


--A1L958 is ix2347~0
--operation mode is normal

A1L958 = (!ix2431_lc # !ix2311_lc # !E2_q[1] # !M1_lt_adr[2]) & CASCADE(A1L879);

--A1L068 is ix2347~2
--operation mode is normal

A1L068 = (!ix2431_lc # !ix2311_lc # !E2_q[1] # !M1_lt_adr[2]) & CASCADE(A1L879);

--A1L168 is ix2347~3
--operation mode is normal

A1L168 = (!ix2431_lc # !ix2311_lc # !E2_q[1] # !M1_lt_adr[2]) & CASCADE(A1L879);


--R1_decR[0] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|pcimt32_cd:cfg_adr_dec|decR[0]
--operation mode is normal

R1_decR[0] = AMPP_FUNCTION(M1_cfg_adr_dec_ena, R1_dec_up[0], G1_ad_ir_address[2], G1_ad_ir_address[3], pci_rstn, GLOBAL(pci_clk));

--R1L01Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|pcimt32_cd:cfg_adr_dec|decR[0]~130
--operation mode is normal

R1L01Q = AMPP_FUNCTION(M1_cfg_adr_dec_ena, R1_dec_up[0], G1_ad_ir_address[2], G1_ad_ir_address[3], pci_rstn, GLOBAL(pci_clk));


--P1_cache_line[1] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|cache_line[1]
--operation mode is normal

P1_cache_line[1] = AMPP_FUNCTION(P1L551, G1_low_ad_IR_data[1], pci_rstn, GLOBAL(pci_clk));

--P1L511Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|cache_line[1]~9
--operation mode is normal

P1L511Q = AMPP_FUNCTION(P1L551, G1_low_ad_IR_data[1], pci_rstn, GLOBAL(pci_clk));


--P1L3 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|_~190
--operation mode is normal

P1L3 = AMPP_FUNCTION(R1_decR[3], P1_cache_line[1]);

--P1L21 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|_~1040
--operation mode is normal

P1L21 = AMPP_FUNCTION(R1_decR[3], P1_cache_line[1]);


--ix2394 is ix2394
--operation mode is normal

ix2394 = M1_lt_adr[19] # M1_lt_adr[5] # !dpm_dec_reg_rdata_LED_2 # !M1_lt_adr[4];

--A1L389 is ix2394~1
--operation mode is normal

A1L389 = M1_lt_adr[19] # M1_lt_adr[5] # !dpm_dec_reg_rdata_LED_2 # !M1_lt_adr[4];

--A1L489 is ix2394~2
--operation mode is normal

A1L489 = M1_lt_adr[19] # M1_lt_adr[5] # !dpm_dec_reg_rdata_LED_2 # !M1_lt_adr[4];


--E2_q[2] is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[2]
--operation mode is clrb_cntr

E2_q[2]_lut_out = (E2_q[2] $ (ix2253_lc & E2L5)) & VCC;
E2_q[2] = DFFEA(E2_q[2]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E2L17Q is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[2]~26
--operation mode is clrb_cntr

E2L17Q = E2_q[2];

--E2L7 is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT
--operation mode is clrb_cntr

E2L7 = CARRY(E2_q[2] & (E2L5));


--A1L658 is ix2346~0
--operation mode is normal

A1L658 = (!ix2431_lc # !ix2311_lc # !E2_q[2] # !M1_lt_adr[2]) & CASCADE(A1L489);

--A1L758 is ix2346~2
--operation mode is normal

A1L758 = (!ix2431_lc # !ix2311_lc # !E2_q[2] # !M1_lt_adr[2]) & CASCADE(A1L489);

--A1L858 is ix2346~3
--operation mode is normal

A1L858 = (!ix2431_lc # !ix2311_lc # !E2_q[2] # !M1_lt_adr[2]) & CASCADE(A1L489);


--P1_cache_line[2] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|cache_line[2]
--operation mode is normal

P1_cache_line[2] = AMPP_FUNCTION(P1L551, G1_low_ad_IR_data[2], pci_rstn, GLOBAL(pci_clk));

--P1L711Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|cache_line[2]~10
--operation mode is normal

P1L711Q = AMPP_FUNCTION(P1L551, G1_low_ad_IR_data[2], pci_rstn, GLOBAL(pci_clk));


--ix2396 is ix2396
--operation mode is normal

ix2396 = M1_lt_adr[19] # M1_lt_adr[5] # !dpm_dec_reg_rdata_LED_3 # !M1_lt_adr[4];

--A1L989 is ix2396~1
--operation mode is normal

A1L989 = M1_lt_adr[19] # M1_lt_adr[5] # !dpm_dec_reg_rdata_LED_3 # !M1_lt_adr[4];

--A1L099 is ix2396~2
--operation mode is normal

A1L099 = M1_lt_adr[19] # M1_lt_adr[5] # !dpm_dec_reg_rdata_LED_3 # !M1_lt_adr[4];


--E2_q[3] is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[3]
--operation mode is clrb_cntr

E2_q[3]_lut_out = (E2_q[3] $ (ix2253_lc & E2L7)) & VCC;
E2_q[3] = DFFEA(E2_q[3]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E2L37Q is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[3]~27
--operation mode is clrb_cntr

E2L37Q = E2_q[3];

--E2L9 is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT
--operation mode is clrb_cntr

E2L9 = CARRY(E2_q[3] & (E2L7));


--A1L358 is ix2345~0
--operation mode is normal

A1L358 = (!ix2431_lc # !ix2311_lc # !E2_q[3] # !M1_lt_adr[2]) & CASCADE(A1L099);

--A1L458 is ix2345~2
--operation mode is normal

A1L458 = (!ix2431_lc # !ix2311_lc # !E2_q[3] # !M1_lt_adr[2]) & CASCADE(A1L099);

--A1L558 is ix2345~3
--operation mode is normal

A1L558 = (!ix2431_lc # !ix2311_lc # !E2_q[3] # !M1_lt_adr[2]) & CASCADE(A1L099);


--P1_cache_line[3] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|cache_line[3]
--operation mode is normal

P1_cache_line[3] = AMPP_FUNCTION(P1L551, G1_low_ad_IR_data[3], pci_rstn, GLOBAL(pci_clk));

--P1L911Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|cache_line[3]~11
--operation mode is normal

P1L911Q = AMPP_FUNCTION(P1L551, G1_low_ad_IR_data[3], pci_rstn, GLOBAL(pci_clk));


--ix2398 is ix2398
--operation mode is normal

ix2398 = M1_lt_adr[19] # M1_lt_adr[5] # !dpm_dec_reg_rdata_LED_4 # !M1_lt_adr[4];

--A1L599 is ix2398~1
--operation mode is normal

A1L599 = M1_lt_adr[19] # M1_lt_adr[5] # !dpm_dec_reg_rdata_LED_4 # !M1_lt_adr[4];

--A1L699 is ix2398~2
--operation mode is normal

A1L699 = M1_lt_adr[19] # M1_lt_adr[5] # !dpm_dec_reg_rdata_LED_4 # !M1_lt_adr[4];


--E2_q[4] is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[4]
--operation mode is clrb_cntr

E2_q[4]_lut_out = (E2_q[4] $ (ix2253_lc & E2L9)) & VCC;
E2_q[4] = DFFEA(E2_q[4]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E2L57Q is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[4]~28
--operation mode is clrb_cntr

E2L57Q = E2_q[4];

--E2L11 is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[4]~COUT
--operation mode is clrb_cntr

E2L11 = CARRY(E2_q[4] & (E2L9));


--A1L058 is ix2344~0
--operation mode is normal

A1L058 = (!ix2431_lc # !ix2311_lc # !E2_q[4] # !M1_lt_adr[2]) & CASCADE(A1L699);

--A1L158 is ix2344~2
--operation mode is normal

A1L158 = (!ix2431_lc # !ix2311_lc # !E2_q[4] # !M1_lt_adr[2]) & CASCADE(A1L699);

--A1L258 is ix2344~3
--operation mode is normal

A1L258 = (!ix2431_lc # !ix2311_lc # !E2_q[4] # !M1_lt_adr[2]) & CASCADE(A1L699);


--P1_cache_line[4] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|cache_line[4]
--operation mode is normal

P1_cache_line[4] = AMPP_FUNCTION(P1L551, G1_low_ad_IR_data[4], pci_rstn, GLOBAL(pci_clk));

--P1L121Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|cache_line[4]~12
--operation mode is normal

P1L121Q = AMPP_FUNCTION(P1L551, G1_low_ad_IR_data[4], pci_rstn, GLOBAL(pci_clk));


--P1L2 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|_~187
--operation mode is normal

P1L2 = AMPP_FUNCTION(R1_decR[3], P1_cache_line[4]);

--P1L31 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|_~1041
--operation mode is normal

P1L31 = AMPP_FUNCTION(R1_decR[3], P1_cache_line[4]);


--P1_cmd_reg[4] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|cmd_reg[4]
--operation mode is normal

P1_cmd_reg[4] = AMPP_FUNCTION(P1L771, G1_low_ad_IR_data[4], pci_rstn, GLOBAL(pci_clk));

--P1L631Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|cmd_reg[4]~11
--operation mode is normal

P1L631Q = AMPP_FUNCTION(P1L771, G1_low_ad_IR_data[4], pci_rstn, GLOBAL(pci_clk));


--ix2400 is ix2400
--operation mode is normal

ix2400 = M1_lt_adr[19] # M1_lt_adr[5] # !dpm_dec_reg_rdata_LED_5 # !M1_lt_adr[4];

--A1L1001 is ix2400~1
--operation mode is normal

A1L1001 = M1_lt_adr[19] # M1_lt_adr[5] # !dpm_dec_reg_rdata_LED_5 # !M1_lt_adr[4];

--A1L2001 is ix2400~2
--operation mode is normal

A1L2001 = M1_lt_adr[19] # M1_lt_adr[5] # !dpm_dec_reg_rdata_LED_5 # !M1_lt_adr[4];


--E2_q[5] is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[5]
--operation mode is clrb_cntr

E2_q[5]_lut_out = (E2_q[5] $ (ix2253_lc & E2L11)) & VCC;
E2_q[5] = DFFEA(E2_q[5]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E2L77Q is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[5]~29
--operation mode is clrb_cntr

E2L77Q = E2_q[5];

--E2L31 is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[5]~COUT
--operation mode is clrb_cntr

E2L31 = CARRY(E2_q[5] & (E2L11));


--A1L748 is ix2343~0
--operation mode is normal

A1L748 = (!ix2431_lc # !ix2311_lc # !E2_q[5] # !M1_lt_adr[2]) & CASCADE(A1L2001);

--A1L848 is ix2343~2
--operation mode is normal

A1L848 = (!ix2431_lc # !ix2311_lc # !E2_q[5] # !M1_lt_adr[2]) & CASCADE(A1L2001);

--A1L948 is ix2343~3
--operation mode is normal

A1L948 = (!ix2431_lc # !ix2311_lc # !E2_q[5] # !M1_lt_adr[2]) & CASCADE(A1L2001);


--P1_cache_line[5] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|cache_line[5]
--operation mode is normal

P1_cache_line[5] = AMPP_FUNCTION(P1L551, G1_low_ad_IR_data[5], pci_rstn, GLOBAL(pci_clk));

--P1L321Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|cache_line[5]~13
--operation mode is normal

P1L321Q = AMPP_FUNCTION(P1L551, G1_low_ad_IR_data[5], pci_rstn, GLOBAL(pci_clk));


--ix2402 is ix2402
--operation mode is normal

ix2402 = M1_lt_adr[19] # M1_lt_adr[5] # !dpm_dec_reg_rdata_LED_6 # !M1_lt_adr[4];

--A1L7001 is ix2402~1
--operation mode is normal

A1L7001 = M1_lt_adr[19] # M1_lt_adr[5] # !dpm_dec_reg_rdata_LED_6 # !M1_lt_adr[4];

--A1L8001 is ix2402~2
--operation mode is normal

A1L8001 = M1_lt_adr[19] # M1_lt_adr[5] # !dpm_dec_reg_rdata_LED_6 # !M1_lt_adr[4];


--E2_q[6] is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[6]
--operation mode is clrb_cntr

E2_q[6]_lut_out = (E2_q[6] $ (ix2253_lc & E2L31)) & VCC;
E2_q[6] = DFFEA(E2_q[6]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E2L97Q is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[6]~30
--operation mode is clrb_cntr

E2L97Q = E2_q[6];

--E2L51 is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[6]~COUT
--operation mode is clrb_cntr

E2L51 = CARRY(E2_q[6] & (E2L31));


--A1L448 is ix2342~0
--operation mode is normal

A1L448 = (!ix2431_lc # !ix2311_lc # !E2_q[6] # !M1_lt_adr[2]) & CASCADE(A1L8001);

--A1L548 is ix2342~2
--operation mode is normal

A1L548 = (!ix2431_lc # !ix2311_lc # !E2_q[6] # !M1_lt_adr[2]) & CASCADE(A1L8001);

--A1L648 is ix2342~3
--operation mode is normal

A1L648 = (!ix2431_lc # !ix2311_lc # !E2_q[6] # !M1_lt_adr[2]) & CASCADE(A1L8001);


--P1_cache_line[6] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|cache_line[6]
--operation mode is normal

P1_cache_line[6] = AMPP_FUNCTION(P1L551, G1_low_ad_IR_data[6], pci_rstn, GLOBAL(pci_clk));

--P1L521Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|cache_line[6]~14
--operation mode is normal

P1L521Q = AMPP_FUNCTION(P1L551, G1_low_ad_IR_data[6], pci_rstn, GLOBAL(pci_clk));


--P1L1 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|_~185
--operation mode is normal

P1L1 = AMPP_FUNCTION(R1_decR[3], P1_cache_line[6]);

--P1L41 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|_~1042
--operation mode is normal

P1L41 = AMPP_FUNCTION(R1_decR[3], P1_cache_line[6]);


--ix2404 is ix2404
--operation mode is normal

ix2404 = M1_lt_adr[19] # M1_lt_adr[5] # !dpm_dec_reg_rdata_LED_7 # !M1_lt_adr[4];

--A1L3101 is ix2404~1
--operation mode is normal

A1L3101 = M1_lt_adr[19] # M1_lt_adr[5] # !dpm_dec_reg_rdata_LED_7 # !M1_lt_adr[4];

--A1L4101 is ix2404~2
--operation mode is normal

A1L4101 = M1_lt_adr[19] # M1_lt_adr[5] # !dpm_dec_reg_rdata_LED_7 # !M1_lt_adr[4];


--E2_q[7] is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[7]
--operation mode is clrb_cntr

E2_q[7]_lut_out = (E2_q[7] $ (ix2253_lc & E2L51)) & VCC;
E2_q[7] = DFFEA(E2_q[7]_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--E2L18Q is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|q[7]~31
--operation mode is clrb_cntr

E2L18Q = E2_q[7];

--E2L71 is lpm_counter:dpm_ni2f_des_dv1_err1_cnt_ix9|alt_counter_f10ke:wysi_counter|counter_cell[7]~COUT
--operation mode is clrb_cntr

E2L71 = CARRY(E2_q[7] & (E2L51));


--A1L148 is ix2341~0
--operation mode is normal

A1L148 = (!ix2431_lc # !ix2311_lc # !E2_q[7] # !M1_lt_adr[2]) & CASCADE(A1L4101);

--A1L248 is ix2341~2
--operation mode is normal

A1L248 = (!ix2431_lc # !ix2311_lc # !E2_q[7] # !M1_lt_adr[2]) & CASCADE(A1L4101);

--A1L348 is ix2341~3
--operation mode is normal

A1L348 = (!ix2431_lc # !ix2311_lc # !E2_q[7] # !M1_lt_adr[2]) & CASCADE(A1L4101);


--P1_cache_line[7] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|cache_line[7]
--operation mode is normal

P1_cache_line[7] = AMPP_FUNCTION(P1L551, G1_low_ad_IR_data[7], pci_rstn, GLOBAL(pci_clk));

--P1L721Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|cache_line[7]~15
--operation mode is normal

P1L721Q = AMPP_FUNCTION(P1L551, G1_low_ad_IR_data[7], pci_rstn, GLOBAL(pci_clk));


--dpm_ni2f_reg_en_valid_cnt is dpm_ni2f_reg_en_valid_cnt
--operation mode is normal

dpm_ni2f_reg_en_valid_cnt_lut_out = dpm_ni2f_reg_des_valid_data;
dpm_ni2f_reg_en_valid_cnt = DFFEA(dpm_ni2f_reg_en_valid_cnt_lut_out, lcst, !dpm_ni2f_reg_sreset120, , , , );

--A1L314Q is dpm_ni2f_reg_en_valid_cnt~1
--operation mode is normal

A1L314Q = dpm_ni2f_reg_en_valid_cnt;


--ix2252_lc is ix2252_lc
--operation mode is normal

ix2252_lc = !E3_q[31] & dpm_ni2f_reg_en_valid_cnt;

--A1L795 is ix2252_lc~0
--operation mode is normal

A1L795 = !E3_q[31] & dpm_ni2f_reg_en_valid_cnt;


--ix2431_lc is ix2431_lc
--operation mode is normal

ix2431_lc = !M1_lt_adr[19] & M1_lt_adr[3];

--A1L5901 is ix2431_lc~0
--operation mode is normal

A1L5901 = !M1_lt_adr[19] & M1_lt_adr[3];


--P1_lat_tmr_reg[0] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|lat_tmr_reg[0]
--operation mode is normal

P1_lat_tmr_reg[0] = AMPP_FUNCTION(P1L751, G1_low_ad_IR_data[11], pci_rstn, GLOBAL(pci_clk));

--P1L641Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|lat_tmr_reg[0]~5
--operation mode is normal

P1L641Q = AMPP_FUNCTION(P1L751, G1_low_ad_IR_data[11], pci_rstn, GLOBAL(pci_clk));


--P1_lat_tmr_reg[1] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|lat_tmr_reg[1]
--operation mode is normal

P1_lat_tmr_reg[1] = AMPP_FUNCTION(P1L751, G1_low_ad_IR_data[12], pci_rstn, GLOBAL(pci_clk));

--P1L841Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|lat_tmr_reg[1]~6
--operation mode is normal

P1L841Q = AMPP_FUNCTION(P1L751, G1_low_ad_IR_data[12], pci_rstn, GLOBAL(pci_clk));


--P1_lat_tmr_reg[2] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|lat_tmr_reg[2]
--operation mode is normal

P1_lat_tmr_reg[2] = AMPP_FUNCTION(P1L751, G1_low_ad_IR_data[13], pci_rstn, GLOBAL(pci_clk));

--P1L051Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|lat_tmr_reg[2]~7
--operation mode is normal

P1L051Q = AMPP_FUNCTION(P1L751, G1_low_ad_IR_data[13], pci_rstn, GLOBAL(pci_clk));


--P1_lat_tmr_reg[3] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|lat_tmr_reg[3]
--operation mode is normal

P1_lat_tmr_reg[3] = AMPP_FUNCTION(P1L751, G1_low_ad_IR_data[14], pci_rstn, GLOBAL(pci_clk));

--P1L251Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|lat_tmr_reg[3]~8
--operation mode is normal

P1L251Q = AMPP_FUNCTION(P1L751, G1_low_ad_IR_data[14], pci_rstn, GLOBAL(pci_clk));


--P1_lat_tmr_reg[4] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|lat_tmr_reg[4]
--operation mode is normal

P1_lat_tmr_reg[4] = AMPP_FUNCTION(P1L751, G1_low_ad_IR_data[15], pci_rstn, GLOBAL(pci_clk));

--P1L451Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|lat_tmr_reg[4]~9
--operation mode is normal

P1L451Q = AMPP_FUNCTION(P1L751, G1_low_ad_IR_data[15], pci_rstn, GLOBAL(pci_clk));


--P1_bar0_reg[20] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|bar0_reg[20]
--operation mode is normal

P1_bar0_reg[20] = AMPP_FUNCTION(P1L57, G1_low_ad_IR_data[20], pci_rstn, GLOBAL(pci_clk));

--P1L18Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|bar0_reg[20]~12
--operation mode is normal

P1L18Q = AMPP_FUNCTION(P1L57, G1_low_ad_IR_data[20], pci_rstn, GLOBAL(pci_clk));


--R1_decR[4] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|pcimt32_cd:cfg_adr_dec|decR[4]
--operation mode is normal

R1_decR[4] = AMPP_FUNCTION(M1_cfg_adr_dec_ena, R1_dec_up[1], G1_ad_ir_address[2], G1_ad_ir_address[3], pci_rstn, GLOBAL(pci_clk));

--R1L81Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|pcimt32_cd:cfg_adr_dec|decR[4]~131
--operation mode is normal

R1L81Q = AMPP_FUNCTION(M1_cfg_adr_dec_ena, R1_dec_up[1], G1_ad_ir_address[2], G1_ad_ir_address[3], pci_rstn, GLOBAL(pci_clk));


--P1_bar0_reg[21] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|bar0_reg[21]
--operation mode is normal

P1_bar0_reg[21] = AMPP_FUNCTION(P1L57, G1_low_ad_IR_data[21], pci_rstn, GLOBAL(pci_clk));

--P1L38Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|bar0_reg[21]~13
--operation mode is normal

P1L38Q = AMPP_FUNCTION(P1L57, G1_low_ad_IR_data[21], pci_rstn, GLOBAL(pci_clk));


--P1_bar0_reg[22] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|bar0_reg[22]
--operation mode is normal

P1_bar0_reg[22] = AMPP_FUNCTION(P1L57, G1_low_ad_IR_data[22], pci_rstn, GLOBAL(pci_clk));

--P1L58Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|bar0_reg[22]~14
--operation mode is normal

P1L58Q = AMPP_FUNCTION(P1L57, G1_low_ad_IR_data[22], pci_rstn, GLOBAL(pci_clk));


--P1_bar0_reg[23] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|bar0_reg[23]
--operation mode is normal

P1_bar0_reg[23] = AMPP_FUNCTION(P1L57, G1_low_ad_IR_data[23], pci_rstn, GLOBAL(pci_clk));

--P1L78Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|bar0_reg[23]~15
--operation mode is normal

P1L78Q = AMPP_FUNCTION(P1L57, G1_low_ad_IR_data[23], pci_rstn, GLOBAL(pci_clk));


--dpm_ni2f_reg_des_dv1_err1 is dpm_ni2f_reg_des_dv1_err1
--operation mode is normal

dpm_ni2f_reg_des_dv1_err1_lut_out = dpm_ni2f_reg_des_en_r & dpm_ni2f_reg_des_er_r;
dpm_ni2f_reg_des_dv1_err1 = DFFEA(dpm_ni2f_reg_des_dv1_err1_lut_out, lcst, , , , , );

--A1L304Q is dpm_ni2f_reg_des_dv1_err1~0
--operation mode is normal

A1L304Q = dpm_ni2f_reg_des_dv1_err1;


--ix2253_lc is ix2253_lc
--operation mode is normal

ix2253_lc = dpm_ni2f_reg_des_dv1_err1 & !E2_q[31];

--A1L006 is ix2253_lc~0
--operation mode is normal

A1L006 = dpm_ni2f_reg_des_dv1_err1 & !E2_q[31];


--A1L877 is ix2320~0
--operation mode is normal

A1L877 = (!M1_lt_adr[19] & M1_lt_adr[3] & M1_lt_adr[2]) & CASCADE(A1L357);

--A1L977 is ix2320~1
--operation mode is normal

A1L977 = (!M1_lt_adr[19] & M1_lt_adr[3] & M1_lt_adr[2]) & CASCADE(A1L357);


--P1_bar0_reg[24] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|bar0_reg[24]
--operation mode is normal

P1_bar0_reg[24] = AMPP_FUNCTION(P1L77, G1_low_ad_IR_data[24], pci_rstn, GLOBAL(pci_clk));

--P1L98Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|bar0_reg[24]~16
--operation mode is normal

P1L98Q = AMPP_FUNCTION(P1L77, G1_low_ad_IR_data[24], pci_rstn, GLOBAL(pci_clk));


--P1L9 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|_~231
--operation mode is normal

P1L9 = AMPP_FUNCTION(R1_decR[4], P1_bar0_reg[24]);

--P1L51 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|_~1043
--operation mode is normal

P1L51 = AMPP_FUNCTION(R1_decR[4], P1_bar0_reg[24]);


--P1_stat_reg[8] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|stat_reg[8]
--operation mode is normal

P1_stat_reg[8] = AMPP_FUNCTION(J1_perr_rep_setR, P1_stat_reg[8], P1_par_rep_rst, pci_rstn, GLOBAL(pci_clk));

--P1L381Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|stat_reg[8]~0
--operation mode is normal

P1L381Q = AMPP_FUNCTION(J1_perr_rep_setR, P1_stat_reg[8], P1_par_rep_rst, pci_rstn, GLOBAL(pci_clk));


--P1_bar0_reg[25] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|bar0_reg[25]
--operation mode is normal

P1_bar0_reg[25] = AMPP_FUNCTION(P1L77, G1_low_ad_IR_data[25], pci_rstn, GLOBAL(pci_clk));

--P1L19Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|bar0_reg[25]~17
--operation mode is normal

P1L19Q = AMPP_FUNCTION(P1L77, G1_low_ad_IR_data[25], pci_rstn, GLOBAL(pci_clk));


--P1_bar0_reg[26] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|bar0_reg[26]
--operation mode is normal

P1_bar0_reg[26] = AMPP_FUNCTION(P1L77, G1_low_ad_IR_data[26], pci_rstn, GLOBAL(pci_clk));

--P1L39Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|bar0_reg[26]~18
--operation mode is normal

P1L39Q = AMPP_FUNCTION(P1L77, G1_low_ad_IR_data[26], pci_rstn, GLOBAL(pci_clk));


--P1_bar0_reg[27] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|bar0_reg[27]
--operation mode is normal

P1_bar0_reg[27] = AMPP_FUNCTION(P1L77, G1_low_ad_IR_data[27], pci_rstn, GLOBAL(pci_clk));

--P1L59Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|bar0_reg[27]~19
--operation mode is normal

P1L59Q = AMPP_FUNCTION(P1L77, G1_low_ad_IR_data[27], pci_rstn, GLOBAL(pci_clk));


--P1_bar0_reg[28] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|bar0_reg[28]
--operation mode is normal

P1_bar0_reg[28] = AMPP_FUNCTION(P1L77, G1_low_ad_IR_data[28], pci_rstn, GLOBAL(pci_clk));

--P1L79Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|bar0_reg[28]~20
--operation mode is normal

P1L79Q = AMPP_FUNCTION(P1L77, G1_low_ad_IR_data[28], pci_rstn, GLOBAL(pci_clk));


--P1L8 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|_~227
--operation mode is normal

P1L8 = AMPP_FUNCTION(R1_decR[4], P1_bar0_reg[28]);

--P1L61 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|_~1044
--operation mode is normal

P1L61 = AMPP_FUNCTION(R1_decR[4], P1_bar0_reg[28]);


--N5_REG is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|pcimt32_sr:$00213|REG
--operation mode is normal

N5_REG = AMPP_FUNCTION(J1_tabrt_set, N5_REG, P1_targ_abrt_rcvd_rst, pci_rstn, GLOBAL(pci_clk));

--N5L2Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|pcimt32_sr:$00213|REG~1
--operation mode is normal

N5L2Q = AMPP_FUNCTION(J1_tabrt_set, N5_REG, P1_targ_abrt_rcvd_rst, pci_rstn, GLOBAL(pci_clk));


--P1_bar0_reg[29] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|bar0_reg[29]
--operation mode is normal

P1_bar0_reg[29] = AMPP_FUNCTION(P1L77, G1_low_ad_IR_data[29], pci_rstn, GLOBAL(pci_clk));

--P1L99Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|bar0_reg[29]~21
--operation mode is normal

P1L99Q = AMPP_FUNCTION(P1L77, G1_low_ad_IR_data[29], pci_rstn, GLOBAL(pci_clk));


--P1L7 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|_~226
--operation mode is normal

P1L7 = AMPP_FUNCTION(R1_decR[4], P1_bar0_reg[29]);

--P1L71 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|_~1045
--operation mode is normal

P1L71 = AMPP_FUNCTION(R1_decR[4], P1_bar0_reg[29]);


--N6_REG is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|pcimt32_sr:$00215|REG
--operation mode is normal

N6_REG = AMPP_FUNCTION(J1_mstr_abrt_set, N6_REG, P1_mstr_abrt_rst, pci_rstn, GLOBAL(pci_clk));

--N6L2Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|pcimt32_sr:$00215|REG~1
--operation mode is normal

N6L2Q = AMPP_FUNCTION(J1_mstr_abrt_set, N6_REG, P1_mstr_abrt_rst, pci_rstn, GLOBAL(pci_clk));


--P1_bar0_reg[30] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|bar0_reg[30]
--operation mode is normal

P1_bar0_reg[30] = AMPP_FUNCTION(P1L77, G1_low_ad_IR_data[30], pci_rstn, GLOBAL(pci_clk));

--P1L101Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|bar0_reg[30]~22
--operation mode is normal

P1L101Q = AMPP_FUNCTION(P1L77, G1_low_ad_IR_data[30], pci_rstn, GLOBAL(pci_clk));


--P1L6 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|_~225
--operation mode is normal

P1L6 = AMPP_FUNCTION(R1_decR[4], P1_bar0_reg[30]);

--P1L81 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|_~1046
--operation mode is normal

P1L81 = AMPP_FUNCTION(R1_decR[4], P1_bar0_reg[30]);


--N7_REG is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|pcimt32_sr:$00217|REG
--operation mode is normal

N7_REG = AMPP_FUNCTION(K1_serr_or, N7_REG, P1_serr_rst, pci_rstn, GLOBAL(pci_clk));

--N7L2Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|pcimt32_sr:$00217|REG~1
--operation mode is normal

N7L2Q = AMPP_FUNCTION(K1_serr_or, N7_REG, P1_serr_rst, pci_rstn, GLOBAL(pci_clk));


--P1_bar0_reg[31] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|bar0_reg[31]
--operation mode is normal

P1_bar0_reg[31] = AMPP_FUNCTION(P1L77, G1_low_ad_IR_data[31], pci_rstn, GLOBAL(pci_clk));

--P1L301Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|bar0_reg[31]~23
--operation mode is normal

P1L301Q = AMPP_FUNCTION(P1L77, G1_low_ad_IR_data[31], pci_rstn, GLOBAL(pci_clk));


--P1L5 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|_~224
--operation mode is normal

P1L5 = AMPP_FUNCTION(R1_decR[4], P1_bar0_reg[31]);

--P1L91 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|_~1047
--operation mode is normal

P1L91 = AMPP_FUNCTION(R1_decR[4], P1_bar0_reg[31]);


--N8_REG is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|pcimt32_sr:$00219|REG
--operation mode is normal

N8_REG = AMPP_FUNCTION(K1_perr_det_setR_r1, K1_perr_det_setR_r3, N8_REG, P1_perr_det_rst, pci_rstn, GLOBAL(pci_clk));

--N8L2Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|pcimt32_sr:$00219|REG~13
--operation mode is normal

N8L2Q = AMPP_FUNCTION(K1_perr_det_setR_r1, K1_perr_det_setR_r3, N8_REG, P1_perr_det_rst, pci_rstn, GLOBAL(pci_clk));


--J1_lm_adr_ack_R_lc1 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lm_adr_ack_R_lc1
--operation mode is normal

J1_lm_adr_ack_R_lc1 = AMPP_FUNCTION(J1_MS_REQ, J1_park, J1_lm_adr_ack_R, J1_MS_ENA);

--J1L672 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lm_adr_ack_R_lc1~11
--operation mode is normal

J1L672 = AMPP_FUNCTION(J1_MS_REQ, J1_park, J1_lm_adr_ack_R, J1_MS_ENA);


--J1_lm_adr_ack_R_lc2 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lm_adr_ack_R_lc2
--operation mode is normal

J1_lm_adr_ack_R_lc2 = AMPP_FUNCTION(J1_MS_PARK, J1_MR_IDLE_not);

--J1L972 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lm_adr_ack_R_lc2~8
--operation mode is normal

J1L972 = AMPP_FUNCTION(J1_MS_PARK, J1_MR_IDLE_not);


--M1L95 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|_~74
--operation mode is normal

M1L95 = AMPP_FUNCTION(M1_trdy_OR_NOT, M1_stop_OR_NOT, M1_TS_DISC);

--M1L001 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|_~1509
--operation mode is normal

M1L001 = AMPP_FUNCTION(M1_trdy_OR_NOT, M1_stop_OR_NOT, M1_TS_DISC);

--M1L101 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|_~1510
--operation mode is normal

M1L101 = AMPP_FUNCTION(M1_trdy_OR_NOT, M1_stop_OR_NOT, M1_TS_DISC);


--M1L57 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|_~448
--operation mode is normal

M1L57 = AMPP_FUNCTION(M1_trdy_OR_NOT, M1_TS_DXFR);

--M1L201 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|_~1511
--operation mode is normal

M1L201 = AMPP_FUNCTION(M1_trdy_OR_NOT, M1_TS_DXFR);

--M1L301 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|_~1512
--operation mode is normal

M1L301 = AMPP_FUNCTION(M1_trdy_OR_NOT, M1_TS_DXFR);


--M1L905 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|TS_ADR_CLMD_d~37
--operation mode is normal

M1L905 = AMPP_FUNCTION(M1_TS_ADR_CLMD, M1_cfg_cyc, J1_mstr_actv_lc, dpm_dec_reg_LT_RDY_n_pci);

--M1L015 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|TS_ADR_CLMD_d~38
--operation mode is normal

M1L015 = AMPP_FUNCTION(M1_TS_ADR_CLMD, M1_cfg_cyc, J1_mstr_actv_lc, dpm_dec_reg_LT_RDY_n_pci);


--M1L1 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|$00083~0
--operation mode is normal

M1L1 = AMPP_FUNCTION(M1_idsel_IR, G1_cben_ir_address[3], G1_cben_ir_address[1], G1_cben_ir_address[2]);

--M1L2 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|$00083~10
--operation mode is normal

M1L2 = AMPP_FUNCTION(M1_idsel_IR, G1_cben_ir_address[3], G1_cben_ir_address[1], G1_cben_ir_address[2]);

--M1L3 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|$00083~11
--operation mode is normal

M1L3 = AMPP_FUNCTION(M1_idsel_IR, G1_cben_ir_address[3], G1_cben_ir_address[1], G1_cben_ir_address[2]);


--M1L861 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|cfg_type0_cyc~21
--operation mode is normal

M1L861 = AMPP_FUNCTION(M1_adr_phase_lc1, G1_ad_ir_address[1], G1_ad_ir_address[0], M1L3);

--M1L961 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|cfg_type0_cyc~22
--operation mode is normal

M1L961 = AMPP_FUNCTION(M1_adr_phase_lc1, G1_ad_ir_address[1], G1_ad_ir_address[0], M1L3);


--P1_mem_cyc is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|mem_cyc
--operation mode is normal

P1_mem_cyc = AMPP_FUNCTION(G1_cben_ir_address[2], G1_cben_ir_address[1], G1_cben_ir_address[3], G1_cben_ir_address[0]);

--P1L461 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|mem_cyc~15
--operation mode is normal

P1L461 = AMPP_FUNCTION(G1_cben_ir_address[2], G1_cben_ir_address[1], G1_cben_ir_address[3], G1_cben_ir_address[0]);


--U31_aeb_out is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|lpm_compare:bar0_comp|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|cmpchain:cmp_end|aeb_out
--operation mode is normal

U31_aeb_out = AMPP_FUNCTION(U11_aeb_out, U21_aeb_out);

--U31L3 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|lpm_compare:bar0_comp|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~8
--operation mode is normal

U31L3 = AMPP_FUNCTION(U11_aeb_out, U21_aeb_out);


--U9_aeb_out is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|lpm_compare:bar0_comp|comptree:comparator|cmpchain:cmp[0]|comptree:comp|comptree:sub_comptree|cmpchain:cmp_end|aeb_out
--operation mode is normal

U9_aeb_out = AMPP_FUNCTION(U8_aeb_out, U7_aeb_out, U5_aeb_out, U6_aeb_out);

--U9L3 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|lpm_compare:bar0_comp|comptree:comparator|cmpchain:cmp[0]|comptree:comp|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~26
--operation mode is normal

U9L3 = AMPP_FUNCTION(U8_aeb_out, U7_aeb_out, U5_aeb_out, U6_aeb_out);


--J1_frame_or_lc3 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|frame_or_lc3
--operation mode is normal

J1_frame_or_lc3 = AMPP_FUNCTION(J1_frame_or_lc3a, J1_last_xfr, J1_frame_or_lc3b, J1_frame_or_lc3c);

--J1L212 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|frame_or_lc3~11
--operation mode is normal

J1L212 = AMPP_FUNCTION(J1_frame_or_lc3a, J1_last_xfr, J1_frame_or_lc3b, J1_frame_or_lc3c);


--J1_frame_or_lc1a is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|frame_or_lc1a
--operation mode is normal

J1_frame_or_lc1a = AMPP_FUNCTION(J1_MR_LLXFR_r1, J1_MR_LLXFR_r2, J1_MS_DXFR, J1_devsel_toR);

--J1L681 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|frame_or_lc1a~20
--operation mode is normal

J1L681 = AMPP_FUNCTION(J1_MR_LLXFR_r1, J1_MR_LLXFR_r2, J1_MS_DXFR, J1_devsel_toR);


--J1_adr_phase is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|adr_phase
--operation mode is normal

J1_adr_phase = AMPP_FUNCTION(J1_MS_ADR, J1_dac_cyc_reg, J1_MS_ENA, pci_gntn, pci_rstn, GLOBAL(pci_clk));

--J1L821Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|adr_phase~4
--operation mode is normal

J1L821Q = AMPP_FUNCTION(J1_MS_ADR, J1_dac_cyc_reg, J1_MS_ENA, pci_gntn, pci_rstn, GLOBAL(pci_clk));


--J1_frame_or_lc1c is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|frame_or_lc1c
--operation mode is normal

J1_frame_or_lc1c = AMPP_FUNCTION(J1_adr_phase, J1_wr_rdn, J1_MR_IDLE_not);

--J1L091 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|frame_or_lc1c~4
--operation mode is normal

J1L091 = AMPP_FUNCTION(J1_adr_phase, J1_wr_rdn, J1_MR_IDLE_not);


--J1_MW_LXFR_r[2] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_LXFR_r[2]
--operation mode is normal

J1_MW_LXFR_r[2] = AMPP_FUNCTION(J1_MW_LXFR_lc[3], pci_gntn, pci_rstn, GLOBAL(pci_clk));

--J1L525Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_LXFR_r[2]~14
--operation mode is normal

J1L525Q = AMPP_FUNCTION(J1_MW_LXFR_lc[3], pci_gntn, pci_rstn, GLOBAL(pci_clk));


--J1_MW_LXFR_r[1] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_LXFR_r[1]
--operation mode is normal

J1_MW_LXFR_r[1] = AMPP_FUNCTION(J1_MW_LXFR_lc[1], A1L5421, J1_MW_LXFR_lc[2], pci_rstn, GLOBAL(pci_clk), J1L125);

--J1L325Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_LXFR_r[1]~15
--operation mode is normal

J1L325Q = AMPP_FUNCTION(J1_MW_LXFR_lc[1], A1L5421, J1_MW_LXFR_lc[2], pci_rstn, GLOBAL(pci_clk), J1L125);


--J1_MW_LXFR is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_LXFR
--operation mode is normal

J1_MW_LXFR = AMPP_FUNCTION(J1_MW_LXFR_r[2], J1_MW_LXFR_r[1]);

--J1L725 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_LXFR~7
--operation mode is normal

J1L725 = AMPP_FUNCTION(J1_MW_LXFR_r[2], J1_MW_LXFR_r[1]);


--J1_MR_PXFR_r1 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_PXFR_r1
--operation mode is normal

J1_MR_PXFR_r1 = AMPP_FUNCTION(A1L5421, J1_MR_PXFR_lc2, J1_MR_PXFR_lc1, J1_last_xfr, pci_rstn, GLOBAL(pci_clk));

--J1L363Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_PXFR_r1~7
--operation mode is normal

J1L363Q = AMPP_FUNCTION(A1L5421, J1_MR_PXFR_lc2, J1_MR_PXFR_lc1, J1_last_xfr, pci_rstn, GLOBAL(pci_clk));


--J1_MR_PXFR_r2 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_PXFR_r2
--operation mode is normal

J1_MR_PXFR_r2 = AMPP_FUNCTION(A1L5421, J1_MR_PXFR, J1_devsel_toR, pci_rstn, GLOBAL(pci_clk), J1L56);

--J1L563Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_PXFR_r2~7
--operation mode is normal

J1L563Q = AMPP_FUNCTION(A1L5421, J1_MR_PXFR, J1_devsel_toR, pci_rstn, GLOBAL(pci_clk), J1L56);


--J1_MR_PXFR is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_PXFR
--operation mode is normal

J1_MR_PXFR = AMPP_FUNCTION(J1_MR_PXFR_r1, J1_MR_PXFR_r2);

--J1L763 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_PXFR~15
--operation mode is normal

J1L763 = AMPP_FUNCTION(J1_MR_PXFR_r1, J1_MR_PXFR_r2);


--J1_MW_DXFR_r4 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_DXFR_r4
--operation mode is normal

J1_MW_DXFR_r4 = AMPP_FUNCTION(A1L5421, J1_lm_rdynR, J1_MW_DXFR, J1_last_xfr, pci_rstn, GLOBAL(pci_clk), J1L83);

--J1L654Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_DXFR_r4~7
--operation mode is normal

J1L654Q = AMPP_FUNCTION(A1L5421, J1_lm_rdynR, J1_MW_DXFR, J1_last_xfr, pci_rstn, GLOBAL(pci_clk), J1L83);


--J1_MW_DXFR_r1 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_DXFR_r1
--operation mode is normal

J1_MW_DXFR_r1 = AMPP_FUNCTION(A1L5421, J1_MW_DXFR_lc[1], J1_MW_DXFR_lc[2], J1_last_xfr, pci_rstn, GLOBAL(pci_clk), J1L23);

--J1L254Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_DXFR_r1~7
--operation mode is normal

J1L254Q = AMPP_FUNCTION(A1L5421, J1_MW_DXFR_lc[1], J1_MW_DXFR_lc[2], J1_last_xfr, pci_rstn, GLOBAL(pci_clk), J1L23);


--J1_MW_DXFR_r2 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_DXFR_r2
--operation mode is normal

J1_MW_DXFR_r2 = AMPP_FUNCTION(J1_last_xfr, J1_lm_rdynR, pci_rstn, GLOBAL(pci_clk), J1L53);

--J1L454Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_DXFR_r2~7
--operation mode is normal

J1L454Q = AMPP_FUNCTION(J1_last_xfr, J1_lm_rdynR, pci_rstn, GLOBAL(pci_clk), J1L53);


--J1_MW_DXFR is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_DXFR
--operation mode is normal

J1_MW_DXFR = AMPP_FUNCTION(J1_MW_DXFR_r4, J1_MW_DXFR_r1, J1_MW_DXFR_r2);

--J1L954 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_DXFR~37
--operation mode is normal

J1L954 = AMPP_FUNCTION(J1_MW_DXFR_r4, J1_MW_DXFR_r1, J1_MW_DXFR_r2);

--J1L854 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_DXFR~36
--operation mode is normal

J1L854 = AMPP_FUNCTION(J1_MW_DXFR_r4, J1_MW_DXFR_r1, J1_MW_DXFR_r2);


--J1_MR_LPXFR_r1 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LPXFR_r1
--operation mode is normal

J1_MR_LPXFR_r1 = AMPP_FUNCTION(J1L333, A1L5421, J1_MR_LPXFR_lc2, pci_rstn, GLOBAL(pci_clk), J1L143);

--J1L243Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LPXFR_r1~0
--operation mode is normal

J1L243Q = AMPP_FUNCTION(J1L333, A1L5421, J1_MR_LPXFR_lc2, pci_rstn, GLOBAL(pci_clk), J1L143);


--J1L84 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|$00200~0
--operation mode is normal

J1L84 = AMPP_FUNCTION(A1L8221, J1_no_op_reg[1]);

--J1L94 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|$00200~10
--operation mode is normal

J1L94 = AMPP_FUNCTION(A1L8221, J1_no_op_reg[1]);

--J1L05 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|$00200~11
--operation mode is normal

J1L05 = AMPP_FUNCTION(A1L8221, J1_no_op_reg[1]);


--J1L37 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|_~445
--operation mode is normal

J1L37 = AMPP_FUNCTION(J1_MS_DXFR, J1_devsel_toR);

--J1L49 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|_~1148
--operation mode is normal

J1L49 = AMPP_FUNCTION(J1_MS_DXFR, J1_devsel_toR);

--J1L59 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|_~1149
--operation mode is normal

J1L59 = AMPP_FUNCTION(J1_MS_DXFR, J1_devsel_toR);


--J1L51 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|$00136~10
--operation mode is normal

J1L51 = AMPP_FUNCTION(J1_irdy_or_lc[3], J1_irdy_or_lc[1], J1_irdy_or_lc[2], J1L59);

--J1L61 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|$00136~12
--operation mode is normal

J1L61 = AMPP_FUNCTION(J1_irdy_or_lc[3], J1_irdy_or_lc[1], J1_irdy_or_lc[2], J1L59);

--J1L71 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|$00136~13
--operation mode is normal

J1L71 = AMPP_FUNCTION(J1_irdy_or_lc[3], J1_irdy_or_lc[1], J1_irdy_or_lc[2], J1L59);


--J1_ms_dxfr_lc1c is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|ms_dxfr_lc1c
--operation mode is normal

J1_ms_dxfr_lc1c = AMPP_FUNCTION(J1_MS_DXFR, J1_irdy_or_not, J1_frame_or_not, J1_mstr_abrt);

--J1L583 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|ms_dxfr_lc1c~32
--operation mode is normal

J1L583 = AMPP_FUNCTION(J1_MS_DXFR, J1_irdy_or_not, J1_frame_or_not, J1_mstr_abrt);


--J1_ms_dxfr_lc1a is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|ms_dxfr_lc1a
--operation mode is normal

J1_ms_dxfr_lc1a = AMPP_FUNCTION(J1_MS_ADR2, J1_MS_ADR, J1_dac_cyc_reg);

--J1L973 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|ms_dxfr_lc1a~9
--operation mode is normal

J1L973 = AMPP_FUNCTION(J1_MS_ADR2, J1_MS_ADR, J1_dac_cyc_reg);


--J1_ms_dxfr_lc1b is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|ms_dxfr_lc1b
--operation mode is normal

J1_ms_dxfr_lc1b = AMPP_FUNCTION(J1_irdy_or_not, J1_MS_DXFR, J1_frame_or_not);

--J1L283 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|ms_dxfr_lc1b~31
--operation mode is normal

J1L283 = AMPP_FUNCTION(J1_irdy_or_not, J1_MS_DXFR, J1_frame_or_not);


--J1_no_op_reg[6] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|no_op_reg[6]
--operation mode is normal

J1_no_op_reg[6] = AMPP_FUNCTION(pci_rstn, GLOBAL(pci_clk));

--J1L675Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|no_op_reg[6]~20
--operation mode is normal

J1L675Q = AMPP_FUNCTION(pci_rstn, GLOBAL(pci_clk));


--J1_MR_END_carry is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_END_carry
--operation mode is arithmetic

J1_MR_END_carry = AMPP_FUNCTION();

--J1L582 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_END_carry~18
--operation mode is arithmetic

J1L582 = AMPP_FUNCTION();

--J1L682 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_END_carry~COUT
--operation mode is arithmetic

J1L682 = AMPP_FUNCTION(A1L7421, J1_MR_END_d_lc2);


--J1_MR_IDLE_lc1 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_IDLE_lc1
--operation mode is normal

J1_MR_IDLE_lc1 = AMPP_FUNCTION(J1_MS_ADR2, J1_MS_ADR, J1_dac_cyc_reg, J1_wr_rdn);

--J1L792 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_IDLE_lc1~26
--operation mode is normal

J1L792 = AMPP_FUNCTION(J1_MS_ADR2, J1_MS_ADR, J1_dac_cyc_reg, J1_wr_rdn);

--J1L692 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_IDLE_lc1~25
--operation mode is normal

J1L692 = AMPP_FUNCTION(J1_MS_ADR2, J1_MS_ADR, J1_dac_cyc_reg, J1_wr_rdn);


--M1L28 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|_~1471
--operation mode is normal

M1L28 = AMPP_FUNCTION(M1_LW_WAIT, dpm_dec_reg_LT_RDY_n_pci, M1_TS_DXFR);

--M1L401 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|_~1513
--operation mode is normal

M1L401 = AMPP_FUNCTION(M1_LW_WAIT, dpm_dec_reg_LT_RDY_n_pci, M1_TS_DXFR);


--M1_LW_DONE_lc[2] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LW_DONE_lc[2]
--operation mode is normal

M1_LW_DONE_lc[2] = AMPP_FUNCTION(M1L28, M1_TS_TURN_AR, M1_LW_LXFR);

--M1L583 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LW_DONE_lc[2]~16
--operation mode is normal

M1L583 = AMPP_FUNCTION(M1L28, M1_TS_TURN_AR, M1_LW_LXFR);


--M1_LR_DONE is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_DONE
--operation mode is normal

M1_LR_DONE = AMPP_FUNCTION(A1L0321, M1_LR_DONE_lc[2], M1_LR_DONE_lc[1], pci_rstn, GLOBAL(pci_clk));

--M1L591Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_DONE~19
--operation mode is normal

M1L591Q = AMPP_FUNCTION(A1L0321, M1_LR_DONE_lc[2], M1_LR_DONE_lc[1], pci_rstn, GLOBAL(pci_clk));


--M1_LR_IDLE_NOT is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_IDLE_NOT
--operation mode is normal

M1_LR_IDLE_NOT = AMPP_FUNCTION(M1_LR_DONE, M1_LR_IDLE_NOT, M1_LR_IDLE_lc1, pci_rstn, GLOBAL(pci_clk));

--M1L202Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_IDLE_NOT~11
--operation mode is normal

M1L202Q = AMPP_FUNCTION(M1_LR_DONE, M1_LR_IDLE_NOT, M1_LR_IDLE_lc1, pci_rstn, GLOBAL(pci_clk));


--M1_$00153 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|$00153
--operation mode is normal

M1_$00153 = AMPP_FUNCTION(M1_TS_DISC, M1_LR_DONE, M1_LR_IDLE_NOT, M1_trdy_OR_NOT);

--M1L03 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|$00153~27
--operation mode is normal

M1L03 = AMPP_FUNCTION(M1_TS_DISC, M1_LR_DONE, M1_LR_IDLE_NOT, M1_trdy_OR_NOT);


--M1_burst_trans_carry is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|burst_trans_carry
--operation mode is arithmetic

M1_burst_trans_carry = AMPP_FUNCTION();

--M1L541 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|burst_trans_carry~18
--operation mode is arithmetic

M1L541 = AMPP_FUNCTION();

--M1L641 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|burst_trans_carry~COUT
--operation mode is arithmetic

M1L641 = AMPP_FUNCTION(A1L5321, M1_no_op_reg[1]);


--M1L06 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|_~82
--operation mode is normal

M1L06 = AMPP_FUNCTION(M1_cfg_cyc, M1_TS_ADR_CLMD, M1_retry);

--M1L501 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|_~1514
--operation mode is normal

M1L501 = AMPP_FUNCTION(M1_cfg_cyc, M1_TS_ADR_CLMD, M1_retry);

--M1L601 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|_~1515
--operation mode is normal

M1L601 = AMPP_FUNCTION(M1_cfg_cyc, M1_TS_ADR_CLMD, M1_retry);


--M1L22 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|$00149~10
--operation mode is normal

M1L22 = AMPP_FUNCTION(M1_TS_ADR_CLMD, M1_trdy_OR_lc[4], M1_retry, M1L601);

--M1L32 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|$00149~12
--operation mode is normal

M1L32 = AMPP_FUNCTION(M1_TS_ADR_CLMD, M1_trdy_OR_lc[4], M1_retry, M1L601);

--M1L42 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|$00149~13
--operation mode is normal

M1L42 = AMPP_FUNCTION(M1_TS_ADR_CLMD, M1_trdy_OR_lc[4], M1_retry, M1L601);


--M1_trdy_OR_lc[3] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|trdy_OR_lc[3]
--operation mode is normal

M1_trdy_OR_lc[3] = AMPP_FUNCTION(M1_trdy_OR_lc[2], M1_trdy_or_cc3);

--M1L894 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|trdy_OR_lc[3]~84
--operation mode is normal

M1L894 = AMPP_FUNCTION(M1_trdy_OR_lc[2], M1_trdy_or_cc3);


--dpm_dec_reg_tmp3 is dpm_dec_reg_tmp3
--operation mode is normal

dpm_dec_reg_tmp3_lut_out = dpm_dec_reg_tmp2;
dpm_dec_reg_tmp3 = DFFEA(dpm_dec_reg_tmp3_lut_out, GLOBAL(pci_clk), pci_rstn, , , , );

--A1L86Q is dpm_dec_reg_tmp3~1
--operation mode is normal

A1L86Q = dpm_dec_reg_tmp3;


--M1_LR_WAIT_32 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_WAIT_32
--operation mode is normal

M1_LR_WAIT_32 = AMPP_FUNCTION(M1_LR_WAIT_32, M1_LR_WAIT_32_lc1, pci_rstn, GLOBAL(pci_clk), M1L511);

--M1L082Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_WAIT_32~28
--operation mode is normal

M1L082Q = AMPP_FUNCTION(M1_LR_WAIT_32, M1_LR_WAIT_32_lc1, pci_rstn, GLOBAL(pci_clk), M1L511);


--M1L16 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|_~84
--operation mode is normal

M1L16 = AMPP_FUNCTION(M1_LR_WAIT, M1_LR_PXFR_32, M1_LR_WAIT_32);

--M1L701 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|_~1516
--operation mode is normal

M1L701 = AMPP_FUNCTION(M1_LR_WAIT, M1_LR_PXFR_32, M1_LR_WAIT_32);

--M1L801 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|_~1517
--operation mode is normal

M1L801 = AMPP_FUNCTION(M1_LR_WAIT, M1_LR_PXFR_32, M1_LR_WAIT_32);


--M1_LR_PXFR_lc[3] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_PXFR_lc[3]
--operation mode is normal

M1_LR_PXFR_lc[3] = AMPP_FUNCTION(M1_lt_rdynR, M1_LR_PXFR, M1_TS_DISC);

--M1L162 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_PXFR_lc[3]~36
--operation mode is normal

M1L162 = AMPP_FUNCTION(M1_lt_rdynR, M1_LR_PXFR, M1_TS_DISC);


--ix2285_lc is ix2285_lc
--operation mode is normal

ix2285_lc = dpm_ni2f_reg_rdreq_fifo & dpm_ni2f_fifo_l_reg_fifo_empty & (dpm_ni2f_fifo_l_reg_fifo_full # !dpm_ni2f_reg_des_valid_data) # !dpm_ni2f_reg_rdreq_fifo & dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_l_reg_fifo_full;

--A1L386 is ix2285_lc~0
--operation mode is normal

A1L386 = dpm_ni2f_reg_rdreq_fifo & dpm_ni2f_fifo_l_reg_fifo_empty & (dpm_ni2f_fifo_l_reg_fifo_full # !dpm_ni2f_reg_des_valid_data) # !dpm_ni2f_reg_rdreq_fifo & dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_l_reg_fifo_full;


--ix2284_lc is ix2284_lc
--operation mode is normal

ix2284_lc = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_l_reg_fifo_full & (!dpm_ni2f_fifo_l_reg_fifo_empty # !dpm_ni2f_reg_rdreq_fifo) # !dpm_ni2f_reg_des_valid_data & dpm_ni2f_reg_rdreq_fifo & (dpm_ni2f_fifo_l_reg_fifo_empty);

--A1L086 is ix2284_lc~0
--operation mode is normal

A1L086 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_l_reg_fifo_full & (!dpm_ni2f_fifo_l_reg_fifo_empty # !dpm_ni2f_reg_rdreq_fifo) # !dpm_ni2f_reg_des_valid_data & dpm_ni2f_reg_rdreq_fifo & (dpm_ni2f_fifo_l_reg_fifo_empty);


--ix2367 is ix2367
--operation mode is normal

ix2367 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_h_reg_fifo_full # !dpm_ni2f_fifo_h_result_dec_80_ix67_lc # !dpm_ni2f_reg_rdreq_fifo;

--A1L609 is ix2367~1
--operation mode is normal

A1L609 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_h_reg_fifo_full # !dpm_ni2f_fifo_h_result_dec_80_ix67_lc # !dpm_ni2f_reg_rdreq_fifo;

--A1L709 is ix2367~2
--operation mode is normal

A1L709 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_h_reg_fifo_full # !dpm_ni2f_fifo_h_result_dec_80_ix67_lc # !dpm_ni2f_reg_rdreq_fifo;


--A1L396 is ix2289~0
--operation mode is normal

A1L396 = (!ix2319_lc # !dpm_ni2f_fifo_h_result_inc_82_ix67_lc) & CASCADE(A1L709);

--A1L496 is ix2289~1
--operation mode is normal

A1L496 = (!ix2319_lc # !dpm_ni2f_fifo_h_result_inc_82_ix67_lc) & CASCADE(A1L709);


--dpm_ni2f_fifo_h_result_dec_80_ix63_carry_sum is dpm_ni2f_fifo_h_result_dec_80_ix63_carry_sum
--operation mode is arithmetic

dpm_ni2f_fifo_h_result_dec_80_ix63_carry_sum = dpm_ni2f_fifo_h_reg_nwords_9 $ (!A1L141);

--A1L341 is dpm_ni2f_fifo_h_result_dec_80_ix63_carry_sum~12
--operation mode is arithmetic

A1L341 = dpm_ni2f_fifo_h_reg_nwords_9 $ (!A1L141);

--A1L441 is dpm_ni2f_fifo_h_result_dec_80_ix63_carry_sum~COUT
--operation mode is arithmetic

A1L441 = CARRY(dpm_ni2f_fifo_h_reg_nwords_9 # A1L141);


--ix2366 is ix2366
--operation mode is normal

ix2366 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_h_reg_fifo_full # !dpm_ni2f_fifo_h_result_dec_80_ix63_carry_sum # !dpm_ni2f_reg_rdreq_fifo;

--A1L309 is ix2366~1
--operation mode is normal

A1L309 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_h_reg_fifo_full # !dpm_ni2f_fifo_h_result_dec_80_ix63_carry_sum # !dpm_ni2f_reg_rdreq_fifo;

--A1L409 is ix2366~2
--operation mode is normal

A1L409 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_h_reg_fifo_full # !dpm_ni2f_fifo_h_result_dec_80_ix63_carry_sum # !dpm_ni2f_reg_rdreq_fifo;


--dpm_ni2f_fifo_h_result_inc_82_ix63_carry_sum is dpm_ni2f_fifo_h_result_inc_82_ix63_carry_sum
--operation mode is arithmetic

dpm_ni2f_fifo_h_result_inc_82_ix63_carry_sum = dpm_ni2f_fifo_h_reg_nwords_9 $ (A1L771);

--A1L971 is dpm_ni2f_fifo_h_result_inc_82_ix63_carry_sum~12
--operation mode is arithmetic

A1L971 = dpm_ni2f_fifo_h_reg_nwords_9 $ (A1L771);

--A1L081 is dpm_ni2f_fifo_h_result_inc_82_ix63_carry_sum~COUT
--operation mode is arithmetic

A1L081 = CARRY(dpm_ni2f_fifo_h_reg_nwords_9 & (A1L771));


--A1L596 is ix2290~0
--operation mode is normal

A1L596 = (!ix2319_lc # !dpm_ni2f_fifo_h_result_inc_82_ix63_carry_sum) & CASCADE(A1L409);

--A1L696 is ix2290~1
--operation mode is normal

A1L696 = (!ix2319_lc # !dpm_ni2f_fifo_h_result_inc_82_ix63_carry_sum) & CASCADE(A1L409);


--dpm_ni2f_fifo_h_result_dec_80_ix59_carry_sum is dpm_ni2f_fifo_h_result_dec_80_ix59_carry_sum
--operation mode is arithmetic

dpm_ni2f_fifo_h_result_dec_80_ix59_carry_sum = dpm_ni2f_fifo_h_reg_nwords_8 $ (!A1L831);

--A1L041 is dpm_ni2f_fifo_h_result_dec_80_ix59_carry_sum~12
--operation mode is arithmetic

A1L041 = dpm_ni2f_fifo_h_reg_nwords_8 $ (!A1L831);

--A1L141 is dpm_ni2f_fifo_h_result_dec_80_ix59_carry_sum~COUT
--operation mode is arithmetic

A1L141 = CARRY(dpm_ni2f_fifo_h_reg_nwords_8 # A1L831);


--ix2365 is ix2365
--operation mode is normal

ix2365 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_h_reg_fifo_full # !dpm_ni2f_fifo_h_result_dec_80_ix59_carry_sum # !dpm_ni2f_reg_rdreq_fifo;

--A1L009 is ix2365~1
--operation mode is normal

A1L009 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_h_reg_fifo_full # !dpm_ni2f_fifo_h_result_dec_80_ix59_carry_sum # !dpm_ni2f_reg_rdreq_fifo;

--A1L109 is ix2365~2
--operation mode is normal

A1L109 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_h_reg_fifo_full # !dpm_ni2f_fifo_h_result_dec_80_ix59_carry_sum # !dpm_ni2f_reg_rdreq_fifo;


--dpm_ni2f_fifo_h_result_inc_82_ix59_carry_sum is dpm_ni2f_fifo_h_result_inc_82_ix59_carry_sum
--operation mode is arithmetic

dpm_ni2f_fifo_h_result_inc_82_ix59_carry_sum = dpm_ni2f_fifo_h_reg_nwords_8 $ (A1L471);

--A1L671 is dpm_ni2f_fifo_h_result_inc_82_ix59_carry_sum~12
--operation mode is arithmetic

A1L671 = dpm_ni2f_fifo_h_reg_nwords_8 $ (A1L471);

--A1L771 is dpm_ni2f_fifo_h_result_inc_82_ix59_carry_sum~COUT
--operation mode is arithmetic

A1L771 = CARRY(dpm_ni2f_fifo_h_reg_nwords_8 & (A1L471));


--A1L796 is ix2291~0
--operation mode is normal

A1L796 = (!ix2319_lc # !dpm_ni2f_fifo_h_result_inc_82_ix59_carry_sum) & CASCADE(A1L109);

--A1L896 is ix2291~1
--operation mode is normal

A1L896 = (!ix2319_lc # !dpm_ni2f_fifo_h_result_inc_82_ix59_carry_sum) & CASCADE(A1L109);


--dpm_ni2f_fifo_h_result_dec_80_ix55_carry_sum is dpm_ni2f_fifo_h_result_dec_80_ix55_carry_sum
--operation mode is arithmetic

dpm_ni2f_fifo_h_result_dec_80_ix55_carry_sum = dpm_ni2f_fifo_h_reg_nwords_7 $ (!A1L531);

--A1L731 is dpm_ni2f_fifo_h_result_dec_80_ix55_carry_sum~12
--operation mode is arithmetic

A1L731 = dpm_ni2f_fifo_h_reg_nwords_7 $ (!A1L531);

--A1L831 is dpm_ni2f_fifo_h_result_dec_80_ix55_carry_sum~COUT
--operation mode is arithmetic

A1L831 = CARRY(dpm_ni2f_fifo_h_reg_nwords_7 # A1L531);


--ix2364 is ix2364
--operation mode is normal

ix2364 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_h_reg_fifo_full # !dpm_ni2f_fifo_h_result_dec_80_ix55_carry_sum # !dpm_ni2f_reg_rdreq_fifo;

--A1L798 is ix2364~1
--operation mode is normal

A1L798 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_h_reg_fifo_full # !dpm_ni2f_fifo_h_result_dec_80_ix55_carry_sum # !dpm_ni2f_reg_rdreq_fifo;

--A1L898 is ix2364~2
--operation mode is normal

A1L898 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_h_reg_fifo_full # !dpm_ni2f_fifo_h_result_dec_80_ix55_carry_sum # !dpm_ni2f_reg_rdreq_fifo;


--dpm_ni2f_fifo_h_result_inc_82_ix55_carry_sum is dpm_ni2f_fifo_h_result_inc_82_ix55_carry_sum
--operation mode is arithmetic

dpm_ni2f_fifo_h_result_inc_82_ix55_carry_sum = dpm_ni2f_fifo_h_reg_nwords_7 $ (A1L171);

--A1L371 is dpm_ni2f_fifo_h_result_inc_82_ix55_carry_sum~12
--operation mode is arithmetic

A1L371 = dpm_ni2f_fifo_h_reg_nwords_7 $ (A1L171);

--A1L471 is dpm_ni2f_fifo_h_result_inc_82_ix55_carry_sum~COUT
--operation mode is arithmetic

A1L471 = CARRY(dpm_ni2f_fifo_h_reg_nwords_7 & (A1L171));


--A1L996 is ix2292~0
--operation mode is normal

A1L996 = (!ix2319_lc # !dpm_ni2f_fifo_h_result_inc_82_ix55_carry_sum) & CASCADE(A1L898);

--A1L007 is ix2292~1
--operation mode is normal

A1L007 = (!ix2319_lc # !dpm_ni2f_fifo_h_result_inc_82_ix55_carry_sum) & CASCADE(A1L898);


--dpm_ni2f_fifo_h_result_dec_80_ix51_carry_sum is dpm_ni2f_fifo_h_result_dec_80_ix51_carry_sum
--operation mode is arithmetic

dpm_ni2f_fifo_h_result_dec_80_ix51_carry_sum = dpm_ni2f_fifo_h_reg_nwords_6 $ (!A1L231);

--A1L431 is dpm_ni2f_fifo_h_result_dec_80_ix51_carry_sum~12
--operation mode is arithmetic

A1L431 = dpm_ni2f_fifo_h_reg_nwords_6 $ (!A1L231);

--A1L531 is dpm_ni2f_fifo_h_result_dec_80_ix51_carry_sum~COUT
--operation mode is arithmetic

A1L531 = CARRY(dpm_ni2f_fifo_h_reg_nwords_6 # A1L231);


--ix2363 is ix2363
--operation mode is normal

ix2363 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_h_reg_fifo_full # !dpm_ni2f_fifo_h_result_dec_80_ix51_carry_sum # !dpm_ni2f_reg_rdreq_fifo;

--A1L498 is ix2363~1
--operation mode is normal

A1L498 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_h_reg_fifo_full # !dpm_ni2f_fifo_h_result_dec_80_ix51_carry_sum # !dpm_ni2f_reg_rdreq_fifo;

--A1L598 is ix2363~2
--operation mode is normal

A1L598 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_h_reg_fifo_full # !dpm_ni2f_fifo_h_result_dec_80_ix51_carry_sum # !dpm_ni2f_reg_rdreq_fifo;


--dpm_ni2f_fifo_h_result_inc_82_ix51_carry_sum is dpm_ni2f_fifo_h_result_inc_82_ix51_carry_sum
--operation mode is arithmetic

dpm_ni2f_fifo_h_result_inc_82_ix51_carry_sum = dpm_ni2f_fifo_h_reg_nwords_6 $ (A1L861);

--A1L071 is dpm_ni2f_fifo_h_result_inc_82_ix51_carry_sum~12
--operation mode is arithmetic

A1L071 = dpm_ni2f_fifo_h_reg_nwords_6 $ (A1L861);

--A1L171 is dpm_ni2f_fifo_h_result_inc_82_ix51_carry_sum~COUT
--operation mode is arithmetic

A1L171 = CARRY(dpm_ni2f_fifo_h_reg_nwords_6 & (A1L861));


--A1L107 is ix2293~0
--operation mode is normal

A1L107 = (!ix2319_lc # !dpm_ni2f_fifo_h_result_inc_82_ix51_carry_sum) & CASCADE(A1L598);

--A1L207 is ix2293~1
--operation mode is normal

A1L207 = (!ix2319_lc # !dpm_ni2f_fifo_h_result_inc_82_ix51_carry_sum) & CASCADE(A1L598);


--dpm_ni2f_fifo_h_result_dec_80_ix47_carry_sum is dpm_ni2f_fifo_h_result_dec_80_ix47_carry_sum
--operation mode is arithmetic

dpm_ni2f_fifo_h_result_dec_80_ix47_carry_sum = dpm_ni2f_fifo_h_reg_nwords_5 $ (!A1L921);

--A1L131 is dpm_ni2f_fifo_h_result_dec_80_ix47_carry_sum~12
--operation mode is arithmetic

A1L131 = dpm_ni2f_fifo_h_reg_nwords_5 $ (!A1L921);

--A1L231 is dpm_ni2f_fifo_h_result_dec_80_ix47_carry_sum~COUT
--operation mode is arithmetic

A1L231 = CARRY(dpm_ni2f_fifo_h_reg_nwords_5 # A1L921);


--ix2362 is ix2362
--operation mode is normal

ix2362 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_h_reg_fifo_full # !dpm_ni2f_fifo_h_result_dec_80_ix47_carry_sum # !dpm_ni2f_reg_rdreq_fifo;

--A1L198 is ix2362~1
--operation mode is normal

A1L198 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_h_reg_fifo_full # !dpm_ni2f_fifo_h_result_dec_80_ix47_carry_sum # !dpm_ni2f_reg_rdreq_fifo;

--A1L298 is ix2362~2
--operation mode is normal

A1L298 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_h_reg_fifo_full # !dpm_ni2f_fifo_h_result_dec_80_ix47_carry_sum # !dpm_ni2f_reg_rdreq_fifo;


--dpm_ni2f_fifo_h_result_inc_82_ix47_carry_sum is dpm_ni2f_fifo_h_result_inc_82_ix47_carry_sum
--operation mode is arithmetic

dpm_ni2f_fifo_h_result_inc_82_ix47_carry_sum = dpm_ni2f_fifo_h_reg_nwords_5 $ (A1L561);

--A1L761 is dpm_ni2f_fifo_h_result_inc_82_ix47_carry_sum~12
--operation mode is arithmetic

A1L761 = dpm_ni2f_fifo_h_reg_nwords_5 $ (A1L561);

--A1L861 is dpm_ni2f_fifo_h_result_inc_82_ix47_carry_sum~COUT
--operation mode is arithmetic

A1L861 = CARRY(dpm_ni2f_fifo_h_reg_nwords_5 & (A1L561));


--A1L307 is ix2294~0
--operation mode is normal

A1L307 = (!ix2319_lc # !dpm_ni2f_fifo_h_result_inc_82_ix47_carry_sum) & CASCADE(A1L298);

--A1L407 is ix2294~1
--operation mode is normal

A1L407 = (!ix2319_lc # !dpm_ni2f_fifo_h_result_inc_82_ix47_carry_sum) & CASCADE(A1L298);


--dpm_ni2f_fifo_h_result_dec_80_ix43_carry_sum is dpm_ni2f_fifo_h_result_dec_80_ix43_carry_sum
--operation mode is arithmetic

dpm_ni2f_fifo_h_result_dec_80_ix43_carry_sum = dpm_ni2f_fifo_h_reg_nwords_4 $ (!A1L621);

--A1L821 is dpm_ni2f_fifo_h_result_dec_80_ix43_carry_sum~12
--operation mode is arithmetic

A1L821 = dpm_ni2f_fifo_h_reg_nwords_4 $ (!A1L621);

--A1L921 is dpm_ni2f_fifo_h_result_dec_80_ix43_carry_sum~COUT
--operation mode is arithmetic

A1L921 = CARRY(dpm_ni2f_fifo_h_reg_nwords_4 # A1L621);


--ix2361 is ix2361
--operation mode is normal

ix2361 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_h_reg_fifo_full # !dpm_ni2f_fifo_h_result_dec_80_ix43_carry_sum # !dpm_ni2f_reg_rdreq_fifo;

--A1L888 is ix2361~1
--operation mode is normal

A1L888 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_h_reg_fifo_full # !dpm_ni2f_fifo_h_result_dec_80_ix43_carry_sum # !dpm_ni2f_reg_rdreq_fifo;

--A1L988 is ix2361~2
--operation mode is normal

A1L988 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_h_reg_fifo_full # !dpm_ni2f_fifo_h_result_dec_80_ix43_carry_sum # !dpm_ni2f_reg_rdreq_fifo;


--dpm_ni2f_fifo_h_result_inc_82_ix43_carry_sum is dpm_ni2f_fifo_h_result_inc_82_ix43_carry_sum
--operation mode is arithmetic

dpm_ni2f_fifo_h_result_inc_82_ix43_carry_sum = dpm_ni2f_fifo_h_reg_nwords_4 $ (A1L261);

--A1L461 is dpm_ni2f_fifo_h_result_inc_82_ix43_carry_sum~12
--operation mode is arithmetic

A1L461 = dpm_ni2f_fifo_h_reg_nwords_4 $ (A1L261);

--A1L561 is dpm_ni2f_fifo_h_result_inc_82_ix43_carry_sum~COUT
--operation mode is arithmetic

A1L561 = CARRY(dpm_ni2f_fifo_h_reg_nwords_4 & (A1L261));


--A1L507 is ix2295~0
--operation mode is normal

A1L507 = (!ix2319_lc # !dpm_ni2f_fifo_h_result_inc_82_ix43_carry_sum) & CASCADE(A1L988);

--A1L607 is ix2295~1
--operation mode is normal

A1L607 = (!ix2319_lc # !dpm_ni2f_fifo_h_result_inc_82_ix43_carry_sum) & CASCADE(A1L988);


--dpm_ni2f_fifo_h_result_dec_80_ix39_carry_sum is dpm_ni2f_fifo_h_result_dec_80_ix39_carry_sum
--operation mode is arithmetic

dpm_ni2f_fifo_h_result_dec_80_ix39_carry_sum = dpm_ni2f_fifo_h_reg_nwords_3 $ (!A1L321);

--A1L521 is dpm_ni2f_fifo_h_result_dec_80_ix39_carry_sum~12
--operation mode is arithmetic

A1L521 = dpm_ni2f_fifo_h_reg_nwords_3 $ (!A1L321);

--A1L621 is dpm_ni2f_fifo_h_result_dec_80_ix39_carry_sum~COUT
--operation mode is arithmetic

A1L621 = CARRY(dpm_ni2f_fifo_h_reg_nwords_3 # A1L321);


--ix2360 is ix2360
--operation mode is normal

ix2360 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_h_reg_fifo_full # !dpm_ni2f_fifo_h_result_dec_80_ix39_carry_sum # !dpm_ni2f_reg_rdreq_fifo;

--A1L588 is ix2360~1
--operation mode is normal

A1L588 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_h_reg_fifo_full # !dpm_ni2f_fifo_h_result_dec_80_ix39_carry_sum # !dpm_ni2f_reg_rdreq_fifo;

--A1L688 is ix2360~2
--operation mode is normal

A1L688 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_h_reg_fifo_full # !dpm_ni2f_fifo_h_result_dec_80_ix39_carry_sum # !dpm_ni2f_reg_rdreq_fifo;


--dpm_ni2f_fifo_h_result_inc_82_ix39_carry_sum is dpm_ni2f_fifo_h_result_inc_82_ix39_carry_sum
--operation mode is arithmetic

dpm_ni2f_fifo_h_result_inc_82_ix39_carry_sum = dpm_ni2f_fifo_h_reg_nwords_3 $ (A1L951);

--A1L161 is dpm_ni2f_fifo_h_result_inc_82_ix39_carry_sum~12
--operation mode is arithmetic

A1L161 = dpm_ni2f_fifo_h_reg_nwords_3 $ (A1L951);

--A1L261 is dpm_ni2f_fifo_h_result_inc_82_ix39_carry_sum~COUT
--operation mode is arithmetic

A1L261 = CARRY(dpm_ni2f_fifo_h_reg_nwords_3 & (A1L951));


--A1L707 is ix2296~0
--operation mode is normal

A1L707 = (!ix2319_lc # !dpm_ni2f_fifo_h_result_inc_82_ix39_carry_sum) & CASCADE(A1L688);

--A1L807 is ix2296~1
--operation mode is normal

A1L807 = (!ix2319_lc # !dpm_ni2f_fifo_h_result_inc_82_ix39_carry_sum) & CASCADE(A1L688);


--ix2319_lc is ix2319_lc
--operation mode is normal

ix2319_lc = dpm_ni2f_reg_des_valid_data & (!dpm_ni2f_fifo_h_reg_fifo_full # !dpm_ni2f_reg_rdreq_fifo);

--A1L777 is ix2319_lc~0
--operation mode is normal

A1L777 = dpm_ni2f_reg_des_valid_data & (!dpm_ni2f_fifo_h_reg_fifo_full # !dpm_ni2f_reg_rdreq_fifo);


--M1_TS_DISC_d_lc3 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|TS_DISC_d_lc3
--operation mode is normal

M1_TS_DISC_d_lc3 = AMPP_FUNCTION(M1_cfg_cyc, M1_targ_burst_lc);

--M1L915 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|TS_DISC_d_lc3~1
--operation mode is normal

M1L915 = AMPP_FUNCTION(M1_cfg_cyc, M1_targ_burst_lc);


--M1L13 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|$00164~0
--operation mode is normal

M1L13 = AMPP_FUNCTION(M1_TS_ADR_CLMD, M1_cfg_cyc, M1_retry, J1_mstr_actv_lc);

--M1L23 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|$00164~10
--operation mode is normal

M1L23 = AMPP_FUNCTION(M1_TS_ADR_CLMD, M1_cfg_cyc, M1_retry, J1_mstr_actv_lc);

--M1L33 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|$00164~11
--operation mode is normal

M1L33 = AMPP_FUNCTION(M1_TS_ADR_CLMD, M1_cfg_cyc, M1_retry, J1_mstr_actv_lc);


--M1L88 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|_~1480
--operation mode is normal

M1L88 = AMPP_FUNCTION(M1_cfg_cyc, dpm_dec_reg_LT_RDY_n_pci, M1L33);

--M1L901 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|_~1518
--operation mode is normal

M1L901 = AMPP_FUNCTION(M1_cfg_cyc, dpm_dec_reg_LT_RDY_n_pci, M1L33);


--M1_cfg_adr_dec_ena_lc1 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|cfg_adr_dec_ena_lc1
--operation mode is normal

M1_cfg_adr_dec_ena_lc1 = AMPP_FUNCTION(M1_idsel_IR, M1_TS_IDLE_NOT, G1_ad_ir_address[1], G1_ad_ir_address[0]);

--M1L351 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|cfg_adr_dec_ena_lc1~27
--operation mode is normal

M1L351 = AMPP_FUNCTION(M1_idsel_IR, M1_TS_IDLE_NOT, G1_ad_ir_address[1], G1_ad_ir_address[0]);


--J1_MR_LLWAIT_r1_lc2 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LLWAIT_r1_lc2
--operation mode is normal

J1_MR_LLWAIT_r1_lc2 = AMPP_FUNCTION(J1_MR_LLWAIT_r1, J1_MR_LLWAIT_r2);

--J1L903 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LLWAIT_r1_lc2~8
--operation mode is normal

J1L903 = AMPP_FUNCTION(J1_MR_LLWAIT_r1, J1_MR_LLWAIT_r2);


--E1_counter_cell[8] is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[8]
--operation mode is up_dn_cntr

E1_counter_cell[8]_lut_out = E1_counter_cell[8] $ E1L52;
E1_counter_cell[8] = DFFEA(E1_counter_cell[8]_lut_out, GLOBAL(pci_clk), , , , , );

--E1L72Q is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[8]~6
--operation mode is up_dn_cntr

E1L72Q = E1_counter_cell[8];

--E1L82 is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[8]~COUT
--operation mode is up_dn_cntr

E1L82 = CARRY(E1_counter_cell[8] & (E1L52));


--M1_LR_PXFR_r1_carry[2] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_PXFR_r1_carry[2]
--operation mode is arithmetic

M1_LR_PXFR_r1_carry[2] = AMPP_FUNCTION();

--M1L862 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_PXFR_r1_carry[2]~49
--operation mode is arithmetic

M1L862 = AMPP_FUNCTION();

--M1L962 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_PXFR_r1_carry[2]~COUT
--operation mode is arithmetic

M1L962 = AMPP_FUNCTION(A1L5321, A1L0321, M1L662);


--M1L35 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|$00198~0
--operation mode is normal

M1L35 = AMPP_FUNCTION(A1L0321, A1L5321);

--M1L45 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|$00198~1
--operation mode is normal

M1L45 = AMPP_FUNCTION(A1L0321, A1L5321);


--M1_LR_PXFR_32_r1 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_PXFR_32_r1
--operation mode is normal

M1_LR_PXFR_32_r1 = AMPP_FUNCTION(M1L84, pci_rstn, GLOBAL(pci_clk), M1L442);

--M1L542Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_PXFR_32_r1~7
--operation mode is normal

M1L542Q = AMPP_FUNCTION(M1L84, pci_rstn, GLOBAL(pci_clk), M1L442);


--M1_LR_PXFR_32_r2 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_PXFR_32_r2
--operation mode is normal

M1_LR_PXFR_32_r2 = AMPP_FUNCTION(M1_LR_WAIT_32, M1_LR_PXFR_32_lc[2], pci_rstn, GLOBAL(pci_clk), M1L25);

--M1L742Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_PXFR_32_r2~7
--operation mode is normal

M1L742Q = AMPP_FUNCTION(M1_LR_WAIT_32, M1_LR_PXFR_32_lc[2], pci_rstn, GLOBAL(pci_clk), M1L25);


--M1_LR_PXFR_32 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_PXFR_32
--operation mode is normal

M1_LR_PXFR_32 = AMPP_FUNCTION(M1_LR_PXFR_32_r1, M1_LR_PXFR_32_r2);

--M1L942 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_PXFR_32~29
--operation mode is normal

M1L942 = AMPP_FUNCTION(M1_LR_PXFR_32_r1, M1_LR_PXFR_32_r2);


--M1_lt_ack_R_r3_lc2 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_ack_R_r3_lc2
--operation mode is normal

M1_lt_ack_R_r3_lc2 = AMPP_FUNCTION(M1_LR_PXFR, M1_TS_ADR_VLD, M1_TS_ADR_CLMD, M1_lt_rdynR);

--M1L423 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_ack_R_r3_lc2~41
--operation mode is normal

M1L423 = AMPP_FUNCTION(M1_LR_PXFR, M1_TS_ADR_VLD, M1_TS_ADR_CLMD, M1_lt_rdynR);


--M1_lt_ack_R_r1_lc[5] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_ack_R_r1_lc[5]
--operation mode is normal

M1_lt_ack_R_r1_lc[5] = AMPP_FUNCTION(M1_TS_ADR_VLD, N3_REG, M1_cfg_cyc, M1_LR_IDLE_NOT);

--M1L303 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_ack_R_r1_lc[5]~118
--operation mode is normal

M1L303 = AMPP_FUNCTION(M1_TS_ADR_VLD, N3_REG, M1_cfg_cyc, M1_LR_IDLE_NOT);


--M1_LR_LXFR_lc[5] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_LXFR_lc[5]
--operation mode is normal

M1_LR_LXFR_lc[5] = AMPP_FUNCTION(M1L422, N3_REG);

--M1L522 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_LXFR_lc[5]~63
--operation mode is normal

M1L522 = AMPP_FUNCTION(M1L422, N3_REG);


--M1_LW_LXFR_carry[1] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LW_LXFR_carry[1]
--operation mode is arithmetic

M1_LW_LXFR_carry[1] = AMPP_FUNCTION();

--M1L793 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LW_LXFR_carry[1]~33
--operation mode is arithmetic

M1L793 = AMPP_FUNCTION();

--M1L893 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LW_LXFR_carry[1]~COUT
--operation mode is arithmetic

M1L893 = AMPP_FUNCTION(M1_TS_TURN_AR, M1_LW_LXFR);


--M1L86 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|_~328
--operation mode is normal

M1L86 = AMPP_FUNCTION(M1_TS_ADR_CLMD, J1_mstr_actv_lc, M1_retry, M1_cfg_cyc);

--M1L011 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|_~1519
--operation mode is normal

M1L011 = AMPP_FUNCTION(M1_TS_ADR_CLMD, J1_mstr_actv_lc, M1_retry, M1_cfg_cyc);

--M1L111 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|_~1520
--operation mode is normal

M1L111 = AMPP_FUNCTION(M1_TS_ADR_CLMD, J1_mstr_actv_lc, M1_retry, M1_cfg_cyc);


--M1L43 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|$00167~10
--operation mode is normal

M1L43 = AMPP_FUNCTION(M1_cfg_cyc, M1_targ_burst_lc, M1_trdy_OR_NOT, M1_TS_DXFR, M1L111);

--M1L53 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|$00167~11
--operation mode is normal

M1L53 = AMPP_FUNCTION(M1_cfg_cyc, M1_targ_burst_lc, M1_trdy_OR_NOT, M1_TS_DXFR, M1L111);


--J1_DXFR_write_lc1 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|DXFR_write_lc1
--operation mode is normal

J1_DXFR_write_lc1 = AMPP_FUNCTION(J1_MS_DXFR, J1_irdy_or_not, J1_mstr_abrt, J1_frame_or_not);

--J1L961 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|DXFR_write_lc1~70
--operation mode is normal

J1L961 = AMPP_FUNCTION(J1_MS_DXFR, J1_irdy_or_not, J1_mstr_abrt, J1_frame_or_not);


--M1_wait_wait32_lc[4] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|wait_wait32_lc[4]
--operation mode is normal

M1_wait_wait32_lc[4] = AMPP_FUNCTION(M1_wait_wait32_lc[2], M1_wait_wait32_lc[3], M1_cfg_cyc);

--M1L855 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|wait_wait32_lc[4]~37
--operation mode is normal

M1L855 = AMPP_FUNCTION(M1_wait_wait32_lc[2], M1_wait_wait32_lc[3], M1_cfg_cyc);


--J1_WAIT_WAIT32_lc3 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|WAIT_WAIT32_lc3
--operation mode is normal

J1_WAIT_WAIT32_lc3 = AMPP_FUNCTION(J1_MW_WAIT_32_d_lc_1c, J1_WAIT_WAIT32_lc1, J1_WAIT_WAIT32_lc2);

--J1L306 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|WAIT_WAIT32_lc3~15
--operation mode is normal

J1L306 = AMPP_FUNCTION(J1_MW_WAIT_32_d_lc_1c, J1_WAIT_WAIT32_lc1, J1_WAIT_WAIT32_lc2);


--J1_no_op_reg[2] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|no_op_reg[2]
--operation mode is normal

J1_no_op_reg[2] = AMPP_FUNCTION(pci_rstn, GLOBAL(pci_clk));

--J1L865Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|no_op_reg[2]~21
--operation mode is normal

J1L865Q = AMPP_FUNCTION(pci_rstn, GLOBAL(pci_clk));


--J1L54 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|$00196~0
--operation mode is normal

J1L54 = AMPP_FUNCTION(A1L7421, J1_no_op_reg[2]);

--J1L64 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|$00196~10
--operation mode is normal

J1L64 = AMPP_FUNCTION(A1L7421, J1_no_op_reg[2]);

--J1L74 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|$00196~11
--operation mode is normal

J1L74 = AMPP_FUNCTION(A1L7421, J1_no_op_reg[2]);


--J1_MW_LAST_lc[3] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_LAST_lc[3]
--operation mode is normal

J1_MW_LAST_lc[3] = AMPP_FUNCTION(J1_MW_LXFR, J1_devsel_toR, J1_lm_rdynR);

--J1L794 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_LAST_lc[3]~17
--operation mode is normal

J1L794 = AMPP_FUNCTION(J1_MW_LXFR, J1_devsel_toR, J1_lm_rdynR);


--J1L24 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|$00194~0
--operation mode is normal

J1L24 = AMPP_FUNCTION(J1_no_op_reg[2], A1L7421);

--J1L34 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|$00194~10
--operation mode is normal

J1L34 = AMPP_FUNCTION(J1_no_op_reg[2], A1L7421);

--J1L44 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|$00194~11
--operation mode is normal

J1L44 = AMPP_FUNCTION(J1_no_op_reg[2], A1L7421);


--G1_low_data_out_hr_ena_d is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_hr_ena_d
--operation mode is normal

G1_low_data_out_hr_ena_d = AMPP_FUNCTION(J1_MS_ENA, J1_dati_hr_ena_lc, M1_TS_IDLE_NOT, M1_dati_hr_ena_lc);

--G1L994 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_data_out_hr_ena_d~15
--operation mode is normal

G1L994 = AMPP_FUNCTION(J1_MS_ENA, J1_dati_hr_ena_lc, M1_TS_IDLE_NOT, M1_dati_hr_ena_lc);


--P1L551 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|latency_cache_ena[0]~51
--operation mode is normal

P1L551 = AMPP_FUNCTION(M1_cfg_dat_vld, R1_decR[3], G1_low_cben_IR_data[0]);

--P1L651 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|latency_cache_ena[0]~53
--operation mode is normal

P1L651 = AMPP_FUNCTION(M1_cfg_dat_vld, R1_decR[3], G1_low_cben_IR_data[0]);


--E01_q[0] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:devsel_cntr|alt_counter_f10ke:wysi_counter|q[0]
--operation mode is clrb_cntr

E01_q[0] = AMPP_FUNCTION(J1_$00067, J1L273, ~GND, A1L8221, pci_rstn, GLOBAL(pci_clk));

--E01L9Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:devsel_cntr|alt_counter_f10ke:wysi_counter|q[0]~0
--operation mode is clrb_cntr

E01L9Q = AMPP_FUNCTION(J1_$00067, J1L273, ~GND, A1L8221, pci_rstn, GLOBAL(pci_clk));

--E01L3 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:devsel_cntr|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT
--operation mode is clrb_cntr

E01L3 = AMPP_FUNCTION();


--E01_q[2] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:devsel_cntr|alt_counter_f10ke:wysi_counter|q[2]
--operation mode is clrb_cntr

E01_q[2] = AMPP_FUNCTION(J1_$00067, J1L273, ~GND, A1L8221, pci_rstn, GLOBAL(pci_clk), E01L5);

--E01L31Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:devsel_cntr|alt_counter_f10ke:wysi_counter|q[2]~1
--operation mode is clrb_cntr

E01L31Q = AMPP_FUNCTION(J1_$00067, J1L273, ~GND, A1L8221, pci_rstn, GLOBAL(pci_clk), E01L5);


--E01_q[1] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:devsel_cntr|alt_counter_f10ke:wysi_counter|q[1]
--operation mode is clrb_cntr

E01_q[1] = AMPP_FUNCTION(J1_$00067, J1L273, ~GND, A1L8221, pci_rstn, GLOBAL(pci_clk), E01L3);

--E01L11Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:devsel_cntr|alt_counter_f10ke:wysi_counter|q[1]~2
--operation mode is clrb_cntr

E01L11Q = AMPP_FUNCTION(J1_$00067, J1L273, ~GND, A1L8221, pci_rstn, GLOBAL(pci_clk), E01L3);

--E01L5 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:devsel_cntr|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT
--operation mode is clrb_cntr

E01L5 = AMPP_FUNCTION(E01L3);


--J1_devsel_toR_lc1 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|devsel_toR_lc1
--operation mode is normal

J1_devsel_toR_lc1 = AMPP_FUNCTION(E01_q[0], E01_q[2], J1_dac_cyc_reg, E01_q[1]);

--J1L951 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|devsel_toR_lc1~40
--operation mode is normal

J1L951 = AMPP_FUNCTION(E01_q[0], E01_q[2], J1_dac_cyc_reg, E01_q[1]);


--P1L751 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|latency_cache_ena[1]~52
--operation mode is normal

P1L751 = AMPP_FUNCTION(M1_cfg_dat_vld, R1_decR[3], G1_low_cben_IR_data[1]);

--P1L851 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|latency_cache_ena[1]~54
--operation mode is normal

P1L851 = AMPP_FUNCTION(M1_cfg_dat_vld, R1_decR[3], G1_low_cben_IR_data[1]);


--P1L57 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|bar0_ena[2]~51
--operation mode is normal

P1L57 = AMPP_FUNCTION(M1_cfg_dat_vld, R1_decR[4], G1_low_cben_IR_data[2]);

--P1L67 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|bar0_ena[2]~53
--operation mode is normal

P1L67 = AMPP_FUNCTION(M1_cfg_dat_vld, R1_decR[4], G1_low_cben_IR_data[2]);


--P1L77 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|bar0_ena[3]~52
--operation mode is normal

P1L77 = AMPP_FUNCTION(M1_cfg_dat_vld, R1_decR[4], G1_low_cben_IR_data[3]);

--P1L87 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|bar0_ena[3]~54
--operation mode is normal

P1L87 = AMPP_FUNCTION(M1_cfg_dat_vld, R1_decR[4], G1_low_cben_IR_data[3]);


--J1_perr_rep_setR is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|perr_rep_setR
--operation mode is normal

J1_perr_rep_setR = AMPP_FUNCTION(J1_MS_DXFR, J1_MS_TAR, J1_MS_TAR_R, A1L0421, pci_rstn, GLOBAL(pci_clk));

--J1L885Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|perr_rep_setR~31
--operation mode is normal

J1L885Q = AMPP_FUNCTION(J1_MS_DXFR, J1_MS_TAR, J1_MS_TAR_R, A1L0421, pci_rstn, GLOBAL(pci_clk));


--J1_tabrt_set is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|tabrt_set
--operation mode is normal

J1_tabrt_set = AMPP_FUNCTION(A1L8221, A1L7421, J1_MS_DXFR, A1L5421, pci_rstn, GLOBAL(pci_clk));

--J1L595Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|tabrt_set~33
--operation mode is normal

J1L595Q = AMPP_FUNCTION(A1L8221, A1L7421, J1_MS_DXFR, A1L5421, pci_rstn, GLOBAL(pci_clk));


--K1_perr_det_setR_r1 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|perr_det_setR_r1
--operation mode is normal

K1_perr_det_setR_r1 = AMPP_FUNCTION(J1_perr_vldR, M1_perr_vldR, A1L8321, K1_xxl[11], pci_rstn, GLOBAL(pci_clk));

--K1L2Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|perr_det_setR_r1~7
--operation mode is normal

K1L2Q = AMPP_FUNCTION(J1_perr_vldR, M1_perr_vldR, A1L8321, K1_xxl[11], pci_rstn, GLOBAL(pci_clk));


--K1_perr_det_setR_r3 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|perr_det_setR_r3
--operation mode is normal

K1_perr_det_setR_r3 = AMPP_FUNCTION(G1_trg_serr_vld, A1L8321, K1_xxlad[11], pci_rstn, GLOBAL(pci_clk));

--K1L4Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pk:parity_Chk|perr_det_setR_r3~7
--operation mode is normal

K1L4Q = AMPP_FUNCTION(G1_trg_serr_vld, A1L8321, K1_xxlad[11], pci_rstn, GLOBAL(pci_clk));


--U11_aeb_out is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|lpm_compare:bar0_comp|comptree:comparator|cmpchain:cmp_end|comptree:comp|cmpchain:cmp[0]|aeb_out
--operation mode is normal

U11_aeb_out = AMPP_FUNCTION(G1_ad_ir_address[28], P1_bar0_reg[28], G1_ad_ir_address[29], P1_bar0_reg[29]);

--U11L3 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|lpm_compare:bar0_comp|comptree:comparator|cmpchain:cmp_end|comptree:comp|cmpchain:cmp[0]|aeb_out~1
--operation mode is normal

U11L3 = AMPP_FUNCTION(G1_ad_ir_address[28], P1_bar0_reg[28], G1_ad_ir_address[29], P1_bar0_reg[29]);


--U21_aeb_out is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|lpm_compare:bar0_comp|comptree:comparator|cmpchain:cmp_end|comptree:comp|cmpchain:cmp[1]|aeb_out
--operation mode is normal

U21_aeb_out = AMPP_FUNCTION(G1_ad_ir_address[30], P1_bar0_reg[30], G1_ad_ir_address[31], P1_bar0_reg[31]);

--U21L3 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|lpm_compare:bar0_comp|comptree:comparator|cmpchain:cmp_end|comptree:comp|cmpchain:cmp[1]|aeb_out~1
--operation mode is normal

U21L3 = AMPP_FUNCTION(G1_ad_ir_address[30], P1_bar0_reg[30], G1_ad_ir_address[31], P1_bar0_reg[31]);


--U8_aeb_out is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|lpm_compare:bar0_comp|comptree:comparator|cmpchain:cmp[0]|comptree:comp|cmpchain:cmp[3]|aeb_out
--operation mode is normal

U8_aeb_out = AMPP_FUNCTION(G1_ad_ir_address[26], P1_bar0_reg[26], G1_ad_ir_address[27], P1_bar0_reg[27]);

--U8L3 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|lpm_compare:bar0_comp|comptree:comparator|cmpchain:cmp[0]|comptree:comp|cmpchain:cmp[3]|aeb_out~1
--operation mode is normal

U8L3 = AMPP_FUNCTION(G1_ad_ir_address[26], P1_bar0_reg[26], G1_ad_ir_address[27], P1_bar0_reg[27]);


--U7_aeb_out is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|lpm_compare:bar0_comp|comptree:comparator|cmpchain:cmp[0]|comptree:comp|cmpchain:cmp[2]|aeb_out
--operation mode is normal

U7_aeb_out = AMPP_FUNCTION(G1_ad_ir_address[24], P1_bar0_reg[24], G1_ad_ir_address[25], P1_bar0_reg[25]);

--U7L3 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|lpm_compare:bar0_comp|comptree:comparator|cmpchain:cmp[0]|comptree:comp|cmpchain:cmp[2]|aeb_out~1
--operation mode is normal

U7L3 = AMPP_FUNCTION(G1_ad_ir_address[24], P1_bar0_reg[24], G1_ad_ir_address[25], P1_bar0_reg[25]);


--U5_aeb_out is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|lpm_compare:bar0_comp|comptree:comparator|cmpchain:cmp[0]|comptree:comp|cmpchain:cmp[0]|aeb_out
--operation mode is normal

U5_aeb_out = AMPP_FUNCTION(G1_ad_ir_address[20], P1_bar0_reg[20], G1_ad_ir_address[21], P1_bar0_reg[21]);

--U5L3 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|lpm_compare:bar0_comp|comptree:comparator|cmpchain:cmp[0]|comptree:comp|cmpchain:cmp[0]|aeb_out~1
--operation mode is normal

U5L3 = AMPP_FUNCTION(G1_ad_ir_address[20], P1_bar0_reg[20], G1_ad_ir_address[21], P1_bar0_reg[21]);


--U6_aeb_out is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|lpm_compare:bar0_comp|comptree:comparator|cmpchain:cmp[0]|comptree:comp|cmpchain:cmp[1]|aeb_out
--operation mode is normal

U6_aeb_out = AMPP_FUNCTION(G1_ad_ir_address[22], P1_bar0_reg[22], G1_ad_ir_address[23], P1_bar0_reg[23]);

--U6L3 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|lpm_compare:bar0_comp|comptree:comparator|cmpchain:cmp[0]|comptree:comp|cmpchain:cmp[1]|aeb_out~1
--operation mode is normal

U6L3 = AMPP_FUNCTION(G1_ad_ir_address[22], P1_bar0_reg[22], G1_ad_ir_address[23], P1_bar0_reg[23]);


--J1_latcntr_toR is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|latcntr_toR
--operation mode is normal

J1_latcntr_toR = AMPP_FUNCTION(J1_latcntr_toR_lc1, J1_latcntr_toR_lc2, J1_latcntr_toR, pci_rstn, GLOBAL(pci_clk), J1L762);

--J1L272Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|latcntr_toR~25
--operation mode is normal

J1L272Q = AMPP_FUNCTION(J1_latcntr_toR_lc1, J1_latcntr_toR_lc2, J1_latcntr_toR, pci_rstn, GLOBAL(pci_clk), J1L762);


--J1_MW_WAIT_32_r[2] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_WAIT_32_r[2]
--operation mode is normal

J1_MW_WAIT_32_r[2] = AMPP_FUNCTION(A1L5421, J1_MW_WAIT_32_lc[2], J1_last_xfr, J1_MW_WAIT_32_lc[3], pci_rstn, GLOBAL(pci_clk), J1L26);

--J1L555Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_WAIT_32_r[2]~14
--operation mode is normal

J1L555Q = AMPP_FUNCTION(A1L5421, J1_MW_WAIT_32_lc[2], J1_last_xfr, J1_MW_WAIT_32_lc[3], pci_rstn, GLOBAL(pci_clk), J1L26);


--J1_MW_WAIT_32_r[1] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_WAIT_32_r[1]
--operation mode is normal

J1_MW_WAIT_32_r[1] = AMPP_FUNCTION(A1L5421, J1_MW_WAIT_32_lc[1], pci_rstn, GLOBAL(pci_clk), J1L223);

--J1L355Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_WAIT_32_r[1]~15
--operation mode is normal

J1L355Q = AMPP_FUNCTION(A1L5421, J1_MW_WAIT_32_lc[1], pci_rstn, GLOBAL(pci_clk), J1L223);


--J1_MW_WAIT_32_lc[2] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_WAIT_32_lc[2]
--operation mode is normal

J1_MW_WAIT_32_lc[2] = AMPP_FUNCTION(J1_MW_WAIT_32_r[2], J1_MW_WAIT_32_r[1]);

--J1L745 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_WAIT_32_lc[2]~32
--operation mode is normal

J1L745 = AMPP_FUNCTION(J1_MW_WAIT_32_r[2], J1_MW_WAIT_32_r[1]);


--J1_frame_or_lc3a is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|frame_or_lc3a
--operation mode is normal

J1_frame_or_lc3a = AMPP_FUNCTION(J1_latcntr_toR, J1_last_xfr_lc1, J1_MW_DXFR_32, J1_MW_WAIT_32_lc[2]);

--J1L502 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|frame_or_lc3a~25
--operation mode is normal

J1L502 = AMPP_FUNCTION(J1_latcntr_toR, J1_last_xfr_lc1, J1_MW_DXFR_32, J1_MW_WAIT_32_lc[2]);


--J1_MW_WAIT is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_WAIT
--operation mode is normal

J1_MW_WAIT = AMPP_FUNCTION(A1L5421, J1L755, J1_MW_WAIT_lc[2], pci_rstn, GLOBAL(pci_clk), J1L14);

--J1L365Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_WAIT~14
--operation mode is normal

J1L365Q = AMPP_FUNCTION(A1L5421, J1L755, J1_MW_WAIT_lc[2], pci_rstn, GLOBAL(pci_clk), J1L14);


--J1_frame_or_lc3b is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|frame_or_lc3b
--operation mode is normal

J1_frame_or_lc3b = AMPP_FUNCTION(J1_MW_WAIT, J1_MW_DXFR, J1_lm_rdynR);

--J1L702 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|frame_or_lc3b~4
--operation mode is normal

J1L702 = AMPP_FUNCTION(J1_MW_WAIT, J1_MW_DXFR, J1_lm_rdynR);


--J1_mw_lxfr_r1_carry is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|mw_lxfr_r1_carry
--operation mode is arithmetic

J1_mw_lxfr_r1_carry = AMPP_FUNCTION();

--J1L025 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|mw_lxfr_r1_carry~11
--operation mode is arithmetic

J1L025 = AMPP_FUNCTION();

--J1L125 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|mw_lxfr_r1_carry~COUT
--operation mode is arithmetic

J1L125 = AMPP_FUNCTION(A1L7421, J1_no_op_reg[1]);


--J1_MR_LPXFR_r1_carry is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LPXFR_r1_carry
--operation mode is arithmetic

J1_MR_LPXFR_r1_carry = AMPP_FUNCTION();

--J1L043 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LPXFR_r1_carry~18
--operation mode is arithmetic

J1L043 = AMPP_FUNCTION();

--J1L143 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LPXFR_r1_carry~COUT
--operation mode is arithmetic

J1L143 = AMPP_FUNCTION(A1L7421, J1_no_op_reg[5]);


--J1_MW_HOLD_lc[2] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_HOLD_lc[2]
--operation mode is normal

J1_MW_HOLD_lc[2] = AMPP_FUNCTION(J1_MW_HOLD, J1_devsel_toR);

--J1L284 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_HOLD_lc[2]~18
--operation mode is normal

J1L284 = AMPP_FUNCTION(J1_MW_HOLD, J1_devsel_toR);


--J1_adr_phase_end is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|adr_phase_end
--operation mode is normal

J1_adr_phase_end = AMPP_FUNCTION(J1_adr_phase_end_lc1, J1_MS_ENA, pci_gntn, J1_dac_cmd, pci_rstn, GLOBAL(pci_clk));

--J1L721Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|adr_phase_end~1
--operation mode is normal

J1L721Q = AMPP_FUNCTION(J1_adr_phase_end_lc1, J1_MS_ENA, pci_gntn, J1_dac_cmd, pci_rstn, GLOBAL(pci_clk));


--J1_irdy_or_lc[3] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|irdy_or_lc[3]
--operation mode is normal

J1_irdy_or_lc[3] = AMPP_FUNCTION(J1_MW_DXFR_32, J1_adr_phase_end, J1_wr_rdn, J1_MR_IDLE_not);

--J1L732 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|irdy_or_lc[3]~54
--operation mode is normal

J1L732 = AMPP_FUNCTION(J1_MW_DXFR_32, J1_adr_phase_end, J1_wr_rdn, J1_MR_IDLE_not);


--J1_irdy_or_lc[1] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|irdy_or_lc[1]
--operation mode is normal

J1_irdy_or_lc[1] = AMPP_FUNCTION(J1_MW_WAIT_32_lc[2], J1_MW_WAIT, J1_MW_DXFR, J1_lm_rdynR);

--J1L132 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|irdy_or_lc[1]~55
--operation mode is normal

J1L132 = AMPP_FUNCTION(J1_MW_WAIT_32_lc[2], J1_MW_WAIT, J1_MW_DXFR, J1_lm_rdynR);


--J1_no_op_reg[7] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|no_op_reg[7]
--operation mode is normal

J1_no_op_reg[7] = AMPP_FUNCTION(pci_rstn, GLOBAL(pci_clk));

--J1L875Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|no_op_reg[7]~22
--operation mode is normal

J1L875Q = AMPP_FUNCTION(pci_rstn, GLOBAL(pci_clk));


--J1_MR_END_d_lc2 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_END_d_lc2
--operation mode is normal

J1_MR_END_d_lc2 = AMPP_FUNCTION(J1_MR_PXFR, J1_MR_LPXFR);

--J1L192 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_END_d_lc2~1
--operation mode is normal

J1L192 = AMPP_FUNCTION(J1_MR_PXFR, J1_MR_LPXFR);


--J1_MR_END_d_lc1 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_END_d_lc1
--operation mode is normal

J1_MR_END_d_lc1 = AMPP_FUNCTION(J1_MR_LLXFR_r2, J1_MR_LLXFR_r1, J1_devsel_toR, J1_MR_END_d_lc2);

--J1L982 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_END_d_lc1~36
--operation mode is normal

J1L982 = AMPP_FUNCTION(J1_MR_LLXFR_r2, J1_MR_LLXFR_r1, J1_devsel_toR, J1_MR_END_d_lc2);


--L1_par[9] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pg:parity_gen|par[9]
--operation mode is normal

L1_par[9] = AMPP_FUNCTION(L1_par[7], L1_par[6], L1_par[5], L1_par[4]);

--L1L13 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pg:parity_gen|par[9]~190
--operation mode is normal

L1L13 = AMPP_FUNCTION(L1_par[7], L1_par[6], L1_par[5], L1_par[4]);


--L1_par[8] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pg:parity_gen|par[8]
--operation mode is normal

L1_par[8] = AMPP_FUNCTION(L1_par[3], L1_par[2], L1_par[1], L1_par[0]);

--L1L82 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pg:parity_gen|par[8]~191
--operation mode is normal

L1L82 = AMPP_FUNCTION(L1_par[3], L1_par[2], L1_par[1], L1_par[0]);


--M1L63 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|$00172~0
--operation mode is normal

M1L63 = AMPP_FUNCTION(M1_TS_ADR_CLMD, J1_mstr_actv_lc, M1_retry);

--M1L73 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|$00172~10
--operation mode is normal

M1L73 = AMPP_FUNCTION(M1_TS_ADR_CLMD, J1_mstr_actv_lc, M1_retry);

--M1L83 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|$00172~11
--operation mode is normal

M1L83 = AMPP_FUNCTION(M1_TS_ADR_CLMD, J1_mstr_actv_lc, M1_retry);


--M1L26 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|_~89
--operation mode is normal

M1L26 = AMPP_FUNCTION(M1_TS_ADR_CLMD, M1_cfg_cyc);

--M1L211 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|_~1521
--operation mode is normal

M1L211 = AMPP_FUNCTION(M1_TS_ADR_CLMD, M1_cfg_cyc);

--M1L311 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|_~1522
--operation mode is normal

M1L311 = AMPP_FUNCTION(M1_TS_ADR_CLMD, M1_cfg_cyc);


--M1L844 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|stop_or_cc1~0
--operation mode is normal

M1L844 = AMPP_FUNCTION(M1_no_op_reg[1], M1_LR_LXFR);

--M1L944 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|stop_or_cc1~10
--operation mode is normal

M1L944 = AMPP_FUNCTION(M1_no_op_reg[1], M1_LR_LXFR);

--M1L054 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|stop_or_cc1~11
--operation mode is normal

M1L054 = AMPP_FUNCTION(M1_no_op_reg[1], M1_LR_LXFR);


--M1_burst_trans_r is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|burst_trans_r
--operation mode is normal

M1_burst_trans_r = AMPP_FUNCTION(M1_TS_TURN_AR, J1_mstr_actv_lc, M1_TS_IDLE_NOT);

--M1L941 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|burst_trans_r~15
--operation mode is normal

M1L941 = AMPP_FUNCTION(M1_TS_TURN_AR, J1_mstr_actv_lc, M1_TS_IDLE_NOT);


--M1_trdy_OR_lc[4] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|trdy_OR_lc[4]
--operation mode is normal

M1_trdy_OR_lc[4] = AMPP_FUNCTION(N3_REG, dpm_dec_reg_LT_RDY_n_pci, M1_LW_IDLE_NOT, J1_mstr_actv_lc);

--M1L105 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|trdy_OR_lc[4]~85
--operation mode is normal

M1L105 = AMPP_FUNCTION(N3_REG, dpm_dec_reg_LT_RDY_n_pci, M1_LW_IDLE_NOT, J1_mstr_actv_lc);


--M1_trdy_OR_lc[2] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|trdy_OR_lc[2]
--operation mode is normal

M1_trdy_OR_lc[2] = AMPP_FUNCTION(M1_lt_rdynR, M1_LR_LXFR, M1_TS_DISC);

--M1L694 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|trdy_OR_lc[2]~86
--operation mode is normal

M1L694 = AMPP_FUNCTION(M1_lt_rdynR, M1_LR_LXFR, M1_TS_DISC);


--M1_trdy_or_cc3 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|trdy_or_cc3
--operation mode is normal

M1_trdy_or_cc3 = AMPP_FUNCTION(M1_LR_LXFR, M1_trdy_OR_lc[1]);

--M1L984 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|trdy_or_cc3~17
--operation mode is normal

M1L984 = AMPP_FUNCTION(M1_LR_LXFR, M1_trdy_OR_lc[1]);


--dpm_dec_reg_tmp2 is dpm_dec_reg_tmp2
--operation mode is normal

dpm_dec_reg_tmp2_lut_out = dpm_dec_reg_tmp1;
dpm_dec_reg_tmp2 = DFFEA(dpm_dec_reg_tmp2_lut_out, GLOBAL(pci_clk), pci_rstn, , , , );

--A1L66Q is dpm_dec_reg_tmp2~1
--operation mode is normal

A1L66Q = dpm_dec_reg_tmp2;


--dpm_ni2f_fifo_l_reg_nwords_2 is dpm_ni2f_fifo_l_reg_nwords_2
--operation mode is normal

dpm_ni2f_fifo_l_reg_nwords_2_lut_out = !A1L276;
dpm_ni2f_fifo_l_reg_nwords_2 = DFFEA(dpm_ni2f_fifo_l_reg_nwords_2_lut_out, lcst, !dpm_ni2f_reg_sreset120, , ix2286_lc, , );

--A1L902Q is dpm_ni2f_fifo_l_reg_nwords_2~1
--operation mode is normal

A1L902Q = dpm_ni2f_fifo_l_reg_nwords_2;


--dpm_ni2f_fifo_l_reg_nwords_1 is dpm_ni2f_fifo_l_reg_nwords_1
--operation mode is normal

dpm_ni2f_fifo_l_reg_nwords_1_lut_out = !A1L476;
dpm_ni2f_fifo_l_reg_nwords_1 = DFFEA(dpm_ni2f_fifo_l_reg_nwords_1_lut_out, lcst, !dpm_ni2f_reg_sreset120, , ix2286_lc, , );

--A1L702Q is dpm_ni2f_fifo_l_reg_nwords_1~1
--operation mode is normal

A1L702Q = dpm_ni2f_fifo_l_reg_nwords_1;


--dpm_ni2f_fifo_l_reg_nwords_0 is dpm_ni2f_fifo_l_reg_nwords_0
--operation mode is normal

dpm_ni2f_fifo_l_reg_nwords_0_lut_out = !A1L676;
dpm_ni2f_fifo_l_reg_nwords_0 = DFFEA(dpm_ni2f_fifo_l_reg_nwords_0_lut_out, lcst, !dpm_ni2f_reg_sreset120, , ix2286_lc, , );

--A1L502Q is dpm_ni2f_fifo_l_reg_nwords_0~1
--operation mode is normal

A1L502Q = dpm_ni2f_fifo_l_reg_nwords_0;


--A1L091 is dpm_ni2f_fifo_l_modgen_eq_69_ix25~0
--operation mode is normal

A1L091 = (dpm_ni2f_fifo_l_reg_nwords_2 & dpm_ni2f_fifo_l_reg_nwords_1 & !dpm_ni2f_fifo_l_reg_nwords_0) & CASCADE(A1L981);

--A1L191 is dpm_ni2f_fifo_l_modgen_eq_69_ix25~1
--operation mode is normal

A1L191 = (dpm_ni2f_fifo_l_reg_nwords_2 & dpm_ni2f_fifo_l_reg_nwords_1 & !dpm_ni2f_fifo_l_reg_nwords_0) & CASCADE(A1L981);


--A1L891 is dpm_ni2f_fifo_l_modgen_eq_73_ix25~0
--operation mode is normal

A1L891 = (!dpm_ni2f_fifo_l_reg_nwords_2 & !dpm_ni2f_fifo_l_reg_nwords_1 & dpm_ni2f_fifo_l_reg_nwords_0) & CASCADE(A1L791);

--A1L991 is dpm_ni2f_fifo_l_modgen_eq_73_ix25~1
--operation mode is normal

A1L991 = (!dpm_ni2f_fifo_l_reg_nwords_2 & !dpm_ni2f_fifo_l_reg_nwords_1 & dpm_ni2f_fifo_l_reg_nwords_0) & CASCADE(A1L791);


--dpm_ni2f_fifo_h_result_dec_80_ix67_lc is dpm_ni2f_fifo_h_result_dec_80_ix67_lc
--operation mode is normal

dpm_ni2f_fifo_h_result_dec_80_ix67_lc = dpm_ni2f_fifo_h_reg_nwords_10 $ !A1L441;

--A1L741 is dpm_ni2f_fifo_h_result_dec_80_ix67_lc~0
--operation mode is normal

A1L741 = dpm_ni2f_fifo_h_reg_nwords_10 $ !A1L441;


--dpm_ni2f_fifo_h_result_inc_82_ix67_lc is dpm_ni2f_fifo_h_result_inc_82_ix67_lc
--operation mode is normal

dpm_ni2f_fifo_h_result_inc_82_ix67_lc = dpm_ni2f_fifo_h_reg_nwords_10 $ A1L081;

--A1L381 is dpm_ni2f_fifo_h_result_inc_82_ix67_lc~0
--operation mode is normal

A1L381 = dpm_ni2f_fifo_h_reg_nwords_10 $ A1L081;


--dpm_ni2f_fifo_h_result_dec_80_ix29_carry_sum is dpm_ni2f_fifo_h_result_dec_80_ix29_carry_sum
--operation mode is arithmetic

dpm_ni2f_fifo_h_result_dec_80_ix29_carry_sum = VCC;

--A1L611 is dpm_ni2f_fifo_h_result_dec_80_ix29_carry_sum~7
--operation mode is arithmetic

A1L611 = VCC;

--A1L711 is dpm_ni2f_fifo_h_result_dec_80_ix29_carry_sum~COUT
--operation mode is arithmetic

A1L711 = CARRY(dpm_ni2f_fifo_h_reg_nwords_0);


--dpm_ni2f_fifo_h_result_inc_82_ix29_carry_sum is dpm_ni2f_fifo_h_result_inc_82_ix29_carry_sum
--operation mode is arithmetic

dpm_ni2f_fifo_h_result_inc_82_ix29_carry_sum = VCC;

--A1L251 is dpm_ni2f_fifo_h_result_inc_82_ix29_carry_sum~7
--operation mode is arithmetic

A1L251 = VCC;

--A1L351 is dpm_ni2f_fifo_h_result_inc_82_ix29_carry_sum~COUT
--operation mode is arithmetic

A1L351 = CARRY(dpm_ni2f_fifo_h_reg_nwords_0);


--J1_MW_END_r[2] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_END_r[2]
--operation mode is normal

J1_MW_END_r[2] = AMPP_FUNCTION(J1_devsel_toR, J1_MW_LXFR, J1_MW_IDLE_not, A1L5421, pci_rstn, GLOBAL(pci_clk));

--J1L174Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_END_r[2]~14
--operation mode is normal

J1L174Q = AMPP_FUNCTION(J1_devsel_toR, J1_MW_LXFR, J1_MW_IDLE_not, A1L5421, pci_rstn, GLOBAL(pci_clk));


--J1_MW_END_r[1] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_END_r[1]
--operation mode is normal

J1_MW_END_r[1] = AMPP_FUNCTION(J1_MW_HOLD, J1_devsel_toR, J1_MW_END_lc1, pci_rstn, GLOBAL(pci_clk), J1L764);

--J1L964Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_END_r[1]~15
--operation mode is normal

J1L964Q = AMPP_FUNCTION(J1_MW_HOLD, J1_devsel_toR, J1_MW_END_lc1, pci_rstn, GLOBAL(pci_clk), J1L764);


--J1_MW_END is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_END
--operation mode is normal

J1_MW_END = AMPP_FUNCTION(J1_MW_END_r[2], J1_MW_END_r[1]);

--J1L374 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_END~8
--operation mode is normal

J1L374 = AMPP_FUNCTION(J1_MW_END_r[2], J1_MW_END_r[1]);


--E1_counter_cell[7] is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[7]
--operation mode is up_dn_cntr

E1_counter_cell[7]_lut_out = E1_counter_cell[7] $ E1L22;
E1_counter_cell[7] = DFFEA(E1_counter_cell[7]_lut_out, GLOBAL(pci_clk), , , , , );

--E1L42Q is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[7]~7
--operation mode is up_dn_cntr

E1L42Q = E1_counter_cell[7];

--E1L52 is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[7]~COUT
--operation mode is up_dn_cntr

E1L52 = CARRY(E1_counter_cell[7] & (E1L22));


--M1L55 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|$00202~0
--operation mode is normal

M1L55 = AMPP_FUNCTION(M1_no_op_reg[1], A1L5321, A1L0321);

--M1L65 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|$00202~10
--operation mode is normal

M1L65 = AMPP_FUNCTION(M1_no_op_reg[1], A1L5321, A1L0321);

--M1L75 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|$00202~11
--operation mode is normal

M1L75 = AMPP_FUNCTION(M1_no_op_reg[1], A1L5321, A1L0321);


--M1_LR_PXFR_32_r1_carry[2] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_PXFR_32_r1_carry[2]
--operation mode is arithmetic

M1_LR_PXFR_32_r1_carry[2] = AMPP_FUNCTION();

--M1L342 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_PXFR_32_r1_carry[2]~49
--operation mode is arithmetic

M1L342 = AMPP_FUNCTION();

--M1L442 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_PXFR_32_r1_carry[2]~COUT
--operation mode is arithmetic

M1L442 = AMPP_FUNCTION(A1L5321, A1L0321, M1L142);


--M1_lreg_busy is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lreg_busy
--operation mode is normal

M1_lreg_busy = AMPP_FUNCTION(M1_LW_DONE, M1_TS_IDLE_NOT, M1_lreg_busy, M1_LW_IDLE_NOT, pci_rstn, GLOBAL(pci_clk));

--M1L682Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lreg_busy~36
--operation mode is normal

M1L682Q = AMPP_FUNCTION(M1_LW_DONE, M1_TS_IDLE_NOT, M1_lreg_busy, M1_LW_IDLE_NOT, pci_rstn, GLOBAL(pci_clk));


--M1_retry_set is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|retry_set
--operation mode is normal

M1_retry_set = AMPP_FUNCTION(M1_lreg_busy, M1_retry_set_lc);

--M1L644 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|retry_set~1
--operation mode is normal

M1L644 = AMPP_FUNCTION(M1_lreg_busy, M1_retry_set_lc);


--M1L834 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|retry_rst_lc2~35
--operation mode is normal

M1L834 = AMPP_FUNCTION(N3_REG, M1_TS_ADR_CLMD, M1_retry_rst_lc1, M1_cfg_cyc);

--M1L044 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|retry_rst_lc2~37
--operation mode is normal

M1L044 = AMPP_FUNCTION(N3_REG, M1_TS_ADR_CLMD, M1_retry_rst_lc1, M1_cfg_cyc);


--M1_retry_rst_lc2 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|retry_rst_lc2
--operation mode is normal

M1_retry_rst_lc2 = AMPP_FUNCTION(M1L834, M1_retry_rst_lc1, M1_TS_IDLE_NOT, M1_adr_phase_lc1);

--M1L144 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|retry_rst_lc2~38
--operation mode is normal

M1L144 = AMPP_FUNCTION(M1L834, M1_retry_rst_lc1, M1_TS_IDLE_NOT, M1_adr_phase_lc1);


--M1_LR_LXFR_carry[1] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_LXFR_carry[1]
--operation mode is arithmetic

M1_LR_LXFR_carry[1] = AMPP_FUNCTION();

--M1L602 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_LXFR_carry[1]~39
--operation mode is arithmetic

M1L602 = AMPP_FUNCTION();

--M1L702 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_LXFR_carry[1]~COUT
--operation mode is arithmetic

M1L702 = AMPP_FUNCTION(M1_LR_LXFR_lc[4]);


--M1L24 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|$00184~0
--operation mode is normal

M1L24 = AMPP_FUNCTION(M1_lt_rdynR, M1_TS_DISC, M1_LR_LXFR_lc[1]);

--M1L34 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|$00184~10
--operation mode is normal

M1L34 = AMPP_FUNCTION(M1_lt_rdynR, M1_TS_DISC, M1_LR_LXFR_lc[1]);

--M1L44 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|$00184~11
--operation mode is normal

M1L44 = AMPP_FUNCTION(M1_lt_rdynR, M1_TS_DISC, M1_LR_LXFR_lc[1]);


--M1_LW_LXFR_lc[3] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LW_LXFR_lc[3]
--operation mode is normal

M1_LW_LXFR_lc[3] = AMPP_FUNCTION(M1_TS_DXFR, M1_LW_WAIT, dpm_dec_reg_LT_RDY_n_pci);

--M1L214 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LW_LXFR_lc[3]~79
--operation mode is normal

M1L214 = AMPP_FUNCTION(M1_TS_DXFR, M1_LW_WAIT, dpm_dec_reg_LT_RDY_n_pci);


--M1L93 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|$00174~0
--operation mode is normal

M1L93 = AMPP_FUNCTION(M1_TS_ADR_CLMD, J1_mstr_actv_lc, M1_LW_IDLE_NOT, M1_retry);

--M1L04 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|$00174~10
--operation mode is normal

M1L04 = AMPP_FUNCTION(M1_TS_ADR_CLMD, J1_mstr_actv_lc, M1_LW_IDLE_NOT, M1_retry);

--M1L14 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|$00174~11
--operation mode is normal

M1L14 = AMPP_FUNCTION(M1_TS_ADR_CLMD, J1_mstr_actv_lc, M1_LW_IDLE_NOT, M1_retry);


--M1_wait_wait32_lc[2] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|wait_wait32_lc[2]
--operation mode is normal

M1_wait_wait32_lc[2] = AMPP_FUNCTION(M1_LR_WAIT, M1_wait_wait32_lc[1]);

--M1L255 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|wait_wait32_lc[2]~38
--operation mode is normal

M1L255 = AMPP_FUNCTION(M1_LR_WAIT, M1_wait_wait32_lc[1]);


--J1_MW_WAIT_32_d_lc_1c is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_WAIT_32_d_lc_1c
--operation mode is normal

J1_MW_WAIT_32_d_lc_1c = AMPP_FUNCTION(J1_MW_WAIT_32_d_lc_1b, J1_MW_WAIT_32_r[2], J1_MW_WAIT_32_r[1]);

--J1L735 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_WAIT_32_d_lc_1c~12
--operation mode is normal

J1L735 = AMPP_FUNCTION(J1_MW_WAIT_32_d_lc_1b, J1_MW_WAIT_32_r[2], J1_MW_WAIT_32_r[1]);


--J1_WAIT_WAIT32_lc1 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|WAIT_WAIT32_lc1
--operation mode is normal

J1_WAIT_WAIT32_lc1 = AMPP_FUNCTION(J1_MW_DXFR, J1_lm_rdynR, J1_devsel_toR);

--J1L895 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|WAIT_WAIT32_lc1~8
--operation mode is normal

J1L895 = AMPP_FUNCTION(J1_MW_DXFR, J1_lm_rdynR, J1_devsel_toR);


--J1_WAIT_WAIT32_lc2 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|WAIT_WAIT32_lc2
--operation mode is normal

J1_WAIT_WAIT32_lc2 = AMPP_FUNCTION(J1_MW_WAIT, J1_MW_DXFR_32, J1_devsel_toR, J1_lm_rdynR);

--J1L006 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|WAIT_WAIT32_lc2~8
--operation mode is normal

J1L006 = AMPP_FUNCTION(J1_MW_WAIT, J1_MW_DXFR_32, J1_devsel_toR, J1_lm_rdynR);


--J1_MW_WAIT_32_d_lc_1a is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_WAIT_32_d_lc_1a
--operation mode is normal

J1_MW_WAIT_32_d_lc_1a = AMPP_FUNCTION(J1_MW_DXFR_32, J1_lm_rdynR, J1_last_xfr_lc1);

--J1L135 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_WAIT_32_d_lc_1a~1
--operation mode is normal

J1L135 = AMPP_FUNCTION(J1_MW_DXFR_32, J1_lm_rdynR, J1_last_xfr_lc1);


--J1_dati_hr_ena_lc is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|dati_hr_ena_lc
--operation mode is normal

J1_dati_hr_ena_lc = AMPP_FUNCTION(J1_MS_DXFR, J1_MW_WAIT);

--J1L551 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|dati_hr_ena_lc~15
--operation mode is normal

J1L551 = AMPP_FUNCTION(J1_MS_DXFR, J1_MW_WAIT);


--M1_dati_hr_ena_lc is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|dati_hr_ena_lc
--operation mode is normal

M1_dati_hr_ena_lc = AMPP_FUNCTION(M1_LR_PXFR, M1_LR_LXFR, M1_LR_DONE);

--M1L271 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|dati_hr_ena_lc~15
--operation mode is normal

M1L271 = AMPP_FUNCTION(M1_LR_PXFR, M1_LR_LXFR, M1_LR_DONE);


--R1_dec_up[1] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|pcimt32_cd:cfg_adr_dec|dec_up[1]
--operation mode is normal

R1_dec_up[1] = AMPP_FUNCTION(G1_ad_ir_address[4], G1_ad_ir_address[5], G1_ad_ir_address[6], G1_ad_ir_address[7]);

--R1L7 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|pcimt32_cd:cfg_adr_dec|dec_up[1]~55
--operation mode is normal

R1L7 = AMPP_FUNCTION(G1_ad_ir_address[4], G1_ad_ir_address[5], G1_ad_ir_address[6], G1_ad_ir_address[7]);


--J1_MS_TAR_R is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MS_TAR_R
--operation mode is normal

J1_MS_TAR_R = AMPP_FUNCTION(J1_MS_TAR, pci_rstn, GLOBAL(pci_clk));

--J1L614Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MS_TAR_R~6
--operation mode is normal

J1L614Q = AMPP_FUNCTION(J1_MS_TAR, pci_rstn, GLOBAL(pci_clk));


--P1_par_rep_rst is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|par_rep_rst
--operation mode is normal

P1_par_rep_rst = AMPP_FUNCTION(G1_low_ad_IR_data[24], M1_cfg_dat_vld, R1_decR[1], G1_low_cben_IR_data[3]);

--P1L071 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|par_rep_rst~10
--operation mode is normal

P1L071 = AMPP_FUNCTION(G1_low_ad_IR_data[24], M1_cfg_dat_vld, R1_decR[1], G1_low_cben_IR_data[3]);


--P1_targ_abrt_rcvd_rst is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|targ_abrt_rcvd_rst
--operation mode is normal

P1_targ_abrt_rcvd_rst = AMPP_FUNCTION(G1_low_ad_IR_data[28], M1_cfg_dat_vld, R1_decR[1], G1_low_cben_IR_data[3]);

--P1L681 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|targ_abrt_rcvd_rst~10
--operation mode is normal

P1L681 = AMPP_FUNCTION(G1_low_ad_IR_data[28], M1_cfg_dat_vld, R1_decR[1], G1_low_cben_IR_data[3]);


--P1_mstr_abrt_rst is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|mstr_abrt_rst
--operation mode is normal

P1_mstr_abrt_rst = AMPP_FUNCTION(G1_low_ad_IR_data[29], M1_cfg_dat_vld, R1_decR[1], G1_low_cben_IR_data[3]);

--P1L761 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|mstr_abrt_rst~10
--operation mode is normal

P1L761 = AMPP_FUNCTION(G1_low_ad_IR_data[29], M1_cfg_dat_vld, R1_decR[1], G1_low_cben_IR_data[3]);


--P1_serr_rst is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|serr_rst
--operation mode is normal

P1_serr_rst = AMPP_FUNCTION(G1_low_ad_IR_data[30], M1_cfg_dat_vld, R1_decR[1], G1_low_cben_IR_data[3]);

--P1L671 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|serr_rst~10
--operation mode is normal

P1L671 = AMPP_FUNCTION(G1_low_ad_IR_data[30], M1_cfg_dat_vld, R1_decR[1], G1_low_cben_IR_data[3]);


--P1_perr_det_rst is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|perr_det_rst
--operation mode is normal

P1_perr_det_rst = AMPP_FUNCTION(G1_low_ad_IR_data[31], M1_cfg_dat_vld, R1_decR[1], G1_low_cben_IR_data[3]);

--P1L371 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|perr_det_rst~10
--operation mode is normal

P1L371 = AMPP_FUNCTION(G1_low_ad_IR_data[31], M1_cfg_dat_vld, R1_decR[1], G1_low_cben_IR_data[3]);


--J1_latcntr_tor_carry is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|latcntr_tor_carry
--operation mode is arithmetic

J1_latcntr_tor_carry = AMPP_FUNCTION();

--J1L662 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|latcntr_tor_carry~18
--operation mode is arithmetic

J1L662 = AMPP_FUNCTION();

--J1L762 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|latcntr_tor_carry~COUT
--operation mode is arithmetic

J1L762 = AMPP_FUNCTION(pci_gntn, J1L58);


--J1_MW_DXFR_32_r[3] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_DXFR_32_r[3]
--operation mode is normal

J1_MW_DXFR_32_r[3] = AMPP_FUNCTION(A1L5421, J1_lm_rdynR, J1_MW_DXFR_32, pci_rstn, GLOBAL(pci_clk), J1L95);

--J1L244Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_DXFR_32_r[3]~21
--operation mode is normal

J1L244Q = AMPP_FUNCTION(A1L5421, J1_lm_rdynR, J1_MW_DXFR_32, pci_rstn, GLOBAL(pci_clk), J1L95);


--J1_MW_DXFR_32_r[2] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_DXFR_32_r[2]
--operation mode is normal

J1_MW_DXFR_32_r[2] = AMPP_FUNCTION(J1_MW_DXFR_32_lc[2], A1L5421, J1_MW_DXFR_32_lc[3], pci_rstn, GLOBAL(pci_clk), J1L65);

--J1L044Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_DXFR_32_r[2]~22
--operation mode is normal

J1L044Q = AMPP_FUNCTION(J1_MW_DXFR_32_lc[2], A1L5421, J1_MW_DXFR_32_lc[3], pci_rstn, GLOBAL(pci_clk), J1L65);


--J1_MW_DXFR_32_r[1] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_DXFR_32_r[1]
--operation mode is normal

J1_MW_DXFR_32_r[1] = AMPP_FUNCTION(A1L5421, J1_MW_DXFR_32_lc[1], J1_MW_WAIT_32_lc[2], J1_latcntr_toR, pci_rstn, GLOBAL(pci_clk), J1L35);

--J1L834Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_DXFR_32_r[1]~23
--operation mode is normal

J1L834Q = AMPP_FUNCTION(A1L5421, J1_MW_DXFR_32_lc[1], J1_MW_WAIT_32_lc[2], J1_latcntr_toR, pci_rstn, GLOBAL(pci_clk), J1L35);


--J1_MW_DXFR_32 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_DXFR_32
--operation mode is normal

J1_MW_DXFR_32 = AMPP_FUNCTION(J1_MW_DXFR_32_r[3], J1_MW_DXFR_32_r[2], J1_MW_DXFR_32_r[1]);

--J1L444 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_DXFR_32~22
--operation mode is normal

J1L444 = AMPP_FUNCTION(J1_MW_DXFR_32_r[3], J1_MW_DXFR_32_r[2], J1_MW_DXFR_32_r[1]);


--J1_MW_LXFR_lc[1] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_LXFR_lc[1]
--operation mode is normal

J1_MW_LXFR_lc[1] = AMPP_FUNCTION(J1_MW_LXFR, J1_lm_rdynR, J1_devsel_toR);

--J1L115 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_LXFR_lc[1]~54
--operation mode is normal

J1L115 = AMPP_FUNCTION(J1_MW_LXFR, J1_lm_rdynR, J1_devsel_toR);


--J1_MW_LXFR_lc[2] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_LXFR_lc[2]
--operation mode is normal

J1_MW_LXFR_lc[2] = AMPP_FUNCTION(J1_lm_rdynR, J1_MW_DXFR, J1_devsel_toR);

--J1L415 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_LXFR_lc[2]~55
--operation mode is normal

J1L415 = AMPP_FUNCTION(J1_lm_rdynR, J1_MW_DXFR, J1_devsel_toR);


--J1L592 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_IDLE_lc1~24
--operation mode is normal

J1L592 = AMPP_FUNCTION(J1_MS_ADR2, J1_MS_ADR, J1_dac_cyc_reg);

--J1L892 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_IDLE_lc1~27
--operation mode is normal

J1L892 = AMPP_FUNCTION(J1_MS_ADR2, J1_MS_ADR, J1_dac_cyc_reg);


--J1_MR_PXFR_lc1 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_PXFR_lc1
--operation mode is normal

J1_MR_PXFR_lc1 = AMPP_FUNCTION(J1L592, J1_MR_IDLE_not, J1_wr_rdn);

--J1L853 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_PXFR_lc1~36
--operation mode is normal

J1L853 = AMPP_FUNCTION(J1L592, J1_MR_IDLE_not, J1_wr_rdn);


--J1_no_op_reg[4] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|no_op_reg[4]
--operation mode is normal

J1_no_op_reg[4] = AMPP_FUNCTION(pci_rstn, GLOBAL(pci_clk));

--J1L275Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|no_op_reg[4]~23
--operation mode is normal

J1L275Q = AMPP_FUNCTION(pci_rstn, GLOBAL(pci_clk));


--J1L36 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|$00217~0
--operation mode is normal

J1L36 = AMPP_FUNCTION(A1L7421, J1_no_op_reg[4]);

--J1L46 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|$00217~10
--operation mode is normal

J1L46 = AMPP_FUNCTION(A1L7421, J1_no_op_reg[4]);

--J1L56 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|$00217~11
--operation mode is normal

J1L56 = AMPP_FUNCTION(A1L7421, J1_no_op_reg[4]);


--J1L63 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|$00186~0
--operation mode is normal

J1L63 = AMPP_FUNCTION(J1_no_op_reg[1], A1L7421, J1_devsel_toR);

--J1L73 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|$00186~10
--operation mode is normal

J1L73 = AMPP_FUNCTION(J1_no_op_reg[1], A1L7421, J1_devsel_toR);

--J1L83 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|$00186~11
--operation mode is normal

J1L83 = AMPP_FUNCTION(J1_no_op_reg[1], A1L7421, J1_devsel_toR);


--J1L03 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|$00184~0
--operation mode is normal

J1L03 = AMPP_FUNCTION(J1_no_op_reg[3], J1_no_op_reg[2], J1_no_op_reg[1], A1L7421);

--J1L13 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|$00184~10
--operation mode is normal

J1L13 = AMPP_FUNCTION(J1_no_op_reg[3], J1_no_op_reg[2], J1_no_op_reg[1], A1L7421);

--J1L23 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|$00184~11
--operation mode is normal

J1L23 = AMPP_FUNCTION(J1_no_op_reg[3], J1_no_op_reg[2], J1_no_op_reg[1], A1L7421);


--J1L33 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|$00185~0
--operation mode is normal

J1L33 = AMPP_FUNCTION(J1_MW_LXFR, J1_devsel_toR);

--J1L43 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|$00185~10
--operation mode is normal

J1L43 = AMPP_FUNCTION(J1_MW_LXFR, J1_devsel_toR);

--J1L53 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|$00185~11
--operation mode is normal

J1L53 = AMPP_FUNCTION(J1_MW_LXFR, J1_devsel_toR);


--J1_MR_LPXFR_lc2 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LPXFR_lc2
--operation mode is normal

J1_MR_LPXFR_lc2 = AMPP_FUNCTION(J1_MR_LPXFR, J1_devsel_toR);

--J1L733 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LPXFR_lc2~8
--operation mode is normal

J1L733 = AMPP_FUNCTION(J1_MR_LPXFR, J1_devsel_toR);


--L1_par[7] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pg:parity_gen|par[7]
--operation mode is normal

L1_par[7] = AMPP_FUNCTION(G1_low_ad_or[28], G1_low_ad_or[29], G1_low_ad_or[30], G1_low_ad_or[31]);

--L1L52 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pg:parity_gen|par[7]~192
--operation mode is normal

L1L52 = AMPP_FUNCTION(G1_low_ad_or[28], G1_low_ad_or[29], G1_low_ad_or[30], G1_low_ad_or[31]);


--L1_par[6] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pg:parity_gen|par[6]
--operation mode is normal

L1_par[6] = AMPP_FUNCTION(G1_low_ad_or[24], G1_low_ad_or[25], G1_low_ad_or[26], G1_low_ad_or[27]);

--L1L22 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pg:parity_gen|par[6]~193
--operation mode is normal

L1L22 = AMPP_FUNCTION(G1_low_ad_or[24], G1_low_ad_or[25], G1_low_ad_or[26], G1_low_ad_or[27]);


--L1_par[5] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pg:parity_gen|par[5]
--operation mode is normal

L1_par[5] = AMPP_FUNCTION(G1_low_ad_or[20], G1_low_ad_or[21], G1_low_ad_or[22], G1_low_ad_or[23]);

--L1L91 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pg:parity_gen|par[5]~194
--operation mode is normal

L1L91 = AMPP_FUNCTION(G1_low_ad_or[20], G1_low_ad_or[21], G1_low_ad_or[22], G1_low_ad_or[23]);


--L1_par[4] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pg:parity_gen|par[4]
--operation mode is normal

L1_par[4] = AMPP_FUNCTION(G1_low_ad_or[16], G1_low_ad_or[17], G1_low_ad_or[18], G1_low_ad_or[19]);

--L1L61 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pg:parity_gen|par[4]~195
--operation mode is normal

L1L61 = AMPP_FUNCTION(G1_low_ad_or[16], G1_low_ad_or[17], G1_low_ad_or[18], G1_low_ad_or[19]);


--L1_par[3] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pg:parity_gen|par[3]
--operation mode is normal

L1_par[3] = AMPP_FUNCTION(G1_low_ad_or[12], G1_low_ad_or[13], G1_low_ad_or[14], G1_low_ad_or[15]);

--L1L31 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pg:parity_gen|par[3]~196
--operation mode is normal

L1L31 = AMPP_FUNCTION(G1_low_ad_or[12], G1_low_ad_or[13], G1_low_ad_or[14], G1_low_ad_or[15]);


--L1_par[2] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pg:parity_gen|par[2]
--operation mode is normal

L1_par[2] = AMPP_FUNCTION(G1_low_ad_or[8], G1_low_ad_or[9], G1_low_ad_or[10], G1_low_ad_or[11]);

--L1L01 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pg:parity_gen|par[2]~197
--operation mode is normal

L1L01 = AMPP_FUNCTION(G1_low_ad_or[8], G1_low_ad_or[9], G1_low_ad_or[10], G1_low_ad_or[11]);


--L1_par[1] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pg:parity_gen|par[1]
--operation mode is normal

L1_par[1] = AMPP_FUNCTION(G1_low_ad_or[4], G1_low_ad_or[5], G1_low_ad_or[6], G1_low_ad_or[7]);

--L1L7 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pg:parity_gen|par[1]~198
--operation mode is normal

L1L7 = AMPP_FUNCTION(G1_low_ad_or[4], G1_low_ad_or[5], G1_low_ad_or[6], G1_low_ad_or[7]);


--L1_par[0] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pg:parity_gen|par[0]
--operation mode is normal

L1_par[0] = AMPP_FUNCTION(G1_low_ad_or[0], G1_low_ad_or[1], G1_low_ad_or[2], G1_low_ad_or[3]);

--L1L4 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_pg:parity_gen|par[0]~199
--operation mode is normal

L1L4 = AMPP_FUNCTION(G1_low_ad_or[0], G1_low_ad_or[1], G1_low_ad_or[2], G1_low_ad_or[3]);


--M1_LW_DONE_lc[1] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LW_DONE_lc[1]
--operation mode is normal

M1_LW_DONE_lc[1] = AMPP_FUNCTION(M1_TS_DISC, dpm_dec_reg_LT_RDY_n_pci);

--M1L283 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LW_DONE_lc[1]~17
--operation mode is normal

M1L283 = AMPP_FUNCTION(M1_TS_DISC, dpm_dec_reg_LT_RDY_n_pci);


--M1_LR_DONE_lc[2] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_DONE_lc[2]
--operation mode is normal

M1_LR_DONE_lc[2] = AMPP_FUNCTION(M1_LR_PXFR, M1_LR_WAIT, M1_LR_PXFR_32, M1_LR_WAIT_32);

--M1L491 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_DONE_lc[2]~27
--operation mode is normal

M1L491 = AMPP_FUNCTION(M1_LR_PXFR, M1_LR_WAIT, M1_LR_PXFR_32, M1_LR_WAIT_32);


--M1_LR_DONE_lc[1] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_DONE_lc[1]
--operation mode is normal

M1_LR_DONE_lc[1] = AMPP_FUNCTION(M1_TS_DISC, M1_LR_PXFR, M1_LR_LXFR, M1_LR_LXFR_lc[1]);

--M1L191 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_DONE_lc[1]~28
--operation mode is normal

M1L191 = AMPP_FUNCTION(M1_TS_DISC, M1_LR_PXFR, M1_LR_LXFR, M1_LR_LXFR_lc[1]);


--M1_LR_IDLE_lc1 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_IDLE_lc1
--operation mode is normal

M1_LR_IDLE_lc1 = AMPP_FUNCTION(M1L891, N3_REG);

--M1L991 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_IDLE_lc1~35
--operation mode is normal

M1L991 = AMPP_FUNCTION(M1L891, N3_REG);


--dpm_dec_reg_tmp1 is dpm_dec_reg_tmp1
--operation mode is normal

dpm_dec_reg_tmp1_lut_out = dpm_dec_reg_tmp;
dpm_dec_reg_tmp1 = DFFEA(dpm_dec_reg_tmp1_lut_out, GLOBAL(pci_clk), pci_rstn, , , , );

--A1L46Q is dpm_dec_reg_tmp1~1
--operation mode is normal

A1L46Q = dpm_dec_reg_tmp1;


--M1L66 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|_~210
--operation mode is normal

M1L66 = AMPP_FUNCTION(A1L5321, A1L0321);

--M1L411 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|_~1523
--operation mode is normal

M1L411 = AMPP_FUNCTION(A1L5321, A1L0321);

--M1L511 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|_~1524
--operation mode is normal

M1L511 = AMPP_FUNCTION(A1L5321, A1L0321);


--dpm_ni2f_fifo_l_reg_nwords_10 is dpm_ni2f_fifo_l_reg_nwords_10
--operation mode is normal

dpm_ni2f_fifo_l_reg_nwords_10_lut_out = !A1L656;
dpm_ni2f_fifo_l_reg_nwords_10 = DFFEA(dpm_ni2f_fifo_l_reg_nwords_10_lut_out, lcst, !dpm_ni2f_reg_sreset120, , ix2286_lc, , );

--A1L522Q is dpm_ni2f_fifo_l_reg_nwords_10~1
--operation mode is normal

A1L522Q = dpm_ni2f_fifo_l_reg_nwords_10;


--dpm_ni2f_fifo_l_reg_nwords_9 is dpm_ni2f_fifo_l_reg_nwords_9
--operation mode is normal

dpm_ni2f_fifo_l_reg_nwords_9_lut_out = !A1L856;
dpm_ni2f_fifo_l_reg_nwords_9 = DFFEA(dpm_ni2f_fifo_l_reg_nwords_9_lut_out, lcst, !dpm_ni2f_reg_sreset120, , ix2286_lc, , );

--A1L322Q is dpm_ni2f_fifo_l_reg_nwords_9~1
--operation mode is normal

A1L322Q = dpm_ni2f_fifo_l_reg_nwords_9;


--dpm_ni2f_fifo_l_reg_nwords_8 is dpm_ni2f_fifo_l_reg_nwords_8
--operation mode is normal

dpm_ni2f_fifo_l_reg_nwords_8_lut_out = !A1L066;
dpm_ni2f_fifo_l_reg_nwords_8 = DFFEA(dpm_ni2f_fifo_l_reg_nwords_8_lut_out, lcst, !dpm_ni2f_reg_sreset120, , ix2286_lc, , );

--A1L122Q is dpm_ni2f_fifo_l_reg_nwords_8~1
--operation mode is normal

A1L122Q = dpm_ni2f_fifo_l_reg_nwords_8;


--dpm_ni2f_fifo_l_reg_nwords_7 is dpm_ni2f_fifo_l_reg_nwords_7
--operation mode is normal

dpm_ni2f_fifo_l_reg_nwords_7_lut_out = !A1L266;
dpm_ni2f_fifo_l_reg_nwords_7 = DFFEA(dpm_ni2f_fifo_l_reg_nwords_7_lut_out, lcst, !dpm_ni2f_reg_sreset120, , ix2286_lc, , );

--A1L912Q is dpm_ni2f_fifo_l_reg_nwords_7~1
--operation mode is normal

A1L912Q = dpm_ni2f_fifo_l_reg_nwords_7;


--dpm_ni2f_fifo_l_modgen_eq_69_ix17 is dpm_ni2f_fifo_l_modgen_eq_69_ix17
--operation mode is normal

dpm_ni2f_fifo_l_modgen_eq_69_ix17 = dpm_ni2f_fifo_l_reg_nwords_10 & dpm_ni2f_fifo_l_reg_nwords_9 & dpm_ni2f_fifo_l_reg_nwords_8 & dpm_ni2f_fifo_l_reg_nwords_7;

--A1L581 is dpm_ni2f_fifo_l_modgen_eq_69_ix17~1
--operation mode is normal

A1L581 = dpm_ni2f_fifo_l_reg_nwords_10 & dpm_ni2f_fifo_l_reg_nwords_9 & dpm_ni2f_fifo_l_reg_nwords_8 & dpm_ni2f_fifo_l_reg_nwords_7;

--A1L681 is dpm_ni2f_fifo_l_modgen_eq_69_ix17~2
--operation mode is normal

A1L681 = dpm_ni2f_fifo_l_reg_nwords_10 & dpm_ni2f_fifo_l_reg_nwords_9 & dpm_ni2f_fifo_l_reg_nwords_8 & dpm_ni2f_fifo_l_reg_nwords_7;


--dpm_ni2f_fifo_l_reg_nwords_6 is dpm_ni2f_fifo_l_reg_nwords_6
--operation mode is normal

dpm_ni2f_fifo_l_reg_nwords_6_lut_out = !A1L466;
dpm_ni2f_fifo_l_reg_nwords_6 = DFFEA(dpm_ni2f_fifo_l_reg_nwords_6_lut_out, lcst, !dpm_ni2f_reg_sreset120, , ix2286_lc, , );

--A1L712Q is dpm_ni2f_fifo_l_reg_nwords_6~1
--operation mode is normal

A1L712Q = dpm_ni2f_fifo_l_reg_nwords_6;


--dpm_ni2f_fifo_l_reg_nwords_5 is dpm_ni2f_fifo_l_reg_nwords_5
--operation mode is normal

dpm_ni2f_fifo_l_reg_nwords_5_lut_out = !A1L666;
dpm_ni2f_fifo_l_reg_nwords_5 = DFFEA(dpm_ni2f_fifo_l_reg_nwords_5_lut_out, lcst, !dpm_ni2f_reg_sreset120, , ix2286_lc, , );

--A1L512Q is dpm_ni2f_fifo_l_reg_nwords_5~1
--operation mode is normal

A1L512Q = dpm_ni2f_fifo_l_reg_nwords_5;


--dpm_ni2f_fifo_l_reg_nwords_4 is dpm_ni2f_fifo_l_reg_nwords_4
--operation mode is normal

dpm_ni2f_fifo_l_reg_nwords_4_lut_out = !A1L866;
dpm_ni2f_fifo_l_reg_nwords_4 = DFFEA(dpm_ni2f_fifo_l_reg_nwords_4_lut_out, lcst, !dpm_ni2f_reg_sreset120, , ix2286_lc, , );

--A1L312Q is dpm_ni2f_fifo_l_reg_nwords_4~1
--operation mode is normal

A1L312Q = dpm_ni2f_fifo_l_reg_nwords_4;


--dpm_ni2f_fifo_l_reg_nwords_3 is dpm_ni2f_fifo_l_reg_nwords_3
--operation mode is normal

dpm_ni2f_fifo_l_reg_nwords_3_lut_out = !A1L076;
dpm_ni2f_fifo_l_reg_nwords_3 = DFFEA(dpm_ni2f_fifo_l_reg_nwords_3_lut_out, lcst, !dpm_ni2f_reg_sreset120, , ix2286_lc, , );

--A1L112Q is dpm_ni2f_fifo_l_reg_nwords_3~1
--operation mode is normal

A1L112Q = dpm_ni2f_fifo_l_reg_nwords_3;


--A1L781 is dpm_ni2f_fifo_l_modgen_eq_69_ix21~0
--operation mode is normal

A1L781 = (dpm_ni2f_fifo_l_reg_nwords_6 & dpm_ni2f_fifo_l_reg_nwords_5 & dpm_ni2f_fifo_l_reg_nwords_4 & dpm_ni2f_fifo_l_reg_nwords_3) & CASCADE(A1L681);

--A1L881 is dpm_ni2f_fifo_l_modgen_eq_69_ix21~2
--operation mode is normal

A1L881 = (dpm_ni2f_fifo_l_reg_nwords_6 & dpm_ni2f_fifo_l_reg_nwords_5 & dpm_ni2f_fifo_l_reg_nwords_4 & dpm_ni2f_fifo_l_reg_nwords_3) & CASCADE(A1L681);

--A1L981 is dpm_ni2f_fifo_l_modgen_eq_69_ix21~3
--operation mode is normal

A1L981 = (dpm_ni2f_fifo_l_reg_nwords_6 & dpm_ni2f_fifo_l_reg_nwords_5 & dpm_ni2f_fifo_l_reg_nwords_4 & dpm_ni2f_fifo_l_reg_nwords_3) & CASCADE(A1L681);


--dpm_ni2f_fifo_l_modgen_eq_73_ix17 is dpm_ni2f_fifo_l_modgen_eq_73_ix17
--operation mode is normal

dpm_ni2f_fifo_l_modgen_eq_73_ix17 = !dpm_ni2f_fifo_l_reg_nwords_10 & !dpm_ni2f_fifo_l_reg_nwords_9 & !dpm_ni2f_fifo_l_reg_nwords_8 & !dpm_ni2f_fifo_l_reg_nwords_7;

--A1L391 is dpm_ni2f_fifo_l_modgen_eq_73_ix17~1
--operation mode is normal

A1L391 = !dpm_ni2f_fifo_l_reg_nwords_10 & !dpm_ni2f_fifo_l_reg_nwords_9 & !dpm_ni2f_fifo_l_reg_nwords_8 & !dpm_ni2f_fifo_l_reg_nwords_7;

--A1L491 is dpm_ni2f_fifo_l_modgen_eq_73_ix17~2
--operation mode is normal

A1L491 = !dpm_ni2f_fifo_l_reg_nwords_10 & !dpm_ni2f_fifo_l_reg_nwords_9 & !dpm_ni2f_fifo_l_reg_nwords_8 & !dpm_ni2f_fifo_l_reg_nwords_7;


--A1L591 is dpm_ni2f_fifo_l_modgen_eq_73_ix21~0
--operation mode is normal

A1L591 = (!dpm_ni2f_fifo_l_reg_nwords_6 & !dpm_ni2f_fifo_l_reg_nwords_5 & !dpm_ni2f_fifo_l_reg_nwords_4 & !dpm_ni2f_fifo_l_reg_nwords_3) & CASCADE(A1L491);

--A1L691 is dpm_ni2f_fifo_l_modgen_eq_73_ix21~2
--operation mode is normal

A1L691 = (!dpm_ni2f_fifo_l_reg_nwords_6 & !dpm_ni2f_fifo_l_reg_nwords_5 & !dpm_ni2f_fifo_l_reg_nwords_4 & !dpm_ni2f_fifo_l_reg_nwords_3) & CASCADE(A1L491);

--A1L791 is dpm_ni2f_fifo_l_modgen_eq_73_ix21~3
--operation mode is normal

A1L791 = (!dpm_ni2f_fifo_l_reg_nwords_6 & !dpm_ni2f_fifo_l_reg_nwords_5 & !dpm_ni2f_fifo_l_reg_nwords_4 & !dpm_ni2f_fifo_l_reg_nwords_3) & CASCADE(A1L491);


--J1_MR_LLWAIT_r1_lc1 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LLWAIT_r1_lc1
--operation mode is normal

J1_MR_LLWAIT_r1_lc1 = AMPP_FUNCTION(J1_MR_PXFR, J1_devsel_toR);

--J1L703 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LLWAIT_r1_lc1~1
--operation mode is normal

J1L703 = AMPP_FUNCTION(J1_MR_PXFR, J1_devsel_toR);


--J1_MW_END_r1_carry is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_END_r1_carry
--operation mode is arithmetic

J1_MW_END_r1_carry = AMPP_FUNCTION();

--J1L664 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_END_r1_carry~25
--operation mode is arithmetic

J1L664 = AMPP_FUNCTION();

--J1L764 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_END_r1_carry~COUT
--operation mode is arithmetic

J1L764 = AMPP_FUNCTION(A1L7421, J1_MW_LAST);


--E1_counter_cell[6] is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[6]
--operation mode is up_dn_cntr

E1_counter_cell[6]_lut_out = E1_counter_cell[6] $ E1L91;
E1_counter_cell[6] = DFFEA(E1_counter_cell[6]_lut_out, GLOBAL(pci_clk), , , , , );

--E1L12Q is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[6]~8
--operation mode is up_dn_cntr

E1L12Q = E1_counter_cell[6];

--E1L22 is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[6]~COUT
--operation mode is up_dn_cntr

E1L22 = CARRY(E1_counter_cell[6] & (E1L91));


--M1_LR_PXFR_r1_carry[1] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_PXFR_r1_carry[1]
--operation mode is arithmetic

M1_LR_PXFR_r1_carry[1] = AMPP_FUNCTION();

--M1L562 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_PXFR_r1_carry[1]~50
--operation mode is arithmetic

M1L562 = AMPP_FUNCTION();

--M1L662 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_PXFR_r1_carry[1]~COUT
--operation mode is arithmetic

M1L662 = AMPP_FUNCTION(M1_LR_PXFR_lc[2]);


--M1L052 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_PXFR_cc1~11
--operation mode is normal

M1L052 = AMPP_FUNCTION(M1_TS_DISC, M1_lt_rdynR, M1_LR_LXFR_lc[1]);

--M1L152 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_PXFR_cc1~13
--operation mode is normal

M1L152 = AMPP_FUNCTION(M1_TS_DISC, M1_lt_rdynR, M1_LR_LXFR_lc[1]);

--M1L252 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_PXFR_cc1~14
--operation mode is normal

M1L252 = AMPP_FUNCTION(M1_TS_DISC, M1_lt_rdynR, M1_LR_LXFR_lc[1]);


--M1_LR_WAIT_lc[1] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_WAIT_lc[1]
--operation mode is normal

M1_LR_WAIT_lc[1] = AMPP_FUNCTION(M1_LR_PXFR, M1_TS_DISC);

--M1L382 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_WAIT_lc[1]~1
--operation mode is normal

M1L382 = AMPP_FUNCTION(M1_LR_PXFR, M1_TS_DISC);


--M1_retry_set_lc is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|retry_set_lc
--operation mode is normal

M1_retry_set_lc = AMPP_FUNCTION(M1_adr_phase_lc1, J1_mstr_actv_lc, M1_TS_IDLE_NOT);

--M1L444 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|retry_set_lc~8
--operation mode is normal

M1L444 = AMPP_FUNCTION(M1_adr_phase_lc1, J1_mstr_actv_lc, M1_TS_IDLE_NOT);


--M1_retry_rst_lc1 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|retry_rst_lc1
--operation mode is normal

M1_retry_rst_lc1 = AMPP_FUNCTION(M1_LW_DONE, M1_LW_IDLE_NOT);

--M1L634 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|retry_rst_lc1~1
--operation mode is normal

M1L634 = AMPP_FUNCTION(M1_LW_DONE, M1_LW_IDLE_NOT);


--M1L54 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|$00187~0
--operation mode is normal

M1L54 = AMPP_FUNCTION(M1_TS_ADR_VLD, M1_LR_IDLE_NOT, K1_serr_or, M1_cfg_cyc);

--M1L64 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|$00187~10
--operation mode is normal

M1L64 = AMPP_FUNCTION(M1_TS_ADR_VLD, M1_LR_IDLE_NOT, K1_serr_or, M1_cfg_cyc);

--M1L74 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|$00187~11
--operation mode is normal

M1L74 = AMPP_FUNCTION(M1_TS_ADR_VLD, M1_LR_IDLE_NOT, K1_serr_or, M1_cfg_cyc);


--J1_devselR is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|devselR
--operation mode is normal

J1_devselR = AMPP_FUNCTION(A1L8221, pci_rstn, GLOBAL(pci_clk));

--J1L261Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|devselR~1
--operation mode is normal

J1L261Q = AMPP_FUNCTION(A1L8221, pci_rstn, GLOBAL(pci_clk));


--J1_$00067 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|$00067
--operation mode is normal

J1_$00067 = AMPP_FUNCTION(J1_MS_DXFR, J1_devselR);

--J1L6 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|$00067~8
--operation mode is normal

J1L6 = AMPP_FUNCTION(J1_MS_DXFR, J1_devselR);


--J1_latcntr_toR_lc1 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|latcntr_toR_lc1
--operation mode is normal

J1_latcntr_toR_lc1 = AMPP_FUNCTION(J1_MS_ENA, J1_MS_REQ);

--J1L962 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|latcntr_toR_lc1~1
--operation mode is normal

J1L962 = AMPP_FUNCTION(J1_MS_ENA, J1_MS_REQ);


--J1_latcntr_toR_lc2 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|latcntr_toR_lc2
--operation mode is normal

J1_latcntr_toR_lc2 = AMPP_FUNCTION(J1_MS_TAR, J1_MS_ENA, J1_MS_REQ, J1_MS_IDLE_not);

--J1L172 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|latcntr_toR_lc2~1
--operation mode is normal

J1L172 = AMPP_FUNCTION(J1_MS_TAR, J1_MS_ENA, J1_MS_REQ, J1_MS_IDLE_not);


--J1L06 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|$00212~0
--operation mode is normal

J1L06 = AMPP_FUNCTION(A1L7421, J1_devsel_toR);

--J1L16 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|$00212~11
--operation mode is normal

J1L16 = AMPP_FUNCTION(A1L7421, J1_devsel_toR);

--J1L26 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|$00212~12
--operation mode is normal

J1L26 = AMPP_FUNCTION(A1L7421, J1_devsel_toR);


--J1L023 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LLXFR_r1_d~1
--operation mode is normal

J1L023 = AMPP_FUNCTION(J1_no_op_reg[1], A1L7421);

--J1L123 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LLXFR_r1_d~31
--operation mode is normal

J1L123 = AMPP_FUNCTION(J1_no_op_reg[1], A1L7421);

--J1L223 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LLXFR_r1_d~32
--operation mode is normal

J1L223 = AMPP_FUNCTION(J1_no_op_reg[1], A1L7421);


--J1L93 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|$00191~0
--operation mode is normal

J1L93 = AMPP_FUNCTION(A1L7421, J1_no_op_reg[1]);

--J1L04 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|$00191~10
--operation mode is normal

J1L04 = AMPP_FUNCTION(A1L7421, J1_no_op_reg[1]);

--J1L14 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|$00191~11
--operation mode is normal

J1L14 = AMPP_FUNCTION(A1L7421, J1_no_op_reg[1]);


--J1_MW_DXFR_lc[1] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_DXFR_lc[1]
--operation mode is normal

J1_MW_DXFR_lc[1] = AMPP_FUNCTION(J1_lm_rdynR, J1_MW_DXFR_32, J1_last_xfr_lc1);

--J1L844 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_DXFR_lc[1]~28
--operation mode is normal

J1L844 = AMPP_FUNCTION(J1_lm_rdynR, J1_MW_DXFR_32, J1_last_xfr_lc1);


--J1L333 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LPXFR_lc1~16
--operation mode is normal

J1L333 = AMPP_FUNCTION(J1_last_xfr, J1_MR_IDLE_not, J1L692);

--J1L433 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LPXFR_lc1~17
--operation mode is normal

J1L433 = AMPP_FUNCTION(J1_last_xfr, J1_MR_IDLE_not, J1L692);


--J1_no_op_reg[5] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|no_op_reg[5]
--operation mode is normal

J1_no_op_reg[5] = AMPP_FUNCTION(pci_rstn, GLOBAL(pci_clk));

--J1L475Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|no_op_reg[5]~24
--operation mode is normal

J1L475Q = AMPP_FUNCTION(pci_rstn, GLOBAL(pci_clk));


--dpm_dec_reg_tmp is dpm_dec_reg_tmp
--operation mode is normal

dpm_dec_reg_tmp_lut_out = M1_TS_IDLE_NOT & P1_bar_hitR[0];
dpm_dec_reg_tmp = DFFEA(dpm_dec_reg_tmp_lut_out, GLOBAL(pci_clk), pci_rstn, , , , );

--A1L96Q is dpm_dec_reg_tmp~0
--operation mode is normal

A1L96Q = dpm_dec_reg_tmp;


--ix2286_lc is ix2286_lc
--operation mode is normal

ix2286_lc = dpm_ni2f_reg_rdreq_fifo & (dpm_ni2f_fifo_l_reg_fifo_empty $ (dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_l_reg_fifo_full)) # !dpm_ni2f_reg_rdreq_fifo & dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_l_reg_fifo_full;

--A1L686 is ix2286_lc~0
--operation mode is normal

A1L686 = dpm_ni2f_reg_rdreq_fifo & (dpm_ni2f_fifo_l_reg_fifo_empty $ (dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_l_reg_fifo_full)) # !dpm_ni2f_reg_rdreq_fifo & dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_l_reg_fifo_full;


--J1_MW_END_lc1 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_END_lc1
--operation mode is normal

J1_MW_END_lc1 = AMPP_FUNCTION(J1_MW_LAST, J1_MW_DXFR, J1_MW_WAIT);

--J1L364 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_END_lc1~20
--operation mode is normal

J1L364 = AMPP_FUNCTION(J1_MW_LAST, J1_MW_DXFR, J1_MW_WAIT);


--E1_counter_cell[5] is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[5]
--operation mode is up_dn_cntr

E1_counter_cell[5]_lut_out = E1_counter_cell[5] $ E1L61;
E1_counter_cell[5] = DFFEA(E1_counter_cell[5]_lut_out, GLOBAL(pci_clk), , , , , );

--E1L81Q is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[5]~9
--operation mode is up_dn_cntr

E1L81Q = E1_counter_cell[5];

--E1L91 is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[5]~COUT
--operation mode is up_dn_cntr

E1L91 = CARRY(E1_counter_cell[5] & (E1L61));


--M1_LR_PXFR_32_r1_carry[1] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_PXFR_32_r1_carry[1]
--operation mode is arithmetic

M1_LR_PXFR_32_r1_carry[1] = AMPP_FUNCTION();

--M1L042 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_PXFR_32_r1_carry[1]~50
--operation mode is arithmetic

M1L042 = AMPP_FUNCTION();

--M1L142 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_PXFR_32_r1_carry[1]~COUT
--operation mode is arithmetic

M1L142 = AMPP_FUNCTION(M1_LR_PXFR_32);


--M1L032 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_PXFR_32_cc1~0
--operation mode is normal

M1L032 = AMPP_FUNCTION(M1_lt_rdynR, M1_LR_LXFR_lc[1]);

--M1L132 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_PXFR_32_cc1~10
--operation mode is normal

M1L132 = AMPP_FUNCTION(M1_lt_rdynR, M1_LR_LXFR_lc[1]);

--M1L232 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_PXFR_32_cc1~11
--operation mode is normal

M1L232 = AMPP_FUNCTION(M1_lt_rdynR, M1_LR_LXFR_lc[1]);


--M1L84 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|$00190~10
--operation mode is normal

M1L84 = AMPP_FUNCTION(M1_LR_LXFR, M1_LR_LXFR_lc[2], M1_LR_LXFR_lc[1], M1_TS_DISC, M1L232);

--M1L94 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|$00190~11
--operation mode is normal

M1L94 = AMPP_FUNCTION(M1_LR_LXFR, M1_LR_LXFR_lc[2], M1_LR_LXFR_lc[1], M1_TS_DISC, M1L232);


--J1L75 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|$00206~0
--operation mode is normal

J1L75 = AMPP_FUNCTION(J1_no_op_reg[1], A1L7421, J1_no_op_reg[3]);

--J1L85 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|$00206~10
--operation mode is normal

J1L85 = AMPP_FUNCTION(J1_no_op_reg[1], A1L7421, J1_no_op_reg[3]);

--J1L95 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|$00206~11
--operation mode is normal

J1L95 = AMPP_FUNCTION(J1_no_op_reg[1], A1L7421, J1_no_op_reg[3]);


--J1L45 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|$00205~0
--operation mode is normal

J1L45 = AMPP_FUNCTION(J1_no_op_reg[3], A1L8221);

--J1L55 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|$00205~10
--operation mode is normal

J1L55 = AMPP_FUNCTION(J1_no_op_reg[3], A1L8221);

--J1L65 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|$00205~11
--operation mode is normal

J1L65 = AMPP_FUNCTION(J1_no_op_reg[3], A1L8221);


--J1L15 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|$00202~0
--operation mode is normal

J1L15 = AMPP_FUNCTION(J1_no_op_reg[1], J1_no_op_reg[2], A1L7421);

--J1L25 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|$00202~10
--operation mode is normal

J1L25 = AMPP_FUNCTION(J1_no_op_reg[1], J1_no_op_reg[2], A1L7421);

--J1L35 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|$00202~11
--operation mode is normal

J1L35 = AMPP_FUNCTION(J1_no_op_reg[1], J1_no_op_reg[2], A1L7421);


--M1L76 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|_~246
--operation mode is normal

M1L76 = AMPP_FUNCTION(M1_TS_ADR_VLD, K1_serr_or, M1_cfg_cyc);

--M1L611 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|_~1525
--operation mode is normal

M1L611 = AMPP_FUNCTION(M1_TS_ADR_VLD, K1_serr_or, M1_cfg_cyc);

--M1L711 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|_~1526
--operation mode is normal

M1L711 = AMPP_FUNCTION(M1_TS_ADR_VLD, K1_serr_or, M1_cfg_cyc);


--dpm_ni2f_fifo_l_result_dec_80_ix35_carry_sum is dpm_ni2f_fifo_l_result_dec_80_ix35_carry_sum
--operation mode is arithmetic

dpm_ni2f_fifo_l_result_dec_80_ix35_carry_sum = dpm_ni2f_fifo_l_reg_nwords_2 $ (!A1L432);

--A1L632 is dpm_ni2f_fifo_l_result_dec_80_ix35_carry_sum~12
--operation mode is arithmetic

A1L632 = dpm_ni2f_fifo_l_reg_nwords_2 $ (!A1L432);

--A1L732 is dpm_ni2f_fifo_l_result_dec_80_ix35_carry_sum~COUT
--operation mode is arithmetic

A1L732 = CARRY(dpm_ni2f_fifo_l_reg_nwords_2 # A1L432);


--ix2370 is ix2370
--operation mode is normal

ix2370 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_l_reg_fifo_full # !dpm_ni2f_fifo_l_result_dec_80_ix35_carry_sum # !dpm_ni2f_reg_rdreq_fifo;

--A1L519 is ix2370~1
--operation mode is normal

A1L519 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_l_reg_fifo_full # !dpm_ni2f_fifo_l_result_dec_80_ix35_carry_sum # !dpm_ni2f_reg_rdreq_fifo;

--A1L619 is ix2370~2
--operation mode is normal

A1L619 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_l_reg_fifo_full # !dpm_ni2f_fifo_l_result_dec_80_ix35_carry_sum # !dpm_ni2f_reg_rdreq_fifo;


--dpm_ni2f_fifo_l_result_inc_82_ix35_carry_sum is dpm_ni2f_fifo_l_result_inc_82_ix35_carry_sum
--operation mode is arithmetic

dpm_ni2f_fifo_l_result_inc_82_ix35_carry_sum = dpm_ni2f_fifo_l_reg_nwords_2 $ (A1L072);

--A1L272 is dpm_ni2f_fifo_l_result_inc_82_ix35_carry_sum~12
--operation mode is arithmetic

A1L272 = dpm_ni2f_fifo_l_reg_nwords_2 $ (A1L072);

--A1L372 is dpm_ni2f_fifo_l_result_inc_82_ix35_carry_sum~COUT
--operation mode is arithmetic

A1L372 = CARRY(dpm_ni2f_fifo_l_reg_nwords_2 & (A1L072));


--A1L276 is ix2281~0
--operation mode is normal

A1L276 = (!ix2318_lc # !dpm_ni2f_fifo_l_result_inc_82_ix35_carry_sum) & CASCADE(A1L619);

--A1L376 is ix2281~1
--operation mode is normal

A1L376 = (!ix2318_lc # !dpm_ni2f_fifo_l_result_inc_82_ix35_carry_sum) & CASCADE(A1L619);


--dpm_ni2f_fifo_l_result_dec_80_ix31_carry_sum is dpm_ni2f_fifo_l_result_dec_80_ix31_carry_sum
--operation mode is arithmetic

dpm_ni2f_fifo_l_result_dec_80_ix31_carry_sum = dpm_ni2f_fifo_l_reg_nwords_1 $ (!A1L132);

--A1L332 is dpm_ni2f_fifo_l_result_dec_80_ix31_carry_sum~12
--operation mode is arithmetic

A1L332 = dpm_ni2f_fifo_l_reg_nwords_1 $ (!A1L132);

--A1L432 is dpm_ni2f_fifo_l_result_dec_80_ix31_carry_sum~COUT
--operation mode is arithmetic

A1L432 = CARRY(dpm_ni2f_fifo_l_reg_nwords_1 # A1L132);


--ix2369 is ix2369
--operation mode is normal

ix2369 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_l_reg_fifo_full # !dpm_ni2f_fifo_l_result_dec_80_ix31_carry_sum # !dpm_ni2f_reg_rdreq_fifo;

--A1L219 is ix2369~1
--operation mode is normal

A1L219 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_l_reg_fifo_full # !dpm_ni2f_fifo_l_result_dec_80_ix31_carry_sum # !dpm_ni2f_reg_rdreq_fifo;

--A1L319 is ix2369~2
--operation mode is normal

A1L319 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_l_reg_fifo_full # !dpm_ni2f_fifo_l_result_dec_80_ix31_carry_sum # !dpm_ni2f_reg_rdreq_fifo;


--dpm_ni2f_fifo_l_result_inc_82_ix31_carry_sum is dpm_ni2f_fifo_l_result_inc_82_ix31_carry_sum
--operation mode is arithmetic

dpm_ni2f_fifo_l_result_inc_82_ix31_carry_sum = dpm_ni2f_fifo_l_reg_nwords_1 $ (A1L762);

--A1L962 is dpm_ni2f_fifo_l_result_inc_82_ix31_carry_sum~12
--operation mode is arithmetic

A1L962 = dpm_ni2f_fifo_l_reg_nwords_1 $ (A1L762);

--A1L072 is dpm_ni2f_fifo_l_result_inc_82_ix31_carry_sum~COUT
--operation mode is arithmetic

A1L072 = CARRY(dpm_ni2f_fifo_l_reg_nwords_1 & (A1L762));


--A1L476 is ix2282~0
--operation mode is normal

A1L476 = (!ix2318_lc # !dpm_ni2f_fifo_l_result_inc_82_ix31_carry_sum) & CASCADE(A1L319);

--A1L576 is ix2282~1
--operation mode is normal

A1L576 = (!ix2318_lc # !dpm_ni2f_fifo_l_result_inc_82_ix31_carry_sum) & CASCADE(A1L319);


--ix2368 is ix2368
--operation mode is normal

ix2368 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_l_reg_fifo_full # !dpm_ni2f_fifo_l_result_dec_80_ix27_lc # !dpm_ni2f_reg_rdreq_fifo;

--A1L909 is ix2368~1
--operation mode is normal

A1L909 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_l_reg_fifo_full # !dpm_ni2f_fifo_l_result_dec_80_ix27_lc # !dpm_ni2f_reg_rdreq_fifo;

--A1L019 is ix2368~2
--operation mode is normal

A1L019 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_l_reg_fifo_full # !dpm_ni2f_fifo_l_result_dec_80_ix27_lc # !dpm_ni2f_reg_rdreq_fifo;


--A1L676 is ix2283~0
--operation mode is normal

A1L676 = (!ix2318_lc # !dpm_ni2f_fifo_l_result_inc_82_ix27_lc) & CASCADE(A1L019);

--A1L776 is ix2283~1
--operation mode is normal

A1L776 = (!ix2318_lc # !dpm_ni2f_fifo_l_result_inc_82_ix27_lc) & CASCADE(A1L019);


--E1_counter_cell[4] is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[4]
--operation mode is up_dn_cntr

E1_counter_cell[4]_lut_out = E1_counter_cell[4] $ E1L31;
E1_counter_cell[4] = DFFEA(E1_counter_cell[4]_lut_out, GLOBAL(pci_clk), , , , , );

--E1L51Q is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[4]~10
--operation mode is up_dn_cntr

E1L51Q = E1_counter_cell[4];

--E1L61 is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[4]~COUT
--operation mode is up_dn_cntr

E1L61 = CARRY(E1_counter_cell[4] & (E1L31));


--M1_LR_LXFR_lc[4] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_LXFR_lc[4]
--operation mode is normal

M1_LR_LXFR_lc[4] = AMPP_FUNCTION(M1_LR_PXFR, M1_lt_rdynR, M1_TS_DISC);

--M1L122 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_LXFR_lc[4]~64
--operation mode is normal

M1L122 = AMPP_FUNCTION(M1_LR_PXFR, M1_lt_rdynR, M1_TS_DISC);


--J1L755 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_WAIT_lc[1]~21
--operation mode is normal

J1L755 = AMPP_FUNCTION(J1_last_xfr, J1_lm_rdynR, J1_devsel_toR, J1L854);

--J1L855 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_WAIT_lc[1]~22
--operation mode is normal

J1L855 = AMPP_FUNCTION(J1_last_xfr, J1_lm_rdynR, J1_devsel_toR, J1L854);


--ix2378 is ix2378
--operation mode is normal

ix2378 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_l_reg_fifo_full # !dpm_ni2f_fifo_l_result_dec_80_ix67_lc # !dpm_ni2f_reg_rdreq_fifo;

--A1L939 is ix2378~1
--operation mode is normal

A1L939 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_l_reg_fifo_full # !dpm_ni2f_fifo_l_result_dec_80_ix67_lc # !dpm_ni2f_reg_rdreq_fifo;

--A1L049 is ix2378~2
--operation mode is normal

A1L049 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_l_reg_fifo_full # !dpm_ni2f_fifo_l_result_dec_80_ix67_lc # !dpm_ni2f_reg_rdreq_fifo;


--A1L656 is ix2273~0
--operation mode is normal

A1L656 = (!ix2318_lc # !dpm_ni2f_fifo_l_result_inc_82_ix67_lc) & CASCADE(A1L049);

--A1L756 is ix2273~1
--operation mode is normal

A1L756 = (!ix2318_lc # !dpm_ni2f_fifo_l_result_inc_82_ix67_lc) & CASCADE(A1L049);


--dpm_ni2f_fifo_l_result_dec_80_ix63_carry_sum is dpm_ni2f_fifo_l_result_dec_80_ix63_carry_sum
--operation mode is arithmetic

dpm_ni2f_fifo_l_result_dec_80_ix63_carry_sum = dpm_ni2f_fifo_l_reg_nwords_9 $ (!A1L552);

--A1L752 is dpm_ni2f_fifo_l_result_dec_80_ix63_carry_sum~12
--operation mode is arithmetic

A1L752 = dpm_ni2f_fifo_l_reg_nwords_9 $ (!A1L552);

--A1L852 is dpm_ni2f_fifo_l_result_dec_80_ix63_carry_sum~COUT
--operation mode is arithmetic

A1L852 = CARRY(dpm_ni2f_fifo_l_reg_nwords_9 # A1L552);


--ix2377 is ix2377
--operation mode is normal

ix2377 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_l_reg_fifo_full # !dpm_ni2f_fifo_l_result_dec_80_ix63_carry_sum # !dpm_ni2f_reg_rdreq_fifo;

--A1L639 is ix2377~1
--operation mode is normal

A1L639 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_l_reg_fifo_full # !dpm_ni2f_fifo_l_result_dec_80_ix63_carry_sum # !dpm_ni2f_reg_rdreq_fifo;

--A1L739 is ix2377~2
--operation mode is normal

A1L739 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_l_reg_fifo_full # !dpm_ni2f_fifo_l_result_dec_80_ix63_carry_sum # !dpm_ni2f_reg_rdreq_fifo;


--dpm_ni2f_fifo_l_result_inc_82_ix63_carry_sum is dpm_ni2f_fifo_l_result_inc_82_ix63_carry_sum
--operation mode is arithmetic

dpm_ni2f_fifo_l_result_inc_82_ix63_carry_sum = dpm_ni2f_fifo_l_reg_nwords_9 $ (A1L192);

--A1L392 is dpm_ni2f_fifo_l_result_inc_82_ix63_carry_sum~12
--operation mode is arithmetic

A1L392 = dpm_ni2f_fifo_l_reg_nwords_9 $ (A1L192);

--A1L492 is dpm_ni2f_fifo_l_result_inc_82_ix63_carry_sum~COUT
--operation mode is arithmetic

A1L492 = CARRY(dpm_ni2f_fifo_l_reg_nwords_9 & (A1L192));


--A1L856 is ix2274~0
--operation mode is normal

A1L856 = (!ix2318_lc # !dpm_ni2f_fifo_l_result_inc_82_ix63_carry_sum) & CASCADE(A1L739);

--A1L956 is ix2274~1
--operation mode is normal

A1L956 = (!ix2318_lc # !dpm_ni2f_fifo_l_result_inc_82_ix63_carry_sum) & CASCADE(A1L739);


--dpm_ni2f_fifo_l_result_dec_80_ix59_carry_sum is dpm_ni2f_fifo_l_result_dec_80_ix59_carry_sum
--operation mode is arithmetic

dpm_ni2f_fifo_l_result_dec_80_ix59_carry_sum = dpm_ni2f_fifo_l_reg_nwords_8 $ (!A1L252);

--A1L452 is dpm_ni2f_fifo_l_result_dec_80_ix59_carry_sum~12
--operation mode is arithmetic

A1L452 = dpm_ni2f_fifo_l_reg_nwords_8 $ (!A1L252);

--A1L552 is dpm_ni2f_fifo_l_result_dec_80_ix59_carry_sum~COUT
--operation mode is arithmetic

A1L552 = CARRY(dpm_ni2f_fifo_l_reg_nwords_8 # A1L252);


--ix2376 is ix2376
--operation mode is normal

ix2376 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_l_reg_fifo_full # !dpm_ni2f_fifo_l_result_dec_80_ix59_carry_sum # !dpm_ni2f_reg_rdreq_fifo;

--A1L339 is ix2376~1
--operation mode is normal

A1L339 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_l_reg_fifo_full # !dpm_ni2f_fifo_l_result_dec_80_ix59_carry_sum # !dpm_ni2f_reg_rdreq_fifo;

--A1L439 is ix2376~2
--operation mode is normal

A1L439 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_l_reg_fifo_full # !dpm_ni2f_fifo_l_result_dec_80_ix59_carry_sum # !dpm_ni2f_reg_rdreq_fifo;


--dpm_ni2f_fifo_l_result_inc_82_ix59_carry_sum is dpm_ni2f_fifo_l_result_inc_82_ix59_carry_sum
--operation mode is arithmetic

dpm_ni2f_fifo_l_result_inc_82_ix59_carry_sum = dpm_ni2f_fifo_l_reg_nwords_8 $ (A1L882);

--A1L092 is dpm_ni2f_fifo_l_result_inc_82_ix59_carry_sum~12
--operation mode is arithmetic

A1L092 = dpm_ni2f_fifo_l_reg_nwords_8 $ (A1L882);

--A1L192 is dpm_ni2f_fifo_l_result_inc_82_ix59_carry_sum~COUT
--operation mode is arithmetic

A1L192 = CARRY(dpm_ni2f_fifo_l_reg_nwords_8 & (A1L882));


--A1L066 is ix2275~0
--operation mode is normal

A1L066 = (!ix2318_lc # !dpm_ni2f_fifo_l_result_inc_82_ix59_carry_sum) & CASCADE(A1L439);

--A1L166 is ix2275~1
--operation mode is normal

A1L166 = (!ix2318_lc # !dpm_ni2f_fifo_l_result_inc_82_ix59_carry_sum) & CASCADE(A1L439);


--dpm_ni2f_fifo_l_result_dec_80_ix55_carry_sum is dpm_ni2f_fifo_l_result_dec_80_ix55_carry_sum
--operation mode is arithmetic

dpm_ni2f_fifo_l_result_dec_80_ix55_carry_sum = dpm_ni2f_fifo_l_reg_nwords_7 $ (!A1L942);

--A1L152 is dpm_ni2f_fifo_l_result_dec_80_ix55_carry_sum~12
--operation mode is arithmetic

A1L152 = dpm_ni2f_fifo_l_reg_nwords_7 $ (!A1L942);

--A1L252 is dpm_ni2f_fifo_l_result_dec_80_ix55_carry_sum~COUT
--operation mode is arithmetic

A1L252 = CARRY(dpm_ni2f_fifo_l_reg_nwords_7 # A1L942);


--ix2375 is ix2375
--operation mode is normal

ix2375 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_l_reg_fifo_full # !dpm_ni2f_fifo_l_result_dec_80_ix55_carry_sum # !dpm_ni2f_reg_rdreq_fifo;

--A1L039 is ix2375~1
--operation mode is normal

A1L039 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_l_reg_fifo_full # !dpm_ni2f_fifo_l_result_dec_80_ix55_carry_sum # !dpm_ni2f_reg_rdreq_fifo;

--A1L139 is ix2375~2
--operation mode is normal

A1L139 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_l_reg_fifo_full # !dpm_ni2f_fifo_l_result_dec_80_ix55_carry_sum # !dpm_ni2f_reg_rdreq_fifo;


--dpm_ni2f_fifo_l_result_inc_82_ix55_carry_sum is dpm_ni2f_fifo_l_result_inc_82_ix55_carry_sum
--operation mode is arithmetic

dpm_ni2f_fifo_l_result_inc_82_ix55_carry_sum = dpm_ni2f_fifo_l_reg_nwords_7 $ (A1L582);

--A1L782 is dpm_ni2f_fifo_l_result_inc_82_ix55_carry_sum~12
--operation mode is arithmetic

A1L782 = dpm_ni2f_fifo_l_reg_nwords_7 $ (A1L582);

--A1L882 is dpm_ni2f_fifo_l_result_inc_82_ix55_carry_sum~COUT
--operation mode is arithmetic

A1L882 = CARRY(dpm_ni2f_fifo_l_reg_nwords_7 & (A1L582));


--A1L266 is ix2276~0
--operation mode is normal

A1L266 = (!ix2318_lc # !dpm_ni2f_fifo_l_result_inc_82_ix55_carry_sum) & CASCADE(A1L139);

--A1L366 is ix2276~1
--operation mode is normal

A1L366 = (!ix2318_lc # !dpm_ni2f_fifo_l_result_inc_82_ix55_carry_sum) & CASCADE(A1L139);


--dpm_ni2f_fifo_l_result_dec_80_ix51_carry_sum is dpm_ni2f_fifo_l_result_dec_80_ix51_carry_sum
--operation mode is arithmetic

dpm_ni2f_fifo_l_result_dec_80_ix51_carry_sum = dpm_ni2f_fifo_l_reg_nwords_6 $ (!A1L642);

--A1L842 is dpm_ni2f_fifo_l_result_dec_80_ix51_carry_sum~12
--operation mode is arithmetic

A1L842 = dpm_ni2f_fifo_l_reg_nwords_6 $ (!A1L642);

--A1L942 is dpm_ni2f_fifo_l_result_dec_80_ix51_carry_sum~COUT
--operation mode is arithmetic

A1L942 = CARRY(dpm_ni2f_fifo_l_reg_nwords_6 # A1L642);


--ix2374 is ix2374
--operation mode is normal

ix2374 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_l_reg_fifo_full # !dpm_ni2f_fifo_l_result_dec_80_ix51_carry_sum # !dpm_ni2f_reg_rdreq_fifo;

--A1L729 is ix2374~1
--operation mode is normal

A1L729 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_l_reg_fifo_full # !dpm_ni2f_fifo_l_result_dec_80_ix51_carry_sum # !dpm_ni2f_reg_rdreq_fifo;

--A1L829 is ix2374~2
--operation mode is normal

A1L829 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_l_reg_fifo_full # !dpm_ni2f_fifo_l_result_dec_80_ix51_carry_sum # !dpm_ni2f_reg_rdreq_fifo;


--dpm_ni2f_fifo_l_result_inc_82_ix51_carry_sum is dpm_ni2f_fifo_l_result_inc_82_ix51_carry_sum
--operation mode is arithmetic

dpm_ni2f_fifo_l_result_inc_82_ix51_carry_sum = dpm_ni2f_fifo_l_reg_nwords_6 $ (A1L282);

--A1L482 is dpm_ni2f_fifo_l_result_inc_82_ix51_carry_sum~12
--operation mode is arithmetic

A1L482 = dpm_ni2f_fifo_l_reg_nwords_6 $ (A1L282);

--A1L582 is dpm_ni2f_fifo_l_result_inc_82_ix51_carry_sum~COUT
--operation mode is arithmetic

A1L582 = CARRY(dpm_ni2f_fifo_l_reg_nwords_6 & (A1L282));


--A1L466 is ix2277~0
--operation mode is normal

A1L466 = (!ix2318_lc # !dpm_ni2f_fifo_l_result_inc_82_ix51_carry_sum) & CASCADE(A1L829);

--A1L566 is ix2277~1
--operation mode is normal

A1L566 = (!ix2318_lc # !dpm_ni2f_fifo_l_result_inc_82_ix51_carry_sum) & CASCADE(A1L829);


--dpm_ni2f_fifo_l_result_dec_80_ix47_carry_sum is dpm_ni2f_fifo_l_result_dec_80_ix47_carry_sum
--operation mode is arithmetic

dpm_ni2f_fifo_l_result_dec_80_ix47_carry_sum = dpm_ni2f_fifo_l_reg_nwords_5 $ (!A1L342);

--A1L542 is dpm_ni2f_fifo_l_result_dec_80_ix47_carry_sum~12
--operation mode is arithmetic

A1L542 = dpm_ni2f_fifo_l_reg_nwords_5 $ (!A1L342);

--A1L642 is dpm_ni2f_fifo_l_result_dec_80_ix47_carry_sum~COUT
--operation mode is arithmetic

A1L642 = CARRY(dpm_ni2f_fifo_l_reg_nwords_5 # A1L342);


--ix2373 is ix2373
--operation mode is normal

ix2373 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_l_reg_fifo_full # !dpm_ni2f_fifo_l_result_dec_80_ix47_carry_sum # !dpm_ni2f_reg_rdreq_fifo;

--A1L429 is ix2373~1
--operation mode is normal

A1L429 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_l_reg_fifo_full # !dpm_ni2f_fifo_l_result_dec_80_ix47_carry_sum # !dpm_ni2f_reg_rdreq_fifo;

--A1L529 is ix2373~2
--operation mode is normal

A1L529 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_l_reg_fifo_full # !dpm_ni2f_fifo_l_result_dec_80_ix47_carry_sum # !dpm_ni2f_reg_rdreq_fifo;


--dpm_ni2f_fifo_l_result_inc_82_ix47_carry_sum is dpm_ni2f_fifo_l_result_inc_82_ix47_carry_sum
--operation mode is arithmetic

dpm_ni2f_fifo_l_result_inc_82_ix47_carry_sum = dpm_ni2f_fifo_l_reg_nwords_5 $ (A1L972);

--A1L182 is dpm_ni2f_fifo_l_result_inc_82_ix47_carry_sum~12
--operation mode is arithmetic

A1L182 = dpm_ni2f_fifo_l_reg_nwords_5 $ (A1L972);

--A1L282 is dpm_ni2f_fifo_l_result_inc_82_ix47_carry_sum~COUT
--operation mode is arithmetic

A1L282 = CARRY(dpm_ni2f_fifo_l_reg_nwords_5 & (A1L972));


--A1L666 is ix2278~0
--operation mode is normal

A1L666 = (!ix2318_lc # !dpm_ni2f_fifo_l_result_inc_82_ix47_carry_sum) & CASCADE(A1L529);

--A1L766 is ix2278~1
--operation mode is normal

A1L766 = (!ix2318_lc # !dpm_ni2f_fifo_l_result_inc_82_ix47_carry_sum) & CASCADE(A1L529);


--dpm_ni2f_fifo_l_result_dec_80_ix43_carry_sum is dpm_ni2f_fifo_l_result_dec_80_ix43_carry_sum
--operation mode is arithmetic

dpm_ni2f_fifo_l_result_dec_80_ix43_carry_sum = dpm_ni2f_fifo_l_reg_nwords_4 $ (!A1L042);

--A1L242 is dpm_ni2f_fifo_l_result_dec_80_ix43_carry_sum~12
--operation mode is arithmetic

A1L242 = dpm_ni2f_fifo_l_reg_nwords_4 $ (!A1L042);

--A1L342 is dpm_ni2f_fifo_l_result_dec_80_ix43_carry_sum~COUT
--operation mode is arithmetic

A1L342 = CARRY(dpm_ni2f_fifo_l_reg_nwords_4 # A1L042);


--ix2372 is ix2372
--operation mode is normal

ix2372 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_l_reg_fifo_full # !dpm_ni2f_fifo_l_result_dec_80_ix43_carry_sum # !dpm_ni2f_reg_rdreq_fifo;

--A1L129 is ix2372~1
--operation mode is normal

A1L129 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_l_reg_fifo_full # !dpm_ni2f_fifo_l_result_dec_80_ix43_carry_sum # !dpm_ni2f_reg_rdreq_fifo;

--A1L229 is ix2372~2
--operation mode is normal

A1L229 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_l_reg_fifo_full # !dpm_ni2f_fifo_l_result_dec_80_ix43_carry_sum # !dpm_ni2f_reg_rdreq_fifo;


--dpm_ni2f_fifo_l_result_inc_82_ix43_carry_sum is dpm_ni2f_fifo_l_result_inc_82_ix43_carry_sum
--operation mode is arithmetic

dpm_ni2f_fifo_l_result_inc_82_ix43_carry_sum = dpm_ni2f_fifo_l_reg_nwords_4 $ (A1L672);

--A1L872 is dpm_ni2f_fifo_l_result_inc_82_ix43_carry_sum~12
--operation mode is arithmetic

A1L872 = dpm_ni2f_fifo_l_reg_nwords_4 $ (A1L672);

--A1L972 is dpm_ni2f_fifo_l_result_inc_82_ix43_carry_sum~COUT
--operation mode is arithmetic

A1L972 = CARRY(dpm_ni2f_fifo_l_reg_nwords_4 & (A1L672));


--A1L866 is ix2279~0
--operation mode is normal

A1L866 = (!ix2318_lc # !dpm_ni2f_fifo_l_result_inc_82_ix43_carry_sum) & CASCADE(A1L229);

--A1L966 is ix2279~1
--operation mode is normal

A1L966 = (!ix2318_lc # !dpm_ni2f_fifo_l_result_inc_82_ix43_carry_sum) & CASCADE(A1L229);


--dpm_ni2f_fifo_l_result_dec_80_ix39_carry_sum is dpm_ni2f_fifo_l_result_dec_80_ix39_carry_sum
--operation mode is arithmetic

dpm_ni2f_fifo_l_result_dec_80_ix39_carry_sum = dpm_ni2f_fifo_l_reg_nwords_3 $ (!A1L732);

--A1L932 is dpm_ni2f_fifo_l_result_dec_80_ix39_carry_sum~12
--operation mode is arithmetic

A1L932 = dpm_ni2f_fifo_l_reg_nwords_3 $ (!A1L732);

--A1L042 is dpm_ni2f_fifo_l_result_dec_80_ix39_carry_sum~COUT
--operation mode is arithmetic

A1L042 = CARRY(dpm_ni2f_fifo_l_reg_nwords_3 # A1L732);


--ix2371 is ix2371
--operation mode is normal

ix2371 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_l_reg_fifo_full # !dpm_ni2f_fifo_l_result_dec_80_ix39_carry_sum # !dpm_ni2f_reg_rdreq_fifo;

--A1L819 is ix2371~1
--operation mode is normal

A1L819 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_l_reg_fifo_full # !dpm_ni2f_fifo_l_result_dec_80_ix39_carry_sum # !dpm_ni2f_reg_rdreq_fifo;

--A1L919 is ix2371~2
--operation mode is normal

A1L919 = dpm_ni2f_reg_des_valid_data & !dpm_ni2f_fifo_l_reg_fifo_full # !dpm_ni2f_fifo_l_result_dec_80_ix39_carry_sum # !dpm_ni2f_reg_rdreq_fifo;


--dpm_ni2f_fifo_l_result_inc_82_ix39_carry_sum is dpm_ni2f_fifo_l_result_inc_82_ix39_carry_sum
--operation mode is arithmetic

dpm_ni2f_fifo_l_result_inc_82_ix39_carry_sum = dpm_ni2f_fifo_l_reg_nwords_3 $ (A1L372);

--A1L572 is dpm_ni2f_fifo_l_result_inc_82_ix39_carry_sum~12
--operation mode is arithmetic

A1L572 = dpm_ni2f_fifo_l_reg_nwords_3 $ (A1L372);

--A1L672 is dpm_ni2f_fifo_l_result_inc_82_ix39_carry_sum~COUT
--operation mode is arithmetic

A1L672 = CARRY(dpm_ni2f_fifo_l_reg_nwords_3 & (A1L372));


--A1L076 is ix2280~0
--operation mode is normal

A1L076 = (!ix2318_lc # !dpm_ni2f_fifo_l_result_inc_82_ix39_carry_sum) & CASCADE(A1L919);

--A1L176 is ix2280~1
--operation mode is normal

A1L176 = (!ix2318_lc # !dpm_ni2f_fifo_l_result_inc_82_ix39_carry_sum) & CASCADE(A1L919);


--ix2318_lc is ix2318_lc
--operation mode is normal

ix2318_lc = dpm_ni2f_reg_des_valid_data & (!dpm_ni2f_fifo_l_reg_fifo_full # !dpm_ni2f_reg_rdreq_fifo);

--A1L477 is ix2318_lc~0
--operation mode is normal

A1L477 = dpm_ni2f_reg_des_valid_data & (!dpm_ni2f_fifo_l_reg_fifo_full # !dpm_ni2f_reg_rdreq_fifo);


--E1_counter_cell[3] is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[3]
--operation mode is up_dn_cntr

E1_counter_cell[3]_lut_out = E1_counter_cell[3] $ E1L01;
E1_counter_cell[3] = DFFEA(E1_counter_cell[3]_lut_out, GLOBAL(pci_clk), , , , , );

--E1L21Q is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[3]~11
--operation mode is up_dn_cntr

E1L21Q = E1_counter_cell[3];

--E1L31 is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT
--operation mode is up_dn_cntr

E1L31 = CARRY(E1_counter_cell[3] & (E1L01));


--dpm_ni2f_fifo_l_result_dec_80_ix67_lc is dpm_ni2f_fifo_l_result_dec_80_ix67_lc
--operation mode is normal

dpm_ni2f_fifo_l_result_dec_80_ix67_lc = dpm_ni2f_fifo_l_reg_nwords_10 $ !A1L852;

--A1L162 is dpm_ni2f_fifo_l_result_dec_80_ix67_lc~0
--operation mode is normal

A1L162 = dpm_ni2f_fifo_l_reg_nwords_10 $ !A1L852;


--dpm_ni2f_fifo_l_result_inc_82_ix67_lc is dpm_ni2f_fifo_l_result_inc_82_ix67_lc
--operation mode is normal

dpm_ni2f_fifo_l_result_inc_82_ix67_lc = dpm_ni2f_fifo_l_reg_nwords_10 $ A1L492;

--A1L792 is dpm_ni2f_fifo_l_result_inc_82_ix67_lc~0
--operation mode is normal

A1L792 = dpm_ni2f_fifo_l_reg_nwords_10 $ A1L492;


--dpm_ni2f_fifo_l_result_dec_80_ix29_carry_sum is dpm_ni2f_fifo_l_result_dec_80_ix29_carry_sum
--operation mode is arithmetic

dpm_ni2f_fifo_l_result_dec_80_ix29_carry_sum = VCC;

--A1L032 is dpm_ni2f_fifo_l_result_dec_80_ix29_carry_sum~7
--operation mode is arithmetic

A1L032 = VCC;

--A1L132 is dpm_ni2f_fifo_l_result_dec_80_ix29_carry_sum~COUT
--operation mode is arithmetic

A1L132 = CARRY(dpm_ni2f_fifo_l_reg_nwords_0);


--dpm_ni2f_fifo_l_result_inc_82_ix29_carry_sum is dpm_ni2f_fifo_l_result_inc_82_ix29_carry_sum
--operation mode is arithmetic

dpm_ni2f_fifo_l_result_inc_82_ix29_carry_sum = VCC;

--A1L662 is dpm_ni2f_fifo_l_result_inc_82_ix29_carry_sum~7
--operation mode is arithmetic

A1L662 = VCC;

--A1L762 is dpm_ni2f_fifo_l_result_inc_82_ix29_carry_sum~COUT
--operation mode is arithmetic

A1L762 = CARRY(dpm_ni2f_fifo_l_reg_nwords_0);


--E1_counter_cell[2] is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[2]
--operation mode is up_dn_cntr

E1_counter_cell[2]_lut_out = E1_counter_cell[2] $ E1L7;
E1_counter_cell[2] = DFFEA(E1_counter_cell[2]_lut_out, GLOBAL(pci_clk), , , , , );

--E1L9Q is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[2]~12
--operation mode is up_dn_cntr

E1L9Q = E1_counter_cell[2];

--E1L01 is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT
--operation mode is up_dn_cntr

E1L01 = CARRY(E1_counter_cell[2] & (E1L7));


--E11_q[0] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[0]
--operation mode is clrb_cntr

E11_q[0] = AMPP_FUNCTION(J1_latcntr_cnt_en, J1_$00064, ~GND, J1L273, pci_rstn, GLOBAL(pci_clk));

--E11L91Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[0]~0
--operation mode is clrb_cntr

E11L91Q = AMPP_FUNCTION(J1_latcntr_cnt_en, J1_$00064, ~GND, J1L273, pci_rstn, GLOBAL(pci_clk));

--E11L3 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT
--operation mode is clrb_cntr

E11L3 = AMPP_FUNCTION();


--E11_q[3] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[3]
--operation mode is clrb_cntr

E11_q[3] = AMPP_FUNCTION(J1_latcntr_cnt_en, J1_$00064, P1_lat_tmr_reg[0], J1L273, pci_rstn, GLOBAL(pci_clk), E11L7);

--E11L52Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[3]~1
--operation mode is clrb_cntr

E11L52Q = AMPP_FUNCTION(J1_latcntr_cnt_en, J1_$00064, P1_lat_tmr_reg[0], J1L273, pci_rstn, GLOBAL(pci_clk), E11L7);

--E11L9 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT
--operation mode is clrb_cntr

E11L9 = AMPP_FUNCTION(E11L7);


--E11_q[2] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[2]
--operation mode is clrb_cntr

E11_q[2] = AMPP_FUNCTION(J1_latcntr_cnt_en, J1_$00064, ~GND, J1L273, pci_rstn, GLOBAL(pci_clk), E11L5);

--E11L32Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[2]~2
--operation mode is clrb_cntr

E11L32Q = AMPP_FUNCTION(J1_latcntr_cnt_en, J1_$00064, ~GND, J1L273, pci_rstn, GLOBAL(pci_clk), E11L5);

--E11L7 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT
--operation mode is clrb_cntr

E11L7 = AMPP_FUNCTION(E11L5);


--E11_q[1] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[1]
--operation mode is clrb_cntr

E11_q[1] = AMPP_FUNCTION(J1_latcntr_cnt_en, J1_$00064, ~GND, J1L273, pci_rstn, GLOBAL(pci_clk), E11L3);

--E11L12Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[1]~3
--operation mode is clrb_cntr

E11L12Q = AMPP_FUNCTION(J1_latcntr_cnt_en, J1_$00064, ~GND, J1L273, pci_rstn, GLOBAL(pci_clk), E11L3);

--E11L5 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT
--operation mode is clrb_cntr

E11L5 = AMPP_FUNCTION(E11L3);


--J1L18 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|_~1127
--operation mode is normal

J1L18 = AMPP_FUNCTION(E11_q[0], E11_q[3], E11_q[2], E11_q[1]);

--J1L69 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|_~1150
--operation mode is normal

J1L69 = AMPP_FUNCTION(E11_q[0], E11_q[3], E11_q[2], E11_q[1]);

--J1L79 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|_~1151
--operation mode is normal

J1L79 = AMPP_FUNCTION(E11_q[0], E11_q[3], E11_q[2], E11_q[1]);


--E11_q[7] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[7]
--operation mode is clrb_cntr

E11_q[7] = AMPP_FUNCTION(J1_latcntr_cnt_en, J1_$00064, P1_lat_tmr_reg[4], J1L273, pci_rstn, GLOBAL(pci_clk), E11L51);

--E11L33Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[7]~4
--operation mode is clrb_cntr

E11L33Q = AMPP_FUNCTION(J1_latcntr_cnt_en, J1_$00064, P1_lat_tmr_reg[4], J1L273, pci_rstn, GLOBAL(pci_clk), E11L51);


--E11_q[6] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[6]
--operation mode is clrb_cntr

E11_q[6] = AMPP_FUNCTION(J1_latcntr_cnt_en, J1_$00064, P1_lat_tmr_reg[3], J1L273, pci_rstn, GLOBAL(pci_clk), E11L31);

--E11L13Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[6]~5
--operation mode is clrb_cntr

E11L13Q = AMPP_FUNCTION(J1_latcntr_cnt_en, J1_$00064, P1_lat_tmr_reg[3], J1L273, pci_rstn, GLOBAL(pci_clk), E11L31);

--E11L51 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|counter_cell[6]~COUT
--operation mode is clrb_cntr

E11L51 = AMPP_FUNCTION(E11L31);


--E11_q[5] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[5]
--operation mode is clrb_cntr

E11_q[5] = AMPP_FUNCTION(J1_latcntr_cnt_en, J1_$00064, P1_lat_tmr_reg[2], J1L273, pci_rstn, GLOBAL(pci_clk), E11L11);

--E11L92Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[5]~6
--operation mode is clrb_cntr

E11L92Q = AMPP_FUNCTION(J1_latcntr_cnt_en, J1_$00064, P1_lat_tmr_reg[2], J1L273, pci_rstn, GLOBAL(pci_clk), E11L11);

--E11L31 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|counter_cell[5]~COUT
--operation mode is clrb_cntr

E11L31 = AMPP_FUNCTION(E11L11);


--E11_q[4] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[4]
--operation mode is clrb_cntr

E11_q[4] = AMPP_FUNCTION(J1_latcntr_cnt_en, J1_$00064, P1_lat_tmr_reg[1], J1L273, pci_rstn, GLOBAL(pci_clk), E11L9);

--E11L72Q is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[4]~7
--operation mode is clrb_cntr

E11L72Q = AMPP_FUNCTION(J1_latcntr_cnt_en, J1_$00064, P1_lat_tmr_reg[1], J1L273, pci_rstn, GLOBAL(pci_clk), E11L9);

--E11L11 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|counter_cell[4]~COUT
--operation mode is clrb_cntr

E11L11 = AMPP_FUNCTION(E11L9);


--J1L58 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|_~1132
--operation mode is normal

J1L58 = AMPP_FUNCTION(E11_q[7], E11_q[6], E11_q[5], E11_q[4], J1L79);

--J1L89 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|_~1152
--operation mode is normal

J1L89 = AMPP_FUNCTION(E11_q[7], E11_q[6], E11_q[5], E11_q[4], J1L79);


--E1_counter_cell[1] is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[1]
--operation mode is up_dn_cntr

E1_counter_cell[1]_lut_out = E1_counter_cell[1] $ E1L4;
E1_counter_cell[1] = DFFEA(E1_counter_cell[1]_lut_out, GLOBAL(pci_clk), , , , , );

--E1L6Q is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[1]~13
--operation mode is up_dn_cntr

E1L6Q = E1_counter_cell[1];

--E1L7 is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT
--operation mode is up_dn_cntr

E1L7 = CARRY(E1_counter_cell[1] & (E1L4));


--E1_counter_cell[0] is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[0]
--operation mode is up_dn_cntr

E1_counter_cell[0]_lut_out = !E1_counter_cell[0];
E1_counter_cell[0] = DFFEA(E1_counter_cell[0]_lut_out, GLOBAL(pci_clk), , , , , );

--E1L3Q is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[0]~14
--operation mode is up_dn_cntr

E1L3Q = E1_counter_cell[0];

--E1L4 is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT
--operation mode is up_dn_cntr

E1L4 = CARRY(E1_counter_cell[0]);


--J1_latcntr_cnt_en is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|latcntr_cnt_en
--operation mode is normal

J1_latcntr_cnt_en = AMPP_FUNCTION(J1_MS_DXFR, J1L58);

--J1L362 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|latcntr_cnt_en~8
--operation mode is normal

J1L362 = AMPP_FUNCTION(J1_MS_DXFR, J1L58);


--J1_$00064 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|$00064
--operation mode is normal

J1_$00064 = AMPP_FUNCTION(J1_MS_TAR, J1_MS_REQ, J1_MS_IDLE_not);

--J1L3 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|$00064~15
--operation mode is normal

J1L3 = AMPP_FUNCTION(J1_MS_TAR, J1_MS_REQ, J1_MS_IDLE_not);


--lcst is lcst
--operation mode is normal

lcst = !DES_CLK;

--A1L7311 is lcst~1
--operation mode is normal

A1L7311 = !DES_CLK;


--G1_trg_serr_vld is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_serr_vld
--operation mode is normal

G1_trg_serr_vld = AMPP_FUNCTION(M1_adr_phase_lc1);

--G1L856 is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_serr_vld~1
--operation mode is normal

G1L856 = AMPP_FUNCTION(M1_adr_phase_lc1);


--G1_low_mstr_cbe_out_lc1[0] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_mstr_cbe_out_lc1[0]
--operation mode is normal

G1_low_mstr_cbe_out_lc1[0] = AMPP_FUNCTION();

--G1L605 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_mstr_cbe_out_lc1[0]~8
--operation mode is normal

G1L605 = AMPP_FUNCTION();


--G1_low_mstr_cbe_out_lc1[1] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_mstr_cbe_out_lc1[1]
--operation mode is normal

G1_low_mstr_cbe_out_lc1[1] = AMPP_FUNCTION();

--G1L905 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_mstr_cbe_out_lc1[1]~9
--operation mode is normal

G1L905 = AMPP_FUNCTION();


--G1_low_mstr_cbe_out_lc1[2] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_mstr_cbe_out_lc1[2]
--operation mode is normal

G1_low_mstr_cbe_out_lc1[2] = AMPP_FUNCTION();

--G1L215 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_mstr_cbe_out_lc1[2]~10
--operation mode is normal

G1L215 = AMPP_FUNCTION();


--G1_low_mstr_cbe_out_lc1[3] is pci_contr:pci|pci_mt32:pci_mt32_inst|low_mstr_cbe_out_lc1[3]
--operation mode is normal

G1_low_mstr_cbe_out_lc1[3] = AMPP_FUNCTION();

--G1L515 is pci_contr:pci|pci_mt32:pci_mt32_inst|low_mstr_cbe_out_lc1[3]~11
--operation mode is normal

G1L515 = AMPP_FUNCTION();


--P1_mbar_hit is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|mbar_hit
--operation mode is normal

P1_mbar_hit = AMPP_FUNCTION(P1_bar_hit[0]);

--P1L161 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|pcimt32_c:cfg|mbar_hit~7
--operation mode is normal

P1L161 = AMPP_FUNCTION(P1_bar_hit[0]);


--G1_trg_cben_IR_ce_A is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cben_IR_ce_A
--operation mode is normal

G1_trg_cben_IR_ce_A = AMPP_FUNCTION(M1_ad_ir_ce_A_lc1, M1_ad_ir_ce_A_lc2);

--G1L255 is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cben_IR_ce_A~7
--operation mode is normal

G1L255 = AMPP_FUNCTION(M1_ad_ir_ce_A_lc1, M1_ad_ir_ce_A_lc2);


--H1_ad_ce[1] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[1]
--operation mode is normal

H1_ad_ce[1] = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);

--H1L5 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[1]~65
--operation mode is normal

H1L5 = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);


--H1_ad_ce[2] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[2]
--operation mode is normal

H1_ad_ce[2] = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);

--H1L7 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[2]~66
--operation mode is normal

H1L7 = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);


--H1_ad_ce[3] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[3]
--operation mode is normal

H1_ad_ce[3] = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);

--H1L9 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[3]~67
--operation mode is normal

H1L9 = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);


--H1_ad_ce[4] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[4]
--operation mode is normal

H1_ad_ce[4] = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);

--H1L11 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[4]~68
--operation mode is normal

H1L11 = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);


--H1_ad_ce[5] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[5]
--operation mode is normal

H1_ad_ce[5] = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);

--H1L31 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[5]~69
--operation mode is normal

H1L31 = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);


--H1_ad_ce[6] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[6]
--operation mode is normal

H1_ad_ce[6] = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);

--H1L51 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[6]~70
--operation mode is normal

H1L51 = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);


--H1_ad_ce[7] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[7]
--operation mode is normal

H1_ad_ce[7] = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);

--H1L71 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[7]~71
--operation mode is normal

H1L71 = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);


--H1_ad_ce[8] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[8]
--operation mode is normal

H1_ad_ce[8] = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);

--H1L91 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[8]~72
--operation mode is normal

H1L91 = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);


--H1_ad_ce[9] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[9]
--operation mode is normal

H1_ad_ce[9] = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);

--H1L12 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[9]~73
--operation mode is normal

H1L12 = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);


--H1_ad_ce[10] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[10]
--operation mode is normal

H1_ad_ce[10] = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);

--H1L32 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[10]~74
--operation mode is normal

H1L32 = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);


--H1_ad_ce[11] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[11]
--operation mode is normal

H1_ad_ce[11] = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);

--H1L52 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[11]~75
--operation mode is normal

H1L52 = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);


--H1_ad_ce[12] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[12]
--operation mode is normal

H1_ad_ce[12] = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);

--H1L72 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[12]~76
--operation mode is normal

H1L72 = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);


--H1_ad_ce[13] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[13]
--operation mode is normal

H1_ad_ce[13] = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);

--H1L92 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[13]~77
--operation mode is normal

H1L92 = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);


--H1_ad_ce[14] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[14]
--operation mode is normal

H1_ad_ce[14] = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);

--H1L13 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[14]~78
--operation mode is normal

H1L13 = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);


--H1_ad_ce[15] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[15]
--operation mode is normal

H1_ad_ce[15] = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);

--H1L33 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[15]~79
--operation mode is normal

H1L33 = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);


--H1_ad_ce[16] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[16]
--operation mode is normal

H1_ad_ce[16] = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);

--H1L53 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[16]~80
--operation mode is normal

H1L53 = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);


--H1_ad_ce[17] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[17]
--operation mode is normal

H1_ad_ce[17] = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);

--H1L73 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[17]~81
--operation mode is normal

H1L73 = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);


--H1_ad_ce[18] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[18]
--operation mode is normal

H1_ad_ce[18] = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);

--H1L93 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[18]~82
--operation mode is normal

H1L93 = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);


--H1_ad_ce[19] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[19]
--operation mode is normal

H1_ad_ce[19] = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);

--H1L14 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[19]~83
--operation mode is normal

H1L14 = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);


--H1_ad_ce[20] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[20]
--operation mode is normal

H1_ad_ce[20] = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);

--H1L34 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[20]~84
--operation mode is normal

H1L34 = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);


--H1_ad_ce[21] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[21]
--operation mode is normal

H1_ad_ce[21] = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);

--H1L54 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[21]~85
--operation mode is normal

H1L54 = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);


--H1_ad_ce[22] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[22]
--operation mode is normal

H1_ad_ce[22] = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);

--H1L74 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[22]~86
--operation mode is normal

H1L74 = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);


--H1_ad_ce[23] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[23]
--operation mode is normal

H1_ad_ce[23] = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);

--H1L94 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[23]~87
--operation mode is normal

H1L94 = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);


--H1_ad_ce[24] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[24]
--operation mode is normal

H1_ad_ce[24] = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);

--H1L15 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[24]~88
--operation mode is normal

H1L15 = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);


--H1_ad_ce[25] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[25]
--operation mode is normal

H1_ad_ce[25] = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);

--H1L35 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[25]~89
--operation mode is normal

H1L35 = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);


--H1_ad_ce[26] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[26]
--operation mode is normal

H1_ad_ce[26] = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);

--H1L55 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[26]~90
--operation mode is normal

H1L55 = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);


--H1_ad_ce[27] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[27]
--operation mode is normal

H1_ad_ce[27] = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);

--H1L75 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[27]~91
--operation mode is normal

H1L75 = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);


--H1_ad_ce[28] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[28]
--operation mode is normal

H1_ad_ce[28] = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);

--H1L95 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[28]~92
--operation mode is normal

H1L95 = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);


--H1_ad_ce[29] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[29]
--operation mode is normal

H1_ad_ce[29] = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);

--H1L16 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[29]~93
--operation mode is normal

H1L16 = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);


--H1_ad_ce[30] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[30]
--operation mode is normal

H1_ad_ce[30] = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);

--H1L36 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[30]~94
--operation mode is normal

H1L36 = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);


--H1_ad_ce[31] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[31]
--operation mode is normal

H1_ad_ce[31] = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);

--H1L56 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_adce:adce|ad_ce[31]~95
--operation mode is normal

H1L56 = AMPP_FUNCTION(G1_ad_ce_nc, A1L5321, A1L7421);


--J1_cbe_oer_r1_lc1 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|cbe_oer_r1_lc1
--operation mode is normal

J1_cbe_oer_r1_lc1 = AMPP_FUNCTION(J1_idle_reg, J1_MS_REQ, J1_MS_IDLE_not);

--J1L331 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|cbe_oer_r1_lc1~2
--operation mode is normal

J1L331 = AMPP_FUNCTION(J1_idle_reg, J1_MS_REQ, J1_MS_IDLE_not);


--M1_devsel_OR_lc[3] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|devsel_OR_lc[3]
--operation mode is normal

M1_devsel_OR_lc[3] = AMPP_FUNCTION();

--M1L971 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|devsel_OR_lc[3]~12
--operation mode is normal

M1L971 = AMPP_FUNCTION();


--J1_irdy_or_lc[5] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|irdy_or_lc[5]
--operation mode is normal

J1_irdy_or_lc[5] = AMPP_FUNCTION(J1_MW_HOLD);

--J1L042 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|irdy_or_lc[5]~56
--operation mode is normal

J1L042 = AMPP_FUNCTION(J1_MW_HOLD);


--M1_stop_or_lc[6] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|stop_or_lc[6]
--operation mode is normal

M1_stop_or_lc[6] = AMPP_FUNCTION();

--M1L664 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|stop_or_lc[6]~52
--operation mode is normal

M1L664 = AMPP_FUNCTION();


--G1_trg_cben_IR_ce_D is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cben_IR_ce_D
--operation mode is normal

G1_trg_cben_IR_ce_D = AMPP_FUNCTION(M1_ad_ir_ce_D_lc1, M1_TS_TURN_AR, M1_cfg_cyc, J1_mstr_actv_lc);

--G1L455 is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cben_IR_ce_D~7
--operation mode is normal

G1L455 = AMPP_FUNCTION(M1_ad_ir_ce_D_lc1, M1_TS_TURN_AR, M1_cfg_cyc, J1_mstr_actv_lc);


--M1_lt_ack_R_r1_lc[8] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_ack_R_r1_lc[8]
--operation mode is normal

M1_lt_ack_R_r1_lc[8] = AMPP_FUNCTION(M1_lt_rdynR);

--M1L213 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_ack_R_r1_lc[8]~119
--operation mode is normal

M1L213 = AMPP_FUNCTION(M1_lt_rdynR);


--G1_trg_cfg_ad_out[0] is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[0]
--operation mode is normal

G1_trg_cfg_ad_out[0] = AMPP_FUNCTION(P1_ad_dat_out[0]);

--G1L855 is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[0]~32
--operation mode is normal

G1L855 = AMPP_FUNCTION(P1_ad_dat_out[0]);


--G1_trg_cfg_ad_out[1] is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[1]
--operation mode is normal

G1_trg_cfg_ad_out[1] = AMPP_FUNCTION(P1_ad_dat_out[1]);

--G1L165 is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[1]~33
--operation mode is normal

G1L165 = AMPP_FUNCTION(P1_ad_dat_out[1]);


--G1_trg_cfg_ad_out[2] is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[2]
--operation mode is normal

G1_trg_cfg_ad_out[2] = AMPP_FUNCTION(P1_ad_dat_out[2]);

--G1L465 is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[2]~34
--operation mode is normal

G1L465 = AMPP_FUNCTION(P1_ad_dat_out[2]);


--G1_trg_cfg_ad_out[3] is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[3]
--operation mode is normal

G1_trg_cfg_ad_out[3] = AMPP_FUNCTION(P1_ad_dat_out[3]);

--G1L765 is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[3]~35
--operation mode is normal

G1L765 = AMPP_FUNCTION(P1_ad_dat_out[3]);


--G1_trg_cfg_ad_out[4] is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[4]
--operation mode is normal

G1_trg_cfg_ad_out[4] = AMPP_FUNCTION(P1_ad_dat_out[4]);

--G1L075 is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[4]~36
--operation mode is normal

G1L075 = AMPP_FUNCTION(P1_ad_dat_out[4]);


--G1_trg_cfg_ad_out[5] is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[5]
--operation mode is normal

G1_trg_cfg_ad_out[5] = AMPP_FUNCTION(P1_ad_dat_out[5]);

--G1L375 is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[5]~37
--operation mode is normal

G1L375 = AMPP_FUNCTION(P1_ad_dat_out[5]);


--G1_trg_cfg_ad_out[6] is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[6]
--operation mode is normal

G1_trg_cfg_ad_out[6] = AMPP_FUNCTION(P1_ad_dat_out[6]);

--G1L675 is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[6]~38
--operation mode is normal

G1L675 = AMPP_FUNCTION(P1_ad_dat_out[6]);


--G1_trg_cfg_ad_out[7] is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[7]
--operation mode is normal

G1_trg_cfg_ad_out[7] = AMPP_FUNCTION(P1_ad_dat_out[7]);

--G1L975 is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[7]~39
--operation mode is normal

G1L975 = AMPP_FUNCTION(P1_ad_dat_out[7]);


--G1_trg_cfg_ad_out[8] is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[8]
--operation mode is normal

G1_trg_cfg_ad_out[8] = AMPP_FUNCTION(P1_ad_dat_out[8]);

--G1L285 is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[8]~40
--operation mode is normal

G1L285 = AMPP_FUNCTION(P1_ad_dat_out[8]);


--G1_trg_cfg_ad_out[9] is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[9]
--operation mode is normal

G1_trg_cfg_ad_out[9] = AMPP_FUNCTION();

--G1L585 is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[9]~41
--operation mode is normal

G1L585 = AMPP_FUNCTION();


--G1_trg_cfg_ad_out[10] is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[10]
--operation mode is normal

G1_trg_cfg_ad_out[10] = AMPP_FUNCTION();

--G1L885 is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[10]~42
--operation mode is normal

G1L885 = AMPP_FUNCTION();


--G1_trg_cfg_ad_out[11] is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[11]
--operation mode is normal

G1_trg_cfg_ad_out[11] = AMPP_FUNCTION(P1_ad_dat_out[11]);

--G1L195 is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[11]~43
--operation mode is normal

G1L195 = AMPP_FUNCTION(P1_ad_dat_out[11]);


--G1_trg_cfg_ad_out[12] is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[12]
--operation mode is normal

G1_trg_cfg_ad_out[12] = AMPP_FUNCTION(P1_ad_dat_out[12]);

--G1L495 is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[12]~44
--operation mode is normal

G1L495 = AMPP_FUNCTION(P1_ad_dat_out[12]);


--G1_trg_cfg_ad_out[13] is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[13]
--operation mode is normal

G1_trg_cfg_ad_out[13] = AMPP_FUNCTION(P1_ad_dat_out[13]);

--G1L795 is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[13]~45
--operation mode is normal

G1L795 = AMPP_FUNCTION(P1_ad_dat_out[13]);


--G1_trg_cfg_ad_out[14] is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[14]
--operation mode is normal

G1_trg_cfg_ad_out[14] = AMPP_FUNCTION(P1_ad_dat_out[14]);

--G1L006 is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[14]~46
--operation mode is normal

G1L006 = AMPP_FUNCTION(P1_ad_dat_out[14]);


--G1_trg_cfg_ad_out[15] is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[15]
--operation mode is normal

G1_trg_cfg_ad_out[15] = AMPP_FUNCTION(P1_ad_dat_out[15]);

--G1L306 is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[15]~47
--operation mode is normal

G1L306 = AMPP_FUNCTION(P1_ad_dat_out[15]);


--G1_trg_cfg_ad_out[16] is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[16]
--operation mode is normal

G1_trg_cfg_ad_out[16] = AMPP_FUNCTION();

--G1L606 is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[16]~48
--operation mode is normal

G1L606 = AMPP_FUNCTION();


--G1_trg_cfg_ad_out[17] is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[17]
--operation mode is normal

G1_trg_cfg_ad_out[17] = AMPP_FUNCTION();

--G1L906 is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[17]~49
--operation mode is normal

G1L906 = AMPP_FUNCTION();


--G1_trg_cfg_ad_out[18] is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[18]
--operation mode is normal

G1_trg_cfg_ad_out[18] = AMPP_FUNCTION(P1_ad_dat_out[18]);

--G1L216 is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[18]~50
--operation mode is normal

G1L216 = AMPP_FUNCTION(P1_ad_dat_out[18]);


--G1_trg_cfg_ad_out[19] is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[19]
--operation mode is normal

G1_trg_cfg_ad_out[19] = AMPP_FUNCTION();

--G1L516 is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[19]~51
--operation mode is normal

G1L516 = AMPP_FUNCTION();


--G1_trg_cfg_ad_out[20] is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[20]
--operation mode is normal

G1_trg_cfg_ad_out[20] = AMPP_FUNCTION(P1_ad_dat_out[20]);

--G1L816 is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[20]~52
--operation mode is normal

G1L816 = AMPP_FUNCTION(P1_ad_dat_out[20]);


--G1_trg_cfg_ad_out[21] is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[21]
--operation mode is normal

G1_trg_cfg_ad_out[21] = AMPP_FUNCTION(P1_ad_dat_out[21]);

--G1L126 is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[21]~53
--operation mode is normal

G1L126 = AMPP_FUNCTION(P1_ad_dat_out[21]);


--G1_trg_cfg_ad_out[22] is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[22]
--operation mode is normal

G1_trg_cfg_ad_out[22] = AMPP_FUNCTION(P1_ad_dat_out[22]);

--G1L426 is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[22]~54
--operation mode is normal

G1L426 = AMPP_FUNCTION(P1_ad_dat_out[22]);


--G1_trg_cfg_ad_out[23] is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[23]
--operation mode is normal

G1_trg_cfg_ad_out[23] = AMPP_FUNCTION(P1_ad_dat_out[23]);

--G1L726 is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[23]~55
--operation mode is normal

G1L726 = AMPP_FUNCTION(P1_ad_dat_out[23]);


--G1_trg_cfg_ad_out[24] is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[24]
--operation mode is normal

G1_trg_cfg_ad_out[24] = AMPP_FUNCTION(P1_ad_dat_out[24]);

--G1L036 is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[24]~56
--operation mode is normal

G1L036 = AMPP_FUNCTION(P1_ad_dat_out[24]);


--G1_trg_cfg_ad_out[25] is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[25]
--operation mode is normal

G1_trg_cfg_ad_out[25] = AMPP_FUNCTION(P1_ad_dat_out[25]);

--G1L336 is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[25]~57
--operation mode is normal

G1L336 = AMPP_FUNCTION(P1_ad_dat_out[25]);


--G1_trg_cfg_ad_out[26] is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[26]
--operation mode is normal

G1_trg_cfg_ad_out[26] = AMPP_FUNCTION(P1_ad_dat_out[26]);

--G1L636 is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[26]~58
--operation mode is normal

G1L636 = AMPP_FUNCTION(P1_ad_dat_out[26]);


--G1_trg_cfg_ad_out[27] is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[27]
--operation mode is normal

G1_trg_cfg_ad_out[27] = AMPP_FUNCTION(P1_ad_dat_out[27]);

--G1L936 is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[27]~59
--operation mode is normal

G1L936 = AMPP_FUNCTION(P1_ad_dat_out[27]);


--G1_trg_cfg_ad_out[28] is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[28]
--operation mode is normal

G1_trg_cfg_ad_out[28] = AMPP_FUNCTION(P1_ad_dat_out[28]);

--G1L246 is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[28]~60
--operation mode is normal

G1L246 = AMPP_FUNCTION(P1_ad_dat_out[28]);


--G1_trg_cfg_ad_out[29] is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[29]
--operation mode is normal

G1_trg_cfg_ad_out[29] = AMPP_FUNCTION(P1_ad_dat_out[29]);

--G1L546 is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[29]~61
--operation mode is normal

G1L546 = AMPP_FUNCTION(P1_ad_dat_out[29]);


--G1_trg_cfg_ad_out[30] is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[30]
--operation mode is normal

G1_trg_cfg_ad_out[30] = AMPP_FUNCTION(P1_ad_dat_out[30]);

--G1L846 is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[30]~62
--operation mode is normal

G1L846 = AMPP_FUNCTION(P1_ad_dat_out[30]);


--G1_trg_cfg_ad_out[31] is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[31]
--operation mode is normal

G1_trg_cfg_ad_out[31] = AMPP_FUNCTION(P1_ad_dat_out[31]);

--G1L156 is pci_contr:pci|pci_mt32:pci_mt32_inst|trg_cfg_ad_out[31]~63
--operation mode is normal

G1L156 = AMPP_FUNCTION(P1_ad_dat_out[31]);


--J1_dac_cmd is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|dac_cmd
--operation mode is normal

J1_dac_cmd = AMPP_FUNCTION();

--J1L841 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|dac_cmd~2
--operation mode is normal

J1L841 = AMPP_FUNCTION();


--J1_frame_or_lc2b is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|frame_or_lc2b
--operation mode is normal

J1_frame_or_lc2b = AMPP_FUNCTION(J1_MR_PXFR);

--J1L991 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|frame_or_lc2b~9
--operation mode is normal

J1L991 = AMPP_FUNCTION(J1_MR_PXFR);


--J1_DXFR_write_lc4a is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|DXFR_write_lc4a
--operation mode is normal

J1_DXFR_write_lc4a = AMPP_FUNCTION(J1_MS_DXFR, J1_irdy_or_not, J1_frame_or_not, J1_mstr_abrt);

--J1L771 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|DXFR_write_lc4a~2
--operation mode is normal

J1L771 = AMPP_FUNCTION(J1_MS_DXFR, J1_irdy_or_not, J1_frame_or_not, J1_mstr_abrt);


--J1_wr_rdn_set is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|wr_rdn_set
--operation mode is normal

J1_wr_rdn_set = AMPP_FUNCTION();

--J1L806 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|wr_rdn_set~2
--operation mode is normal

J1L806 = AMPP_FUNCTION();


--M1_rd_backoff is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|rd_backoff
--operation mode is normal

M1_rd_backoff = AMPP_FUNCTION(M1_TS_DISC);

--M1L334 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|rd_backoff~2
--operation mode is normal

M1L334 = AMPP_FUNCTION(M1_TS_DISC);


--J1_last_xfr is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|last_xfr
--operation mode is normal

J1_last_xfr = AMPP_FUNCTION(J1_last_xfr_lc1);

--J1L062 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|last_xfr~14
--operation mode is normal

J1L062 = AMPP_FUNCTION(J1_last_xfr_lc1);


--J1_MR_LPXFR is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LPXFR
--operation mode is normal

J1_MR_LPXFR = AMPP_FUNCTION(J1_MR_LPXFR_r1);

--J1L443 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LPXFR~16
--operation mode is normal

J1L443 = AMPP_FUNCTION(J1_MR_LPXFR_r1);


--J1_irdy_or_lc6a is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|irdy_or_lc6a
--operation mode is normal

J1_irdy_or_lc6a = AMPP_FUNCTION(J1_MR_PXFR);

--J1L822 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|irdy_or_lc6a~9
--operation mode is normal

J1L822 = AMPP_FUNCTION(J1_MR_PXFR);


--J1_DXFR_write_lc2 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|DXFR_write_lc2
--operation mode is normal

J1_DXFR_write_lc2 = AMPP_FUNCTION(J1_MS_ADR2, J1_MS_ADR, J1_dac_cyc_reg);

--J1L171 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|DXFR_write_lc2~6
--operation mode is normal

J1L171 = AMPP_FUNCTION(J1_MS_ADR2, J1_MS_ADR, J1_dac_cyc_reg);


--dpm_ni2f_fifo_h_result_dec_80_ix27_lc is dpm_ni2f_fifo_h_result_dec_80_ix27_lc
--operation mode is normal

dpm_ni2f_fifo_h_result_dec_80_ix27_lc = !dpm_ni2f_fifo_h_reg_nwords_0;

--A1L411 is dpm_ni2f_fifo_h_result_dec_80_ix27_lc~1
--operation mode is normal

A1L411 = !dpm_ni2f_fifo_h_reg_nwords_0;


--dpm_ni2f_fifo_h_result_inc_82_ix27_lc is dpm_ni2f_fifo_h_result_inc_82_ix27_lc
--operation mode is normal

dpm_ni2f_fifo_h_result_inc_82_ix27_lc = !dpm_ni2f_fifo_h_reg_nwords_0;

--A1L051 is dpm_ni2f_fifo_h_result_inc_82_ix27_lc~1
--operation mode is normal

A1L051 = !dpm_ni2f_fifo_h_reg_nwords_0;


--J1_MR_LLXFR_r1_d_lc1 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LLXFR_r1_d_lc1
--operation mode is normal

J1_MR_LLXFR_r1_d_lc1 = AMPP_FUNCTION();

--J1L913 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LLXFR_r1_d_lc1~2
--operation mode is normal

J1L913 = AMPP_FUNCTION();


--J1_MR_LWAIT_lc2 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LWAIT_lc2
--operation mode is normal

J1_MR_LWAIT_lc2 = AMPP_FUNCTION(J1_MR_LWAIT);

--J1L353 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LWAIT_lc2~9
--operation mode is normal

J1L353 = AMPP_FUNCTION(J1_MR_LWAIT);


--M1_lt_ack_R_r3_lc1 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_ack_R_r3_lc1
--operation mode is normal

M1_lt_ack_R_r3_lc1 = AMPP_FUNCTION(M1_LR_PXFR);

--M1L123 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_ack_R_r3_lc1~10
--operation mode is normal

M1L123 = AMPP_FUNCTION(M1_LR_PXFR);


--M1_lt_ack_R_r1_lc[3] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_ack_R_r1_lc[3]
--operation mode is normal

M1_lt_ack_R_r1_lc[3] = AMPP_FUNCTION(M1_LR_LXFR);

--M1L792 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_ack_R_r1_lc[3]~120
--operation mode is normal

M1L792 = AMPP_FUNCTION(M1_LR_LXFR);


--M1_lt_ack_R_r1_lc[1] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_ack_R_r1_lc[1]
--operation mode is normal

M1_lt_ack_R_r1_lc[1] = AMPP_FUNCTION();

--M1L192 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_ack_R_r1_lc[1]~121
--operation mode is normal

M1L192 = AMPP_FUNCTION();


--M1_lt_ack_R_r1_lc[2] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_ack_R_r1_lc[2]
--operation mode is normal

M1_lt_ack_R_r1_lc[2] = AMPP_FUNCTION(M1_lt_rdynR);

--M1L492 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|lt_ack_R_r1_lc[2]~122
--operation mode is normal

M1L492 = AMPP_FUNCTION(M1_lt_rdynR);


--J1_MW_WAIT_32_d_lc_1d is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_WAIT_32_d_lc_1d
--operation mode is normal

J1_MW_WAIT_32_d_lc_1d = AMPP_FUNCTION(J1_MW_WAIT_32_d_lc_1a);

--J1L045 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_WAIT_32_d_lc_1d~2
--operation mode is normal

J1L045 = AMPP_FUNCTION(J1_MW_WAIT_32_d_lc_1a);


--J1_MW_LAST_lc[1] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_LAST_lc[1]
--operation mode is normal

J1_MW_LAST_lc[1] = AMPP_FUNCTION(J1_latcntr_toR, J1_last_xfr_lc1, J1_MW_DXFR_32, J1_MW_WAIT_32_lc[2]);

--J1L294 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_LAST_lc[1]~18
--operation mode is normal

J1L294 = AMPP_FUNCTION(J1_latcntr_toR, J1_last_xfr_lc1, J1_MW_DXFR_32, J1_MW_WAIT_32_lc[2]);


--J1_MW_LAST_lc[2] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_LAST_lc[2]
--operation mode is normal

J1_MW_LAST_lc[2] = AMPP_FUNCTION(J1_MW_WAIT, J1_MW_DXFR, J1_lm_rdynR);

--J1L494 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_LAST_lc[2]~19
--operation mode is normal

J1L494 = AMPP_FUNCTION(J1_MW_WAIT, J1_MW_DXFR, J1_lm_rdynR);


--J1_MW_DXFR_lc[2] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_DXFR_lc[2]
--operation mode is normal

J1_MW_DXFR_lc[2] = AMPP_FUNCTION(J1_MW_WAIT, J1_MW_DXFR, J1_lm_rdynR);

--J1L054 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_DXFR_lc[2]~29
--operation mode is normal

J1L054 = AMPP_FUNCTION(J1_MW_WAIT, J1_MW_DXFR, J1_lm_rdynR);


--J1_frame_or_lc3c is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|frame_or_lc3c
--operation mode is normal

J1_frame_or_lc3c = AMPP_FUNCTION();

--J1L012 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|frame_or_lc3c~5
--operation mode is normal

J1L012 = AMPP_FUNCTION();


--J1_last_xfr_lc1 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|last_xfr_lc1
--operation mode is normal

J1_last_xfr_lc1 = AMPP_FUNCTION(J1_latcntr_toR);

--J1L852 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|last_xfr_lc1~2
--operation mode is normal

J1L852 = AMPP_FUNCTION(J1_latcntr_toR);


--J1_MW_HOLD_lc[1] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_HOLD_lc[1]
--operation mode is normal

J1_MW_HOLD_lc[1] = AMPP_FUNCTION();

--J1L874 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_HOLD_lc[1]~19
--operation mode is normal

J1L874 = AMPP_FUNCTION();


--J1_MW_DXFR_32_lc[3] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_DXFR_32_lc[3]
--operation mode is normal

J1_MW_DXFR_32_lc[3] = AMPP_FUNCTION(J1_MW_HOLD, J1_devsel_toR);

--J1L534 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_DXFR_32_lc[3]~14
--operation mode is normal

J1L534 = AMPP_FUNCTION(J1_MW_HOLD, J1_devsel_toR);


--J1_irdy_or_lc[2] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|irdy_or_lc[2]
--operation mode is normal

J1_irdy_or_lc[2] = AMPP_FUNCTION();

--J1L432 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|irdy_or_lc[2]~57
--operation mode is normal

J1L432 = AMPP_FUNCTION();


--J1_MW_IDLE_lc1 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_IDLE_lc1
--operation mode is normal

J1_MW_IDLE_lc1 = AMPP_FUNCTION(J1_MW_IDLE_not);

--J1L684 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_IDLE_lc1~9
--operation mode is normal

J1L684 = AMPP_FUNCTION(J1_MW_IDLE_not);


--M1_wait_wait32_lc[1] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|wait_wait32_lc[1]
--operation mode is normal

M1_wait_wait32_lc[1] = AMPP_FUNCTION(M1_lt_rdynR, M1_LR_PXFR, M1_TS_DISC);

--M1L945 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|wait_wait32_lc[1]~39
--operation mode is normal

M1L945 = AMPP_FUNCTION(M1_lt_rdynR, M1_LR_PXFR, M1_TS_DISC);


--M1_wait_wait32_lc[3] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|wait_wait32_lc[3]
--operation mode is normal

M1_wait_wait32_lc[3] = AMPP_FUNCTION(M1_LR_WAIT_32);

--M1L555 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|wait_wait32_lc[3]~40
--operation mode is normal

M1L555 = AMPP_FUNCTION(M1_LR_WAIT_32);


--J1_MW_WAIT_lc[2] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_WAIT_lc[2]
--operation mode is normal

J1_MW_WAIT_lc[2] = AMPP_FUNCTION(J1_MW_WAIT, J1_MW_DXFR_32, J1_devsel_toR, J1_lm_rdynR);

--J1L265 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_WAIT_lc[2]~23
--operation mode is normal

J1L265 = AMPP_FUNCTION(J1_MW_WAIT, J1_MW_DXFR_32, J1_devsel_toR, J1_lm_rdynR);


--J1_MW_WAIT_32_lc[1] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_WAIT_32_lc[1]
--operation mode is normal

J1_MW_WAIT_32_lc[1] = AMPP_FUNCTION(J1_MW_DXFR_32, J1_lm_rdynR, J1_last_xfr_lc1);

--J1L545 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_WAIT_32_lc[1]~33
--operation mode is normal

J1L545 = AMPP_FUNCTION(J1_MW_DXFR_32, J1_lm_rdynR, J1_last_xfr_lc1);


--J1_mstr_abrt_set is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|mstr_abrt_set
--operation mode is normal

J1_mstr_abrt_set = AMPP_FUNCTION(J1_devsel_toR);

--J1L124 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|mstr_abrt_set~8
--operation mode is normal

J1L124 = AMPP_FUNCTION(J1_devsel_toR);


--J1_MW_LXFR_lc[3] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_LXFR_lc[3]
--operation mode is normal

J1_MW_LXFR_lc[3] = AMPP_FUNCTION();

--J1L715 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_LXFR_lc[3]~56
--operation mode is normal

J1L715 = AMPP_FUNCTION();


--J1_MR_PXFR_lc2 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_PXFR_lc2
--operation mode is normal

J1_MR_PXFR_lc2 = AMPP_FUNCTION();

--J1L163 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_PXFR_lc2~2
--operation mode is normal

J1L163 = AMPP_FUNCTION();


--M1_trdy_OR_lc[1] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|trdy_OR_lc[1]
--operation mode is normal

M1_trdy_OR_lc[1] = AMPP_FUNCTION();

--M1L394 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|trdy_OR_lc[1]~87
--operation mode is normal

M1L394 = AMPP_FUNCTION();


--J1_MR_LWAIT_lc1 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LWAIT_lc1
--operation mode is normal

J1_MR_LWAIT_lc1 = AMPP_FUNCTION(J1_MR_PXFR, J1_devsel_toR);

--J1L053 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LWAIT_lc1~1
--operation mode is normal

J1L053 = AMPP_FUNCTION(J1_MR_PXFR, J1_devsel_toR);


--J1_MR_LLXFR_r2_d_lc1 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LLXFR_r2_d_lc1
--operation mode is normal

J1_MR_LLXFR_r2_d_lc1 = AMPP_FUNCTION();

--J1L033 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MR_LLXFR_r2_d_lc1~2
--operation mode is normal

J1L033 = AMPP_FUNCTION();


--M1_LR_LXFR_lc[1] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_LXFR_lc[1]
--operation mode is normal

M1_LR_LXFR_lc[1] = AMPP_FUNCTION();

--M1L412 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_LXFR_lc[1]~65
--operation mode is normal

M1L412 = AMPP_FUNCTION();


--M1_LR_LXFR_lc[2] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_LXFR_lc[2]
--operation mode is normal

M1_LR_LXFR_lc[2] = AMPP_FUNCTION();

--M1L712 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_LXFR_lc[2]~66
--operation mode is normal

M1L712 = AMPP_FUNCTION();


--J1_MW_WAIT_32_d_lc_1b is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_WAIT_32_d_lc_1b
--operation mode is normal

J1_MW_WAIT_32_d_lc_1b = AMPP_FUNCTION();

--J1L435 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_WAIT_32_d_lc_1b~9
--operation mode is normal

J1L435 = AMPP_FUNCTION();


--M1_LR_WAIT_32_lc1 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_WAIT_32_lc1
--operation mode is normal

M1_LR_WAIT_32_lc1 = AMPP_FUNCTION();

--M1L972 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_WAIT_32_lc1~9
--operation mode is normal

M1L972 = AMPP_FUNCTION();


--M1_LR_PXFR_32_lc[2] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_PXFR_32_lc[2]
--operation mode is normal

M1_LR_PXFR_32_lc[2] = AMPP_FUNCTION();

--M1L632 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_PXFR_32_lc[2]~17
--operation mode is normal

M1L632 = AMPP_FUNCTION();


--J1_MW_WAIT_32_lc[3] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_WAIT_32_lc[3]
--operation mode is normal

J1_MW_WAIT_32_lc[3] = AMPP_FUNCTION();

--J1L055 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_WAIT_32_lc[3]~34
--operation mode is normal

J1L055 = AMPP_FUNCTION();


--M1_LR_PXFR_lc[2] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_PXFR_lc[2]
--operation mode is normal

M1_LR_PXFR_lc[2] = AMPP_FUNCTION(M1_LR_PXFR, M1_lt_rdynR, M1_TS_DISC);

--M1L952 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_PXFR_lc[2]~37
--operation mode is normal

M1L952 = AMPP_FUNCTION(M1_LR_PXFR, M1_lt_rdynR, M1_TS_DISC);


--J1_MW_DXFR_32_lc[2] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_DXFR_32_lc[2]
--operation mode is normal

J1_MW_DXFR_32_lc[2] = AMPP_FUNCTION();

--J1L334 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_DXFR_32_lc[2]~15
--operation mode is normal

J1L334 = AMPP_FUNCTION();


--J1_MW_DXFR_32_lc[1] is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_DXFR_32_lc[1]
--operation mode is normal

J1_MW_DXFR_32_lc[1] = AMPP_FUNCTION();

--J1L034 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MW_DXFR_32_lc[1]~16
--operation mode is normal

J1L034 = AMPP_FUNCTION();


--dpm_ni2f_fifo_l_result_dec_80_ix27_lc is dpm_ni2f_fifo_l_result_dec_80_ix27_lc
--operation mode is normal

dpm_ni2f_fifo_l_result_dec_80_ix27_lc = !dpm_ni2f_fifo_l_reg_nwords_0;

--A1L822 is dpm_ni2f_fifo_l_result_dec_80_ix27_lc~1
--operation mode is normal

A1L822 = !dpm_ni2f_fifo_l_reg_nwords_0;


--dpm_ni2f_fifo_l_result_inc_82_ix27_lc is dpm_ni2f_fifo_l_result_inc_82_ix27_lc
--operation mode is normal

dpm_ni2f_fifo_l_result_inc_82_ix27_lc = !dpm_ni2f_fifo_l_reg_nwords_0;

--A1L462 is dpm_ni2f_fifo_l_result_inc_82_ix27_lc~1
--operation mode is normal

A1L462 = !dpm_ni2f_fifo_l_reg_nwords_0;


--A1L359 is ix2383~0
--operation mode is normal

A1L359 = (sg_reg_mx_q & (!dpm_dec_reg_rdata_LED_1) # !sg_reg_mx_q & !dpm_dec_reg_rdata_LED_5) & CASCADE(A1L947);

--A1L459 is ix2383~1
--operation mode is normal

A1L459 = (sg_reg_mx_q & (!dpm_dec_reg_rdata_LED_1) # !sg_reg_mx_q & !dpm_dec_reg_rdata_LED_5) & CASCADE(A1L947);


--A1L585 is ix2247~0
--operation mode is normal

A1L585 = (sg_reg_mx_q & (dpm_dec_reg_rdata_LED_1) # !sg_reg_mx_q & dpm_dec_reg_rdata_LED_5) & CASCADE(A1L8011);

--A1L685 is ix2247~1
--operation mode is normal

A1L685 = (sg_reg_mx_q & (dpm_dec_reg_rdata_LED_1) # !sg_reg_mx_q & dpm_dec_reg_rdata_LED_5) & CASCADE(A1L8011);


--A1L447 is ix2309~0
--operation mode is normal

A1L447 = (sg_reg_mx_q & (dpm_dec_reg_rdata_LED_0) # !sg_reg_mx_q & dpm_dec_reg_rdata_LED_4) & CASCADE(A1L085);

--A1L547 is ix2309~1
--operation mode is normal

A1L547 = (sg_reg_mx_q & (dpm_dec_reg_rdata_LED_0) # !sg_reg_mx_q & dpm_dec_reg_rdata_LED_4) & CASCADE(A1L085);


--A1L6011 is ix2575~0
--operation mode is normal

A1L6011 = (sg_reg_mx_q & (dpm_dec_reg_rdata_LED_2) # !sg_reg_mx_q & dpm_dec_reg_rdata_LED_6) & CASCADE(A1L0111);

--A1L7011 is ix2575~2
--operation mode is normal

A1L7011 = (sg_reg_mx_q & (dpm_dec_reg_rdata_LED_2) # !sg_reg_mx_q & dpm_dec_reg_rdata_LED_6) & CASCADE(A1L0111);

--A1L8011 is ix2575~3
--operation mode is normal

A1L8011 = (sg_reg_mx_q & (dpm_dec_reg_rdata_LED_2) # !sg_reg_mx_q & dpm_dec_reg_rdata_LED_6) & CASCADE(A1L0111);


--A1L868 is ix2354~0
--operation mode is normal

A1L868 = (G1_cben_ir_address[1] & G1_cben_ir_address[0] & !ix2382_lc) & CASCADE(A1L067);

--A1L968 is ix2354~1
--operation mode is normal

A1L968 = (G1_cben_ir_address[1] & G1_cben_ir_address[0] & !ix2382_lc) & CASCADE(A1L067);


--M1L58 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|_~1477
--operation mode is normal

M1L58 = AMPP_FUNCTION(M1_TS_ADR_CLMD, M1L12);

--M1L811 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|_~1527
--operation mode is normal

M1L811 = AMPP_FUNCTION(M1_TS_ADR_CLMD, M1L12);


--J1L31 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|$00135~29
--operation mode is normal

J1L31 = AMPP_FUNCTION(J1_MW_LXFR, J1_lm_rdynR, J1L71);

--J1L41 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|$00135~30
--operation mode is normal

J1L41 = AMPP_FUNCTION(J1_MW_LXFR, J1_lm_rdynR, J1L71);


--M1L954 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|stop_or_lc[3]~45
--operation mode is normal

M1L954 = AMPP_FUNCTION(M1L554, M1L99);

--M1L064 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|stop_or_lc[3]~53
--operation mode is normal

M1L064 = AMPP_FUNCTION(M1L554, M1L99);


--M1L78 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|_~1479
--operation mode is normal

M1L78 = AMPP_FUNCTION(M1_LW_LXFR, M1_TS_DXFR, dpm_dec_reg_LT_RDY_n_pci, M1L72);

--M1L911 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|_~1528
--operation mode is normal

M1L911 = AMPP_FUNCTION(M1_LW_LXFR, M1_TS_DXFR, dpm_dec_reg_LT_RDY_n_pci, M1L72);


--M1L91 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|$00133~10
--operation mode is normal

M1L91 = AMPP_FUNCTION(M1_trdy_OR_NOT, M1_TS_DXFR, M1L101);

--M1L02 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|$00133~12
--operation mode is normal

M1L02 = AMPP_FUNCTION(M1_trdy_OR_NOT, M1_TS_DXFR, M1L101);

--M1L12 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|$00133~13
--operation mode is normal

M1L12 = AMPP_FUNCTION(M1_trdy_OR_NOT, M1_TS_DXFR, M1L101);


--M1L52 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|$00151~10
--operation mode is normal

M1L52 = AMPP_FUNCTION(M1_lt_rdynR, M1_LR_PXFR, M1_TS_DISC, M1L801);

--M1L62 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|$00151~12
--operation mode is normal

M1L62 = AMPP_FUNCTION(M1_lt_rdynR, M1_LR_PXFR, M1_TS_DISC, M1L801);

--M1L72 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|$00151~13
--operation mode is normal

M1L72 = AMPP_FUNCTION(M1_lt_rdynR, M1_LR_PXFR, M1_TS_DISC, M1L801);


--M1L625 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|TS_DXFR_d_lc[3]~45
--operation mode is normal

M1L625 = AMPP_FUNCTION(M1_cfg_cyc, M1_targ_burst_lc, M1L301);

--M1L725 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|TS_DXFR_d_lc[3]~47
--operation mode is normal

M1L725 = AMPP_FUNCTION(M1_cfg_cyc, M1_targ_burst_lc, M1L301);


--M1L983 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LW_IDLE_lc1~37
--operation mode is normal

M1L983 = AMPP_FUNCTION(dpm_dec_reg_LT_RDY_n_pci, M1L83);

--M1L193 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LW_IDLE_lc1~40
--operation mode is normal

M1L193 = AMPP_FUNCTION(dpm_dec_reg_LT_RDY_n_pci, M1L83);


--M1L754 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|stop_or_lc[2]~46
--operation mode is normal

M1L754 = AMPP_FUNCTION(M1_retry, M1L311);

--M1L854 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|stop_or_lc[2]~54
--operation mode is normal

M1L854 = AMPP_FUNCTION(M1_retry, M1L311);


--M1L554 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|stop_or_lc[1]~47
--operation mode is normal

M1L554 = AMPP_FUNCTION(M1_TS_DISC, M1L054);

--M1L654 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|stop_or_lc[1]~55
--operation mode is normal

M1L654 = AMPP_FUNCTION(M1_TS_DISC, M1L054);


--M1L812 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_LXFR_lc[3]~59
--operation mode is normal

M1L812 = AMPP_FUNCTION(M1L44);

--M1L912 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_LXFR_lc[3]~67
--operation mode is normal

M1L912 = AMPP_FUNCTION(M1L44);


--M1L504 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LW_LXFR_lc[1]~75
--operation mode is normal

M1L504 = AMPP_FUNCTION(dpm_dec_reg_LT_RDY_n_pci, M1L14);

--M1L704 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LW_LXFR_lc[1]~80
--operation mode is normal

M1L704 = AMPP_FUNCTION(dpm_dec_reg_LT_RDY_n_pci, M1L14);


--M1L452 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_PXFR_lc[1]~34
--operation mode is normal

M1L452 = AMPP_FUNCTION(M1_LR_LXFR, M1L252);

--M1L552 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_PXFR_lc[1]~38
--operation mode is normal

M1L552 = AMPP_FUNCTION(M1_LR_LXFR, M1L252);


--M1L422 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_LXFR_lc[5]~60
--operation mode is normal

M1L422 = AMPP_FUNCTION(M1_retry, M1L74);

--M1L622 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_LXFR_lc[5]~68
--operation mode is normal

M1L622 = AMPP_FUNCTION(M1_retry, M1L74);


--M1L891 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_IDLE_lc1~33
--operation mode is normal

M1L891 = AMPP_FUNCTION(M1_retry, M1L711);

--M1L002 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|LR_IDLE_lc1~36
--operation mode is normal

M1L002 = AMPP_FUNCTION(M1_retry, M1L711);


--M1L05 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|$00192~1
--operation mode is normal

M1L05 = AMPP_FUNCTION(M1L35);

--M1L15 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|$00192~3
--operation mode is normal

M1L15 = AMPP_FUNCTION(M1L35);

--M1L25 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_t:trg|$00192~4
--operation mode is normal

M1L25 = AMPP_FUNCTION(M1L35);


--~GND is ~GND
--operation mode is normal

~GND = GND;

--A1L9131 is ~GND~0
--operation mode is normal

A1L9131 = GND;


--CLK50M is CLK50M
--operation mode is input

CLK50M = INPUT();


--LVDS_in[0] is LVDS_in[0]
--operation mode is input

LVDS_in[0] = INPUT();


--LVDS_in[1] is LVDS_in[1]
--operation mode is input

LVDS_in[1] = INPUT();


--LVDS_in[2] is LVDS_in[2]
--operation mode is input

LVDS_in[2] = INPUT();


--LVDS_in[3] is LVDS_in[3]
--operation mode is input

LVDS_in[3] = INPUT();


--pci_lockn is pci_lockn
--operation mode is input

pci_lockn = INPUT();


--pci_rstn is pci_rstn
--operation mode is input

pci_rstn = INPUT();


--DES_CLK is DES_CLK
--operation mode is input

DES_CLK = INPUT();


--DES_EN is DES_EN
--operation mode is input

DES_EN = INPUT();


--pci_clk is pci_clk
--operation mode is input

pci_clk = INPUT();


--pci_gntn is pci_gntn
--operation mode is input

pci_gntn = INPUT();


--DES_ER is DES_ER
--operation mode is input

DES_ER = INPUT();


--DES_DATA[0] is DES_DATA[0]
--operation mode is input

DES_DATA[0] = INPUT();


--DES_DATA[1] is DES_DATA[1]
--operation mode is input

DES_DATA[1] = INPUT();


--DES_DATA[2] is DES_DATA[2]
--operation mode is input

DES_DATA[2] = INPUT();


--DES_DATA[3] is DES_DATA[3]
--operation mode is input

DES_DATA[3] = INPUT();


--DES_DATA[4] is DES_DATA[4]
--operation mode is input

DES_DATA[4] = INPUT();


--DES_DATA[5] is DES_DATA[5]
--operation mode is input

DES_DATA[5] = INPUT();


--DES_DATA[6] is DES_DATA[6]
--operation mode is input

DES_DATA[6] = INPUT();


--DES_DATA[7] is DES_DATA[7]
--operation mode is input

DES_DATA[7] = INPUT();


--DES_DATA[8] is DES_DATA[8]
--operation mode is input

DES_DATA[8] = INPUT();


--DES_DATA[9] is DES_DATA[9]
--operation mode is input

DES_DATA[9] = INPUT();


--DES_DATA[10] is DES_DATA[10]
--operation mode is input

DES_DATA[10] = INPUT();


--DES_DATA[11] is DES_DATA[11]
--operation mode is input

DES_DATA[11] = INPUT();


--DES_DATA[12] is DES_DATA[12]
--operation mode is input

DES_DATA[12] = INPUT();


--DES_DATA[13] is DES_DATA[13]
--operation mode is input

DES_DATA[13] = INPUT();


--DES_DATA[14] is DES_DATA[14]
--operation mode is input

DES_DATA[14] = INPUT();


--DES_DATA[15] is DES_DATA[15]
--operation mode is input

DES_DATA[15] = INPUT();


--pci_idsel is pci_idsel
--operation mode is input

pci_idsel = INPUT();


--KCLK is KCLK
--operation mode is output

KCLK = OUTPUT(!dpm_ni2f_reg_we_n);


--KDAT is KDAT
--operation mode is output

KDAT = OUTPUT(dpm_ni2f_reg_not_empty);


--LED_GRN is LED_GRN
--operation mode is output

LED_GRN = OUTPUT(!dpm_ni2f_reg_not_empty);


--LED_RED is LED_RED
--operation mode is output

LED_RED = OUTPUT(dpm_ni2f_reg_not_empty);


--LVDS_EN is LVDS_EN
--operation mode is output

LVDS_EN = OUTPUT(VCC);


--LVDS_out[0] is LVDS_out[0]
--operation mode is output

LVDS_out[0] = OUTPUT(GND);


--LVDS_out[1] is LVDS_out[1]
--operation mode is output

LVDS_out[1] = OUTPUT(GND);


--LVDS_out[2] is LVDS_out[2]
--operation mode is output

LVDS_out[2] = OUTPUT(GND);


--LVDS_out[3] is LVDS_out[3]
--operation mode is output

LVDS_out[3] = OUTPUT(GND);


--MCLK is MCLK
--operation mode is output

MCLK = OUTPUT(dpm_ni2f_reg_ds_en_reg);


--pci_intan is pci_intan
--operation mode is output

pci_intan = OUTPUT(VCC);


--pci_reqn is pci_reqn
--operation mode is output

pci_reqn_open_drain_out = OPNDRN(VCC);
pci_reqn = OUTPUT(pci_reqn_open_drain_out);


--pci_serrn is pci_serrn
--operation mode is output

pci_serrn_open_drain_out = OPNDRN(!K1_serr_or);
pci_serrn = OUTPUT(pci_serrn_open_drain_out);


--R7S[7] is R7S[7]
--operation mode is output

R7S[7] = OUTPUT(ix2698_lc);


--R7S[6] is R7S[6]
--operation mode is output

R7S[6] = OUTPUT(ix2697_lc);


--R7S[5] is R7S[5]
--operation mode is output

R7S[5] = OUTPUT(ix2696_lc);


--R7S[4] is R7S[4]
--operation mode is output

R7S[4] = OUTPUT(ix2695_lc);


--R7S[3] is R7S[3]
--operation mode is output

R7S[3] = OUTPUT(ix2694_lc);


--R7S[2] is R7S[2]
--operation mode is output

R7S[2] = OUTPUT(ix2693_lc);


--R7S[1] is R7S[1]
--operation mode is output

R7S[1] = OUTPUT(ix2692_lc);


--R7S_mux is R7S_mux
--operation mode is output

R7S_mux = OUTPUT(sg_reg_mx_q);


--SRAM_AD[0] is SRAM_AD[0]
--operation mode is output

SRAM_AD[0] = OUTPUT(dpm_ni2f_reg_addr_0);


--SRAM_AD[1] is SRAM_AD[1]
--operation mode is output

SRAM_AD[1] = OUTPUT(dpm_ni2f_reg_addr_1);


--SRAM_AD[2] is SRAM_AD[2]
--operation mode is output

SRAM_AD[2] = OUTPUT(dpm_ni2f_reg_addr_2);


--SRAM_AD[3] is SRAM_AD[3]
--operation mode is output

SRAM_AD[3] = OUTPUT(dpm_ni2f_reg_addr_3);


--SRAM_AD[4] is SRAM_AD[4]
--operation mode is output

SRAM_AD[4] = OUTPUT(dpm_ni2f_reg_addr_4);


--SRAM_AD[5] is SRAM_AD[5]
--operation mode is output

SRAM_AD[5] = OUTPUT(dpm_ni2f_reg_addr_5);


--SRAM_AD[6] is SRAM_AD[6]
--operation mode is output

SRAM_AD[6] = OUTPUT(dpm_ni2f_reg_addr_6);


--SRAM_AD[7] is SRAM_AD[7]
--operation mode is output

SRAM_AD[7] = OUTPUT(dpm_ni2f_reg_addr_7);


--SRAM_AD[8] is SRAM_AD[8]
--operation mode is output

SRAM_AD[8] = OUTPUT(dpm_ni2f_reg_addr_8);


--SRAM_AD[9] is SRAM_AD[9]
--operation mode is output

SRAM_AD[9] = OUTPUT(dpm_ni2f_reg_addr_9);


--SRAM_AD[10] is SRAM_AD[10]
--operation mode is output

SRAM_AD[10] = OUTPUT(dpm_ni2f_reg_addr_10);


--SRAM_AD[11] is SRAM_AD[11]
--operation mode is output

SRAM_AD[11] = OUTPUT(dpm_ni2f_reg_addr_11);


--SRAM_AD[12] is SRAM_AD[12]
--operation mode is output

SRAM_AD[12] = OUTPUT(dpm_ni2f_reg_addr_12);


--SRAM_AD[13] is SRAM_AD[13]
--operation mode is output

SRAM_AD[13] = OUTPUT(dpm_ni2f_reg_addr_13);


--SRAM_AD[14] is SRAM_AD[14]
--operation mode is output

SRAM_AD[14] = OUTPUT(dpm_ni2f_reg_addr_14);


--SRAM_AD[15] is SRAM_AD[15]
--operation mode is output

SRAM_AD[15] = OUTPUT(dpm_ni2f_reg_addr_15);


--SRAM_AD[16] is SRAM_AD[16]
--operation mode is output

SRAM_AD[16] = OUTPUT(dpm_ni2f_reg_addr_16);


--SRAM_AD[17] is SRAM_AD[17]
--operation mode is output

SRAM_AD[17] = OUTPUT(dpm_ni2f_reg_addr_17);


--SRAM_BW1n is SRAM_BW1n
--operation mode is output

SRAM_BW1n = OUTPUT(!dpm_ni2f_reg_we_n);


--SRAM_BW2n is SRAM_BW2n
--operation mode is output

SRAM_BW2n = OUTPUT(!dpm_ni2f_reg_we_n);


--SRAM_CEn is SRAM_CEn
--operation mode is output

SRAM_CEn = OUTPUT(!dpm_ni2f_reg_ce_n);


--SRAM_CLK is SRAM_CLK
--operation mode is output

SRAM_CLK = OUTPUT(!dpm_ni2f_reg_clk_sram_i);


--SRAM_OEn is SRAM_OEn
--operation mode is output

SRAM_OEn = OUTPUT(!dpm_ni2f_reg_re_n);


--pci_ad_0 is pci_ad_0
--operation mode is bidir

pci_ad_0 = pci_ad[0];

--pci_ad[0] is pci_ad[0]
--operation mode is bidir

pci_ad[0]_tri_out = TRI(G1_low_ad_or[0], G1_ad_tri_oe);
pci_ad[0] = BIDIR(pci_ad[0]_tri_out);


--pci_ad_1 is pci_ad_1
--operation mode is bidir

pci_ad_1 = pci_ad[1];

--pci_ad[1] is pci_ad[1]
--operation mode is bidir

pci_ad[1]_tri_out = TRI(G1_low_ad_or[1], G1_ad_tri_oe);
pci_ad[1] = BIDIR(pci_ad[1]_tri_out);


--pci_ad_2 is pci_ad_2
--operation mode is bidir

pci_ad_2 = pci_ad[2];

--pci_ad[2] is pci_ad[2]
--operation mode is bidir

pci_ad[2]_tri_out = TRI(G1_low_ad_or[2], G1_ad_tri_oe);
pci_ad[2] = BIDIR(pci_ad[2]_tri_out);


--pci_ad_3 is pci_ad_3
--operation mode is bidir

pci_ad_3 = pci_ad[3];

--pci_ad[3] is pci_ad[3]
--operation mode is bidir

pci_ad[3]_tri_out = TRI(G1_low_ad_or[3], G1_ad_tri_oe);
pci_ad[3] = BIDIR(pci_ad[3]_tri_out);


--pci_ad_4 is pci_ad_4
--operation mode is bidir

pci_ad_4 = pci_ad[4];

--pci_ad[4] is pci_ad[4]
--operation mode is bidir

pci_ad[4]_tri_out = TRI(G1_low_ad_or[4], G1_ad_tri_oe);
pci_ad[4] = BIDIR(pci_ad[4]_tri_out);


--pci_ad_5 is pci_ad_5
--operation mode is bidir

pci_ad_5 = pci_ad[5];

--pci_ad[5] is pci_ad[5]
--operation mode is bidir

pci_ad[5]_tri_out = TRI(G1_low_ad_or[5], G1_ad_tri_oe);
pci_ad[5] = BIDIR(pci_ad[5]_tri_out);


--pci_ad_6 is pci_ad_6
--operation mode is bidir

pci_ad_6 = pci_ad[6];

--pci_ad[6] is pci_ad[6]
--operation mode is bidir

pci_ad[6]_tri_out = TRI(G1_low_ad_or[6], G1_ad_tri_oe);
pci_ad[6] = BIDIR(pci_ad[6]_tri_out);


--pci_ad_7 is pci_ad_7
--operation mode is bidir

pci_ad_7 = pci_ad[7];

--pci_ad[7] is pci_ad[7]
--operation mode is bidir

pci_ad[7]_tri_out = TRI(G1_low_ad_or[7], G1_ad_tri_oe);
pci_ad[7] = BIDIR(pci_ad[7]_tri_out);


--pci_ad_8 is pci_ad_8
--operation mode is bidir

pci_ad_8 = pci_ad[8];

--pci_ad[8] is pci_ad[8]
--operation mode is bidir

pci_ad[8]_tri_out = TRI(G1_low_ad_or[8], G1_ad_tri_oe);
pci_ad[8] = BIDIR(pci_ad[8]_tri_out);


--pci_ad_9 is pci_ad_9
--operation mode is bidir

pci_ad_9 = pci_ad[9];

--pci_ad[9] is pci_ad[9]
--operation mode is bidir

pci_ad[9]_tri_out = TRI(G1_low_ad_or[9], G1_ad_tri_oe);
pci_ad[9] = BIDIR(pci_ad[9]_tri_out);


--pci_ad_10 is pci_ad_10
--operation mode is bidir

pci_ad_10 = pci_ad[10];

--pci_ad[10] is pci_ad[10]
--operation mode is bidir

pci_ad[10]_tri_out = TRI(G1_low_ad_or[10], G1_ad_tri_oe);
pci_ad[10] = BIDIR(pci_ad[10]_tri_out);


--pci_ad_11 is pci_ad_11
--operation mode is bidir

pci_ad_11 = pci_ad[11];

--pci_ad[11] is pci_ad[11]
--operation mode is bidir

pci_ad[11]_tri_out = TRI(G1_low_ad_or[11], G1_ad_tri_oe);
pci_ad[11] = BIDIR(pci_ad[11]_tri_out);


--pci_ad_12 is pci_ad_12
--operation mode is bidir

pci_ad_12 = pci_ad[12];

--pci_ad[12] is pci_ad[12]
--operation mode is bidir

pci_ad[12]_tri_out = TRI(G1_low_ad_or[12], G1_ad_tri_oe);
pci_ad[12] = BIDIR(pci_ad[12]_tri_out);


--pci_ad_13 is pci_ad_13
--operation mode is bidir

pci_ad_13 = pci_ad[13];

--pci_ad[13] is pci_ad[13]
--operation mode is bidir

pci_ad[13]_tri_out = TRI(G1_low_ad_or[13], G1_ad_tri_oe);
pci_ad[13] = BIDIR(pci_ad[13]_tri_out);


--pci_ad_14 is pci_ad_14
--operation mode is bidir

pci_ad_14 = pci_ad[14];

--pci_ad[14] is pci_ad[14]
--operation mode is bidir

pci_ad[14]_tri_out = TRI(G1_low_ad_or[14], G1_ad_tri_oe);
pci_ad[14] = BIDIR(pci_ad[14]_tri_out);


--pci_ad_15 is pci_ad_15
--operation mode is bidir

pci_ad_15 = pci_ad[15];

--pci_ad[15] is pci_ad[15]
--operation mode is bidir

pci_ad[15]_tri_out = TRI(G1_low_ad_or[15], G1_ad_tri_oe);
pci_ad[15] = BIDIR(pci_ad[15]_tri_out);


--pci_ad_16 is pci_ad_16
--operation mode is bidir

pci_ad_16 = pci_ad[16];

--pci_ad[16] is pci_ad[16]
--operation mode is bidir

pci_ad[16]_tri_out = TRI(G1_low_ad_or[16], G1_ad_tri_oe);
pci_ad[16] = BIDIR(pci_ad[16]_tri_out);


--pci_ad_17 is pci_ad_17
--operation mode is bidir

pci_ad_17 = pci_ad[17];

--pci_ad[17] is pci_ad[17]
--operation mode is bidir

pci_ad[17]_tri_out = TRI(G1_low_ad_or[17], G1_ad_tri_oe);
pci_ad[17] = BIDIR(pci_ad[17]_tri_out);


--pci_ad_18 is pci_ad_18
--operation mode is bidir

pci_ad_18 = pci_ad[18];

--pci_ad[18] is pci_ad[18]
--operation mode is bidir

pci_ad[18]_tri_out = TRI(G1_low_ad_or[18], G1_ad_tri_oe);
pci_ad[18] = BIDIR(pci_ad[18]_tri_out);


--pci_ad_19 is pci_ad_19
--operation mode is bidir

pci_ad_19 = pci_ad[19];

--pci_ad[19] is pci_ad[19]
--operation mode is bidir

pci_ad[19]_tri_out = TRI(G1_low_ad_or[19], G1_ad_tri_oe);
pci_ad[19] = BIDIR(pci_ad[19]_tri_out);


--pci_ad_20 is pci_ad_20
--operation mode is bidir

pci_ad_20 = pci_ad[20];

--pci_ad[20] is pci_ad[20]
--operation mode is bidir

pci_ad[20]_tri_out = TRI(G1_low_ad_or[20], G1_ad_tri_oe);
pci_ad[20] = BIDIR(pci_ad[20]_tri_out);


--pci_ad_21 is pci_ad_21
--operation mode is bidir

pci_ad_21 = pci_ad[21];

--pci_ad[21] is pci_ad[21]
--operation mode is bidir

pci_ad[21]_tri_out = TRI(G1_low_ad_or[21], G1_ad_tri_oe);
pci_ad[21] = BIDIR(pci_ad[21]_tri_out);


--pci_ad_22 is pci_ad_22
--operation mode is bidir

pci_ad_22 = pci_ad[22];

--pci_ad[22] is pci_ad[22]
--operation mode is bidir

pci_ad[22]_tri_out = TRI(G1_low_ad_or[22], G1_ad_tri_oe);
pci_ad[22] = BIDIR(pci_ad[22]_tri_out);


--pci_ad_23 is pci_ad_23
--operation mode is bidir

pci_ad_23 = pci_ad[23];

--pci_ad[23] is pci_ad[23]
--operation mode is bidir

pci_ad[23]_tri_out = TRI(G1_low_ad_or[23], G1_ad_tri_oe);
pci_ad[23] = BIDIR(pci_ad[23]_tri_out);


--pci_ad_24 is pci_ad_24
--operation mode is bidir

pci_ad_24 = pci_ad[24];

--pci_ad[24] is pci_ad[24]
--operation mode is bidir

pci_ad[24]_tri_out = TRI(G1_low_ad_or[24], G1_ad_tri_oe);
pci_ad[24] = BIDIR(pci_ad[24]_tri_out);


--pci_ad_25 is pci_ad_25
--operation mode is bidir

pci_ad_25 = pci_ad[25];

--pci_ad[25] is pci_ad[25]
--operation mode is bidir

pci_ad[25]_tri_out = TRI(G1_low_ad_or[25], G1_ad_tri_oe);
pci_ad[25] = BIDIR(pci_ad[25]_tri_out);


--pci_ad_26 is pci_ad_26
--operation mode is bidir

pci_ad_26 = pci_ad[26];

--pci_ad[26] is pci_ad[26]
--operation mode is bidir

pci_ad[26]_tri_out = TRI(G1_low_ad_or[26], G1_ad_tri_oe);
pci_ad[26] = BIDIR(pci_ad[26]_tri_out);


--pci_ad_27 is pci_ad_27
--operation mode is bidir

pci_ad_27 = pci_ad[27];

--pci_ad[27] is pci_ad[27]
--operation mode is bidir

pci_ad[27]_tri_out = TRI(G1_low_ad_or[27], G1_ad_tri_oe);
pci_ad[27] = BIDIR(pci_ad[27]_tri_out);


--pci_ad_28 is pci_ad_28
--operation mode is bidir

pci_ad_28 = pci_ad[28];

--pci_ad[28] is pci_ad[28]
--operation mode is bidir

pci_ad[28]_tri_out = TRI(G1_low_ad_or[28], G1_ad_tri_oe);
pci_ad[28] = BIDIR(pci_ad[28]_tri_out);


--pci_ad_29 is pci_ad_29
--operation mode is bidir

pci_ad_29 = pci_ad[29];

--pci_ad[29] is pci_ad[29]
--operation mode is bidir

pci_ad[29]_tri_out = TRI(G1_low_ad_or[29], G1_ad_tri_oe);
pci_ad[29] = BIDIR(pci_ad[29]_tri_out);


--pci_ad_30 is pci_ad_30
--operation mode is bidir

pci_ad_30 = pci_ad[30];

--pci_ad[30] is pci_ad[30]
--operation mode is bidir

pci_ad[30]_tri_out = TRI(G1_low_ad_or[30], G1_ad_tri_oe);
pci_ad[30] = BIDIR(pci_ad[30]_tri_out);


--pci_ad_31 is pci_ad_31
--operation mode is bidir

pci_ad_31 = pci_ad[31];

--pci_ad[31] is pci_ad[31]
--operation mode is bidir

pci_ad[31]_tri_out = TRI(G1_low_ad_or[31], G1_ad_tri_oe);
pci_ad[31] = BIDIR(pci_ad[31]_tri_out);


--pci_cben_0 is pci_cben_0
--operation mode is bidir

pci_cben_0 = pci_cben[0];

--pci_cben[0] is pci_cben[0]
--operation mode is bidir

pci_cben[0]_tri_out = TRI(G1_low_cben_or[0], !J1_cbe_oer_not);
pci_cben[0] = BIDIR(pci_cben[0]_tri_out);


--pci_cben_1 is pci_cben_1
--operation mode is bidir

pci_cben_1 = pci_cben[1];

--pci_cben[1] is pci_cben[1]
--operation mode is bidir

pci_cben[1]_tri_out = TRI(G1_low_cben_or[1], !J1_cbe_oer_not);
pci_cben[1] = BIDIR(pci_cben[1]_tri_out);


--pci_cben_2 is pci_cben_2
--operation mode is bidir

pci_cben_2 = pci_cben[2];

--pci_cben[2] is pci_cben[2]
--operation mode is bidir

pci_cben[2]_tri_out = TRI(G1_low_cben_or[2], !J1_cbe_oer_not);
pci_cben[2] = BIDIR(pci_cben[2]_tri_out);


--pci_cben_3 is pci_cben_3
--operation mode is bidir

pci_cben_3 = pci_cben[3];

--pci_cben[3] is pci_cben[3]
--operation mode is bidir

pci_cben[3]_tri_out = TRI(G1_low_cben_or[3], !J1_cbe_oer_not);
pci_cben[3] = BIDIR(pci_cben[3]_tri_out);


--A1L8221 is pci_devseln~0
--operation mode is bidir

A1L8221 = pci_devseln;

--pci_devseln is pci_devseln
--operation mode is bidir

pci_devseln_tri_out = TRI(M1_devsel_OR_not, M1_targ_oeR_reg);
pci_devseln = BIDIR(pci_devseln_tri_out);


--A1L0321 is pci_framen~0
--operation mode is bidir

A1L0321 = pci_framen;

--pci_framen is pci_framen
--operation mode is bidir

pci_framen_tri_out = TRI(J1_frame_or_not, !J1_cbe_oer_not);
pci_framen = BIDIR(pci_framen_tri_out);


--A1L5321 is pci_irdyn~0
--operation mode is bidir

A1L5321 = pci_irdyn;

--pci_irdyn is pci_irdyn
--operation mode is bidir

pci_irdyn_tri_out = TRI(J1_irdy_or_not, J1_irdy_oer);
pci_irdyn = BIDIR(pci_irdyn_tri_out);


--A1L8321 is pci_par~0
--operation mode is bidir

A1L8321 = pci_par;

--pci_par is pci_par
--operation mode is bidir

pci_par_tri_out = TRI(G1_par_or, G1_par_oeR);
pci_par = BIDIR(pci_par_tri_out);


--A1L0421 is pci_perrn~0
--operation mode is bidir

A1L0421 = pci_perrn;

--pci_perrn is pci_perrn
--operation mode is bidir

pci_perrn_tri_out = TRI(!K1_perr_or_not, G1_perr_oe_r);
pci_perrn = BIDIR(pci_perrn_tri_out);


--A1L5421 is pci_stopn~0
--operation mode is bidir

A1L5421 = pci_stopn;

--pci_stopn is pci_stopn
--operation mode is bidir

pci_stopn_tri_out = TRI(M1_stop_OR_NOT, M1_targ_oeR_reg);
pci_stopn = BIDIR(pci_stopn_tri_out);


--A1L7421 is pci_trdyn~0
--operation mode is bidir

A1L7421 = pci_trdyn;

--pci_trdyn is pci_trdyn
--operation mode is bidir

pci_trdyn_tri_out = TRI(M1_trdy_OR_NOT, M1_targ_oeR_reg);
pci_trdyn = BIDIR(pci_trdyn_tri_out);


--SRAM_IO_0 is SRAM_IO_0
--operation mode is bidir

SRAM_IO_0 = SRAM_IO[0];

--SRAM_IO[0] is SRAM_IO[0]
--operation mode is bidir

SRAM_IO[0]_tri_out = TRI(F2_q[0], dpm_ni2f_reg_we_n);
SRAM_IO[0] = BIDIR(SRAM_IO[0]_tri_out);


--SRAM_IO_1 is SRAM_IO_1
--operation mode is bidir

SRAM_IO_1 = SRAM_IO[1];

--SRAM_IO[1] is SRAM_IO[1]
--operation mode is bidir

SRAM_IO[1]_tri_out = TRI(F2_q[1], dpm_ni2f_reg_we_n);
SRAM_IO[1] = BIDIR(SRAM_IO[1]_tri_out);


--SRAM_IO_2 is SRAM_IO_2
--operation mode is bidir

SRAM_IO_2 = SRAM_IO[2];

--SRAM_IO[2] is SRAM_IO[2]
--operation mode is bidir

SRAM_IO[2]_tri_out = TRI(F2_q[2], dpm_ni2f_reg_we_n);
SRAM_IO[2] = BIDIR(SRAM_IO[2]_tri_out);


--SRAM_IO_3 is SRAM_IO_3
--operation mode is bidir

SRAM_IO_3 = SRAM_IO[3];

--SRAM_IO[3] is SRAM_IO[3]
--operation mode is bidir

SRAM_IO[3]_tri_out = TRI(F2_q[3], dpm_ni2f_reg_we_n);
SRAM_IO[3] = BIDIR(SRAM_IO[3]_tri_out);


--SRAM_IO_4 is SRAM_IO_4
--operation mode is bidir

SRAM_IO_4 = SRAM_IO[4];

--SRAM_IO[4] is SRAM_IO[4]
--operation mode is bidir

SRAM_IO[4]_tri_out = TRI(F2_q[4], dpm_ni2f_reg_we_n);
SRAM_IO[4] = BIDIR(SRAM_IO[4]_tri_out);


--SRAM_IO_5 is SRAM_IO_5
--operation mode is bidir

SRAM_IO_5 = SRAM_IO[5];

--SRAM_IO[5] is SRAM_IO[5]
--operation mode is bidir

SRAM_IO[5]_tri_out = TRI(F2_q[5], dpm_ni2f_reg_we_n);
SRAM_IO[5] = BIDIR(SRAM_IO[5]_tri_out);


--SRAM_IO_6 is SRAM_IO_6
--operation mode is bidir

SRAM_IO_6 = SRAM_IO[6];

--SRAM_IO[6] is SRAM_IO[6]
--operation mode is bidir

SRAM_IO[6]_tri_out = TRI(F2_q[6], dpm_ni2f_reg_we_n);
SRAM_IO[6] = BIDIR(SRAM_IO[6]_tri_out);


--SRAM_IO_7 is SRAM_IO_7
--operation mode is bidir

SRAM_IO_7 = SRAM_IO[7];

--SRAM_IO[7] is SRAM_IO[7]
--operation mode is bidir

SRAM_IO[7]_tri_out = TRI(F2_q[7], dpm_ni2f_reg_we_n);
SRAM_IO[7] = BIDIR(SRAM_IO[7]_tri_out);


--SRAM_IO_8 is SRAM_IO_8
--operation mode is bidir

SRAM_IO_8 = SRAM_IO[8];

--SRAM_IO[8] is SRAM_IO[8]
--operation mode is bidir

SRAM_IO[8]_tri_out = TRI(F1_q[0], dpm_ni2f_reg_we_n);
SRAM_IO[8] = BIDIR(SRAM_IO[8]_tri_out);


--SRAM_IO_9 is SRAM_IO_9
--operation mode is bidir

SRAM_IO_9 = SRAM_IO[9];

--SRAM_IO[9] is SRAM_IO[9]
--operation mode is bidir

SRAM_IO[9]_tri_out = TRI(F1_q[1], dpm_ni2f_reg_we_n);
SRAM_IO[9] = BIDIR(SRAM_IO[9]_tri_out);


--SRAM_IO_10 is SRAM_IO_10
--operation mode is bidir

SRAM_IO_10 = SRAM_IO[10];

--SRAM_IO[10] is SRAM_IO[10]
--operation mode is bidir

SRAM_IO[10]_tri_out = TRI(F1_q[2], dpm_ni2f_reg_we_n);
SRAM_IO[10] = BIDIR(SRAM_IO[10]_tri_out);


--SRAM_IO_11 is SRAM_IO_11
--operation mode is bidir

SRAM_IO_11 = SRAM_IO[11];

--SRAM_IO[11] is SRAM_IO[11]
--operation mode is bidir

SRAM_IO[11]_tri_out = TRI(F1_q[3], dpm_ni2f_reg_we_n);
SRAM_IO[11] = BIDIR(SRAM_IO[11]_tri_out);


--SRAM_IO_12 is SRAM_IO_12
--operation mode is bidir

SRAM_IO_12 = SRAM_IO[12];

--SRAM_IO[12] is SRAM_IO[12]
--operation mode is bidir

SRAM_IO[12]_tri_out = TRI(F1_q[4], dpm_ni2f_reg_we_n);
SRAM_IO[12] = BIDIR(SRAM_IO[12]_tri_out);


--SRAM_IO_13 is SRAM_IO_13
--operation mode is bidir

SRAM_IO_13 = SRAM_IO[13];

--SRAM_IO[13] is SRAM_IO[13]
--operation mode is bidir

SRAM_IO[13]_tri_out = TRI(F1_q[5], dpm_ni2f_reg_we_n);
SRAM_IO[13] = BIDIR(SRAM_IO[13]_tri_out);


--SRAM_IO_14 is SRAM_IO_14
--operation mode is bidir

SRAM_IO_14 = SRAM_IO[14];

--SRAM_IO[14] is SRAM_IO[14]
--operation mode is bidir

SRAM_IO[14]_tri_out = TRI(F1_q[6], dpm_ni2f_reg_we_n);
SRAM_IO[14] = BIDIR(SRAM_IO[14]_tri_out);


--SRAM_IO_15 is SRAM_IO_15
--operation mode is bidir

SRAM_IO_15 = SRAM_IO[15];

--SRAM_IO[15] is SRAM_IO[15]
--operation mode is bidir

SRAM_IO[15]_tri_out = TRI(F1_q[7], dpm_ni2f_reg_we_n);
SRAM_IO[15] = BIDIR(SRAM_IO[15]_tri_out);


--SRAM_IO[16] is SRAM_IO[16]
--operation mode is bidir

SRAM_IO[16]_open_drain_out = OPNDRN(!dpm_ni2f_reg_we_n);
SRAM_IO[16] = BIDIR(SRAM_IO[16]_open_drain_out);


--SRAM_IO[17] is SRAM_IO[17]
--operation mode is bidir

SRAM_IO[17]_open_drain_out = OPNDRN(!dpm_ni2f_reg_we_n);
SRAM_IO[17] = BIDIR(SRAM_IO[17]_open_drain_out);


--A1L905 is dpm_ni2f_reg_sreset120~1
--operation mode is normal

A1L905 = !dpm_ni2f_reg_sreset120;


--J1L273 is pci_contr:pci|pci_mt32:pci_mt32_inst|pcimt32_m:mstr|MS_ADR~55
--operation mode is normal

J1L273 = AMPP_FUNCTION(J1_MS_ADR);