C:\MGC\LeoSpec\LS2006a_59\bin\win32\spectrum -file read_top_trap_pci.tcl \ -logfile REPORTS/compile_top_trap_pci.txt ------------------------------------------------- LeonardoSpectrum Level 3 - 2006a.59 (Release Production Release, compiled May 12 2006 at 13:20:39) Copyright 1990-2006 Mentor Graphics. All rights reserved. Portions copyright 1991-2006 Compuware Corporation Checking Security ... Info, Working Directory is now 'J:/angelov/ACEX_designs.svn/ni_sdr_sram' Info, Log file moved to new working directory Info: setting extract_ram to false -- Reading file C:\MGC\LeoSpec\LS2006a_59\\data\standard.vhd for unit standard -- Loading package standard into library std -- Reading vhdl file J:/angelov/ACEX_designs.svn/ni_sdr_sram/SRC/tsr_translate.vhd into library work -- Reading file C:\MGC\LeoSpec\LS2006a_59\\data\std_1164.vhd for unit STD_LOGIC_1164 -- Loading package std_logic_1164 into library IEEE -- Loading entity tsr_translate into library work -- Loading architecture a of tsr_translate into library work -- Reading vhdl file J:/angelov/ACEX_designs.svn/ni_sdr_sram/SRC/decoder.vhd into library work -- Loading entity decoder into library work -- Loading architecture a of decoder into library work "J:/angelov/ACEX_designs.svn/ni_sdr_sram/SRC/decoder.vhd",line 25: Warning, input rdata_rdy is never used. -- Reading vhdl file J:/angelov/ACEX_designs.svn/ni_sdr_sram/SRC/s7segm.vhd into library work -- Searching for SYNOPSYS package STD_LOGIC_ARITH.. -- Reading file C:\MGC\LeoSpec\LS2006a_59\\data\syn_arit.vhd for unit STD_LOGIC_ARITH -- Loading package std_logic_arith into library IEEE -- Searching for SYNOPSYS package STD_LOGIC_UNSIGNED.. -- Reading file C:\MGC\LeoSpec\LS2006a_59\\data\syn_unsi.vhd for unit STD_LOGIC_UNSIGNED -- Loading package STD_LOGIC_UNSIGNED into library IEEE -- Loading entity s7segm into library work -- Loading architecture angel of s7segm into library work -- Reading vhdl file J:/angelov/ACEX_designs.svn/ni_sdr_sram/SRC/dbl7seg.vhd into library work -- Loading entity dbl7seg into library work -- Loading architecture angel of dbl7seg into library work -- Reading vhdl file J:/angelov/ACEX_designs.svn/ni_sdr_sram/SRC/nififo8m.vhd into library work -- Reading file C:\MGC\LeoSpec\LS2006a_59\\lib\lpm_components.vhd for unit lpm_components -- Loading package LPM_COMPONENTS into library lpm -- Loading entity nififo8m into library work -- Loading architecture a of nififo8m into library work -- Reading vhdl file J:/angelov/ACEX_designs.svn/ni_sdr_sram/SRC/ni2fifo.vhd into library work -- Loading entity ni2fifo into library work "J:/angelov/ACEX_designs.svn/ni_sdr_sram/SRC/ni2fifo.vhd",line 55: Info, Enumerated type sm_type with 12 elements encoded as onehot. Encodings for sm_type values value sm_type[11-0] ============================== idle -----------1 fifo_rd1 ----------1- fifo_rd2 ---------1-- sram_A --------1--- sram_Ae -------1---- sram_A1 ------1----- sram_A1e -----1------ sram_D ----1------- sram_De ---1-------- sram_D1 --1--------- sram_D1e -1---------- sram_fin 1----------- -- Loading architecture a of ni2fifo into library work "J:/angelov/ACEX_designs.svn/ni_sdr_sram/SRC/ni2fifo.vhd",line 65: Warning, signal rdempty_s is never used. "J:/angelov/ACEX_designs.svn/ni_sdr_sram/SRC/ni2fifo.vhd",line 65: Warning, signal rdempty_s is never assigned a value. "J:/angelov/ACEX_designs.svn/ni_sdr_sram/SRC/ni2fifo.vhd",line 69: Warning, signal cdata is never used. -- Reading vhdl file J:/angelov/ACEX_designs.svn/ni_sdr_sram/SRC/trap_dpm.vhd into library work -- Loading entity trap_dpm into library work -- Loading architecture a of trap_dpm into library work "J:/angelov/ACEX_designs.svn/ni_sdr_sram/SRC/trap_dpm.vhd",line 138: Warning, signal sel_s is never used. "J:/angelov/ACEX_designs.svn/ni_sdr_sram/SRC/trap_dpm.vhd",line 139: Warning, signal sel_p is never used. -- Reading vhdl file J:/angelov/ACEX_designs.svn/ni_sdr_sram/SRC/top_trap_pci.vhd into library work -- Loading entity top_trap_pci into library work -- Loading architecture a of top_trap_pci into library work "J:/angelov/ACEX_designs.svn/ni_sdr_sram/SRC/top_trap_pci.vhd",line 163: Warning, signal lm_req32n is never assigned a value. "J:/angelov/ACEX_designs.svn/ni_sdr_sram/SRC/top_trap_pci.vhd",line 164: Warning, signal lm_req64n is never used. "J:/angelov/ACEX_designs.svn/ni_sdr_sram/SRC/top_trap_pci.vhd",line 164: Warning, signal lm_req64n is never assigned a value. "J:/angelov/ACEX_designs.svn/ni_sdr_sram/SRC/top_trap_pci.vhd",line 174: Warning, signal l_ldat_ackn is never used. "J:/angelov/ACEX_designs.svn/ni_sdr_sram/SRC/top_trap_pci.vhd",line 174: Warning, signal l_ldat_ackn is never assigned a value. "J:/angelov/ACEX_designs.svn/ni_sdr_sram/SRC/top_trap_pci.vhd",line 183: Warning, signal req64n is never used. "J:/angelov/ACEX_designs.svn/ni_sdr_sram/SRC/top_trap_pci.vhd",line 183: Warning, signal req64n is never assigned a value. "J:/angelov/ACEX_designs.svn/ni_sdr_sram/SRC/top_trap_pci.vhd",line 184: Warning, signal acq64n is never used. "J:/angelov/ACEX_designs.svn/ni_sdr_sram/SRC/top_trap_pci.vhd",line 184: Warning, signal acq64n is never assigned a value. "J:/angelov/ACEX_designs.svn/ni_sdr_sram/SRC/top_trap_pci.vhd",line 185: Warning, signal par64 is never used. "J:/angelov/ACEX_designs.svn/ni_sdr_sram/SRC/top_trap_pci.vhd",line 185: Warning, signal par64 is never assigned a value. "J:/angelov/ACEX_designs.svn/ni_sdr_sram/SRC/top_trap_pci.vhd",line 11: Warning, output pci_reqn is never assigned a value. "J:/angelov/ACEX_designs.svn/ni_sdr_sram/SRC/top_trap_pci.vhd",line 22: Warning, input pci_lockn is never used. "J:/angelov/ACEX_designs.svn/ni_sdr_sram/SRC/top_trap_pci.vhd",line 27: Warning, input LVDS_in is never used. "J:/angelov/ACEX_designs.svn/ni_sdr_sram/SRC/top_trap_pci.vhd",line 37: Warning, input CLK50M is never used. -- Compiling root entity top_trap_pci(a) "J:/angelov/ACEX_designs.svn/ni_sdr_sram/SRC/top_trap_pci.vhd",line 151: Warning, component GLOBAL has no visible entity binding. -- Compiling entity dbl7seg(angel) -- Compiling entity s7segm(angel) "J:/angelov/ACEX_designs.svn/ni_sdr_sram/SRC/top_trap_pci.vhd",line 156: Warning, component LCELL has no visible entity binding. -- Compiling entity trap_dpm(a) "J:/angelov/ACEX_designs.svn/ni_sdr_sram/SRC/trap_dpm.vhd",line 108: Warning, component lpm_counter has no visible entity binding. -- Compiling entity decoder_32(a) -- Compiling entity tsr_translate(a) -- Compiling entity ni2fifo(a) -- Compiling entity nififo8m_11_8(a) "J:/angelov/ACEX_designs.svn/ni_sdr_sram/SRC/nififo8m.vhd",line 69: Info, others clause is never selected for synthesis. "J:/angelov/ACEX_designs.svn/ni_sdr_sram/SRC/nififo8m.vhd",line 27: Warning, component dpram has no visible entity binding. "J:/angelov/ACEX_designs.svn/ni_sdr_sram/SRC/ni2fifo.vhd",line 234: Info, others clause is never selected for synthesis. "J:/angelov/ACEX_designs.svn/ni_sdr_sram/SRC/ni2fifo.vhd",line 307: Info, others clause is never selected for synthesis. "J:/angelov/ACEX_designs.svn/ni_sdr_sram/SRC/top_trap_pci.vhd",line 60: Warning, component pci_contr has no visible entity binding. "J:/angelov/ACEX_designs.svn/ni_sdr_sram/SRC/top_trap_pci.vhd",line 319: Warning, Multiple drivers on lm_rdyn : also line 320. -- Boundary optimization. -- Boundary optimization. -- Start pre-optimization for design .work.s7segm.angel -- Start pre-optimization for design .work.dbl7seg.angel_unfold_1539 -- Start pre-optimization for design .work.decoder_32.a_unfold_994 -- Start pre-optimization for design .work.nififo8m_11_8.a_unfold_1083 "J:/angelov/ACEX_designs.svn/ni_sdr_sram/SRC/nififo8m.vhd", line 72:Info, Inferred counter instance 'wpointer' of type 'counter_up_cnt_en_aclear_clock_11' "J:/angelov/ACEX_designs.svn/ni_sdr_sram/SRC/nififo8m.vhd", line 79:Info, Inferred counter instance 'rpointer' of type 'counter_up_cnt_en_aclear_clock_11' -- Start pre-optimization for design .work.nififo8m_11_8.a "J:/angelov/ACEX_designs.svn/ni_sdr_sram/SRC/nififo8m.vhd", line 72:Info, Inferred counter instance 'wpointer' of type 'counter_up_cnt_en_aclear_clock_11' "J:/angelov/ACEX_designs.svn/ni_sdr_sram/SRC/nififo8m.vhd", line 79:Info, Inferred counter instance 'rpointer' of type 'counter_up_cnt_en_aclear_clock_11' -- Start pre-optimization for design .work.ni2fifo.a_unfold_1029 "J:/angelov/ACEX_designs.svn/ni_sdr_sram/SRC/ni2fifo.vhd", line 117:Info, Inferred counter instance 'des_valid_data_cnt' of type 'counter_up_cnt_en_aclear_clock_32' "J:/angelov/ACEX_designs.svn/ni_sdr_sram/SRC/ni2fifo.vhd", line 120:Info, Inferred counter instance 'des_dv1_err1_cnt' of type 'counter_up_cnt_en_aclear_clock_32' "J:/angelov/ACEX_designs.svn/ni_sdr_sram/SRC/ni2fifo.vhd", line 254:Info, Inferred counter instance 'wcounter' of type 'counter_up_cnt_en_sclear_clock_18' "J:/angelov/ACEX_designs.svn/ni_sdr_sram/SRC/ni2fifo.vhd", line 257:Info, Inferred counter instance 'rcounter' of type 'counter_up_cnt_en_sclear_clock_6' -- Start pre-optimization for design .work.trap_dpm.a_unfold_1316 -- Start pre-optimization for design .work.top_trap_pci.a -- Start pre-optimization for design .work.s7segm.angel -- Start pre-optimization for design .work.dbl7seg.angel_unfold_1539 -- Start pre-optimization for design .work.decoder_32.a_unfold_994 -- Start pre-optimization for design .work.nififo8m_11_8.a_unfold_1083 -- Start pre-optimization for design .work.nififo8m_11_8.a -- Start pre-optimization for design .work.ni2fifo.a_unfold_1029 -- Start pre-optimization for design .work.trap_dpm.a_unfold_1316 -- Start pre-optimization for design .work.top_trap_pci.a Info: setting part to EP1K100QC208 Info: setting process to 1 Reading library file `C:\MGC\LeoSpec\LS2006a_59\\lib\acex1.syn`... Library version = 4.5 Delays assume: Process=1 Info: setting encoding to auto Using default wire table: STD-1 -- Start optimization for design .work.top_trap_pci.a Using default wire table: STD-1 Warning, port pci_reqn is connected to a disabled tristate, possibly unconnected port in design. est est Pass LCs Delay DFFs TRIs PIs POs --CPU-- min:sec 1 565 10 158 0 23 105 00:04 2 560 10 158 0 23 105 00:04 3 595 12 158 0 23 105 00:05 4 611 11 158 0 23 105 00:04 Info, Pass 1 was selected as best. Info: setting opt_best_result to 5666.950000 Info: setting opt_best_pass to 1 Using default wire table: STD-1 -- Start timing optimization for design .work.top_trap_pci.a No critical paths to optimize at this level AutoWrite args are : NETLIST/top_trap_pci.edf -- Applying renaming rule 'ALTERA' to database Warning, Renaming will cause your database to change -- Calling set_altera_eqn to set up writing Equations -- Writing file NETLIST/top_trap_pci.edf Info, Writing batch file 'NETLIST/top_trap_pci.tcl' Info: setting quartus_exec_path to F:\altera\quartus40/bin Using default wire table: STD-1