LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;

entity tsr_translate is
port(
        lt_tsr          :       in  STD_LOGIC_VECTOR(11 downto 0);

        bar_hit         :       out STD_LOGIC_VECTOR(5 downto 0);
        exp_rom_hit     :       out STD_LOGIC;
        trans64         :       out STD_LOGIC;
        targ_access     :       out STD_LOGIC;
        burst_trans     :       out STD_LOGIC;
        pxfr            :       out STD_LOGIC;
        dac             :       out STD_LOGIC
        );
end tsr_translate;

architecture a of tsr_translate is
begin
        bar_hit         <=      lt_tsr(5 downto 0);
        exp_rom_hit     <=      lt_tsr(6);
        trans64         <=      lt_tsr(7);
        targ_access     <=      lt_tsr(8);
        burst_trans     <=      lt_tsr(9);
        pxfr            <=      lt_tsr(10);
        dac             <=      lt_tsr(11);
end a;