LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; entity top_trap_pci is port ( pci_clk : IN STD_LOGIC ; pci_rstn : IN STD_LOGIC ; pci_gntn : IN STD_LOGIC ; pci_idsel : IN STD_LOGIC ; pci_intan : OUT STD_LOGIC ; pci_reqn : OUT STD_LOGIC ; pci_serrn : OUT STD_LOGIC ; pci_framen : INOUT STD_LOGIC ; pci_irdyn : INOUT STD_LOGIC ; pci_devseln : INOUT STD_LOGIC ; pci_trdyn : INOUT STD_LOGIC ; pci_stopn : INOUT STD_LOGIC ; pci_ad : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0); pci_cben : INOUT STD_LOGIC_VECTOR ( 3 DOWNTO 0); pci_par : INOUT STD_LOGIC ; pci_perrn : INOUT STD_LOGIC ; pci_lockn : IN STD_LOGIC ; -- SCSN R7S : out std_logic_vector(1 to 7); R7S_mux : out std_logic; LVDS_in : in std_logic_vector(3 downto 0); LVDS_out : out std_logic_vector(3 downto 0); LED_GRN : out std_logic; LED_RED : out std_logic; -- mouse & keyboard PS/2 MCLK : out std_logic; KCLK : out std_logic; KDAT : out std_logic; CLK50M : in std_logic; DES_CLK : in std_logic; -- continuously running DES_EN : in std_logic; -- used as vaild data DES_ER : in std_logic; -- used as data error DES_DATA : in std_logic_vector(15 downto 0); -- ni in port LVDS_EN : out std_logic; -- SRAM SRAM_CLK : OUT STD_LOGIC; SRAM_BW1n : OUT STD_LOGIC; SRAM_BW2n : OUT STD_LOGIC; SRAM_OEn : OUT STD_LOGIC; SRAM_CEn : OUT STD_LOGIC; SRAM_AD : OUT STD_LOGIC_VECTOR(17 downto 0); SRAM_IO : INOUT STD_LOGIC_VECTOR(17 downto 0) ); end top_trap_pci; -------------------------------------------------------------------------------------------------------- -- ARCHITECTURE -------------------------------------------------------------------------------------------------------- architecture a of top_trap_pci is component pci_contr PORT ( clk : IN STD_LOGIC; rstn : IN STD_LOGIC; gntn : IN STD_LOGIC; idsel : IN STD_LOGIC; l_adi : IN STD_LOGIC_VECTOR (31 DOWNTO 0); l_cbeni : IN STD_LOGIC_VECTOR (3 DOWNTO 0); lm_req32n : IN STD_LOGIC; lm_lastn : IN STD_LOGIC; lm_rdyn : IN STD_LOGIC; lt_rdyn : IN STD_LOGIC; lt_abortn : IN STD_LOGIC; lt_discn : IN STD_LOGIC; lirqn : IN STD_LOGIC; framen : INOUT STD_LOGIC; irdyn : INOUT STD_LOGIC; devseln : INOUT STD_LOGIC; trdyn : INOUT STD_LOGIC; stopn : INOUT STD_LOGIC; intan : OUT STD_LOGIC; reqn : OUT STD_LOGIC; serrn : OUT STD_LOGIC; l_adro : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); l_dato : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); l_beno : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); l_cmdo : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); lm_adr_ackn : OUT STD_LOGIC; lm_ackn : OUT STD_LOGIC; lm_dxfrn : OUT STD_LOGIC; lm_tsr : OUT STD_LOGIC_VECTOR (9 DOWNTO 0); lt_framen : OUT STD_LOGIC; lt_ackn : OUT STD_LOGIC; lt_dxfrn : OUT STD_LOGIC; lt_tsr : OUT STD_LOGIC_VECTOR (11 DOWNTO 0); cmd_reg : OUT STD_LOGIC_VECTOR (5 DOWNTO 0); stat_reg : OUT STD_LOGIC_VECTOR (5 DOWNTO 0); cache : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); ad : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0); cben : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0); par : INOUT STD_LOGIC; perrn : INOUT STD_LOGIC ); end component; component dbl7seg IS PORT( CL, CR : IN STD_LOGIC_VECTOR(3 downto 0); -- code for left/right mx : IN STD_LOGIC; -- 100Hz dis : IN STD_LOGIC; -- disable outputs (switch off) mx_out : OUT STD_LOGIC; Q : OUT STD_LOGIC_VECTOR(1 to 7) -- output to 7segm ind. ); END component; component trap_dpm is port ( clk_pci : in std_logic; reset_n : in std_logic; -- the bus interface data_in : in std_logic_vector(31 downto 0); addr_in : in std_logic_vector(31 downto 0); LT_TSR : in std_logic_vector(11 downto 0); LT_CMD : in std_logic_vector( 3 downto 0); LT_ACQ_n : in std_logic; LT_RDY_n : out std_logic; data_out : out std_logic_vector(31 downto 0); dis_clk : out std_logic; -- trap des_clk : in std_logic; -- data clock des_en : in std_logic; -- data valid des_er : in std_logic; -- data error des_data : in std_logic_vector(15 downto 0); -- data SRAM_CLK : OUT STD_LOGIC; SRAM_WEn : OUT STD_LOGIC; SRAM_OEn : OUT STD_LOGIC; SRAM_CEn : OUT STD_LOGIC; SRAM_AD : OUT STD_LOGIC_VECTOR(17 downto 0); SRAM_Q : in std_logic_vector(15 downto 0); SRAM_D : out std_logic_vector(15 downto 0); not_empty : out std_logic; ds_en_reg : out std_logic; res_reset_n : out std_logic; data_LED : out std_logic_vector( 9 downto 0) ); end component; COMPONENT GLOBAL PORT (a_in : IN STD_LOGIC; a_out: OUT STD_LOGIC); END COMPONENT; COMPONENT LCELL PORT (IN1 : IN STD_LOGIC; Y : OUT STD_LOGIC); END COMPONENT; signal l_cbeni : STD_LOGIC_VECTOR ( 3 DOWNTO 0); signal l_adi : STD_LOGIC_VECTOR (31 DOWNTO 0); signal lm_req32n : STD_LOGIC ; signal lm_req64n : STD_LOGIC ; signal lm_lastn : STD_LOGIC ; signal lm_rdyn : STD_LOGIC ; signal lt_rdyn : STD_LOGIC ; signal lt_abortn : STD_LOGIC ; signal lt_discn : STD_LOGIC ; signal lirqn : STD_LOGIC ; signal l_adro : STD_LOGIC_VECTOR (31 DOWNTO 0); signal l_dato : STD_LOGIC_VECTOR (31 DOWNTO 0); signal l_cmdo : STD_LOGIC_VECTOR ( 3 DOWNTO 0); signal l_ldat_ackn : std_logic ; signal lt_ackn : STD_LOGIC ; signal lt_tsr : STD_LOGIC_VECTOR (11 DOWNTO 0); signal dseg : std_logic_vector(7 downto 0); signal slow_clk : std_logic; signal des_clk_i : std_logic; signal clk_pci : std_logic; signal req64n : std_logic; signal acq64n : std_logic; signal par64 : std_logic; signal data_LED : std_logic_vector( 9 downto 0); signal full : std_logic; signal des_clk_n : std_logic; signal SRAM_WEn : std_logic; signal SRAM_CLK_i : std_logic; signal SRAM_OEn_i : std_logic; signal SRAM_CEn_i : std_logic; signal Q_SRAM : std_logic_vector(15 downto 0); signal D_SRAM : std_logic_vector(15 downto 0); signal DES_DATA_i : std_logic_vector(15 downto 0); signal DES_EN_i : std_logic; signal DES_ER_i : std_logic; signal ds_en_reg : std_logic; begin LVDS_EN <= '1'; LVDS_OUT <= (others => '0'); SRAM_IO <= "00" & D_SRAM when SRAM_WEn='0' else (others => 'Z'); Q_SRAM <= SRAM_IO(Q_SRAM'range); SRAM_BW1n <= SRAM_WEn; SRAM_BW2n <= SRAM_WEn; pclk: GLOBAL PORT map(a_in => pci_clk, a_out => clk_pci ); dseg <= data_LED(dseg'range); LED_GRN <= not full; LED_RED <= full; KDAT <= full; -- KCLK <= not full; KCLK <= SRAM_WEn; MCLK <= ds_en_reg; sg: dbl7seg PORT map( CL => dseg(7 downto 4), CR => dseg(3 downto 0), mx => slow_clk, dis => '0', mx_out => R7S_mux, Q => R7S); lcst: LCELL PORT map(IN1 => des_clk_n, Y => des_clk_i); des_clk_n <= not DES_CLK; DES_EN_i <= DES_EN; DES_ER_i <= DES_ER; DES_DATA_i <= DES_DATA; dpm: trap_dpm port map( clk_pci => clk_pci, reset_n => pci_rstn, -- the bus interface data_in => l_dato , addr_in => l_adro , LT_TSR => lt_tsr , LT_CMD => l_cmdo , LT_ACQ_n => lt_ackn , LT_RDY_n => lt_rdyn , data_out => l_adi , dis_clk => slow_clk, -- trap des_clk => DES_CLK_i, des_en => DES_EN_i, des_er => DES_ER_i, des_data => DES_DATA_i, not_empty => full, ds_en_reg => ds_en_reg, SRAM_CLK => SRAM_CLK_i, SRAM_WEn => SRAM_WEn, SRAM_OEn => SRAM_OEn_i, SRAM_CEn => SRAM_CEn_i, SRAM_AD => SRAM_AD, SRAM_Q => Q_SRAM, SRAM_D => D_SRAM, res_reset_n => open, data_LED => data_LED ); SRAM_CLK <= SRAM_CLK_i; SRAM_OEn <= SRAM_OEn_i; SRAM_CEn <= SRAM_CEn_i; pci: pci_contr PORT map( clk => clk_pci, rstn => pci_rstn, gntn => pci_gntn, l_cbeni => l_cbeni, idsel => pci_idsel, l_adi => l_adi, lm_req32n => lm_req32n, lm_lastn => lm_lastn, lm_rdyn => lm_rdyn, lt_rdyn => lt_rdyn, lt_abortn => lt_abortn, lt_discn => lt_discn, lirqn => lirqn, intan => pci_intan, serrn => pci_serrn, l_adro => l_adro, l_dato => l_dato, l_beno => open, l_cmdo => l_cmdo, lt_framen => open, lt_ackn => lt_ackn, lt_dxfrn => open, lt_tsr => lt_tsr, cmd_reg => open, stat_reg => open, framen => pci_framen, irdyn => pci_irdyn, devseln => pci_devseln, trdyn => pci_trdyn, stopn => pci_stopn, ad => pci_AD, cben => pci_CBEn, par => pci_par, perrn => pci_perrn ); l_cbeni <= (others => '0'); lm_lastn <= '1'; lm_rdyn <= '1'; lm_rdyn <= '1'; lt_abortn <= '1'; lt_discn <= '1'; lirqn <= '1'; end;