library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

LIBRARY lpm;
USE lpm.lpm_components.all;

ENTITY nififo8m is
generic (Na : Integer := 11; Nd : Integer := 8);
        PORT
        (
                data            : IN STD_LOGIC_VECTOR (Nd-1 DOWNTO 0);
                wrreq           : IN STD_LOGIC ;
                rdreq           : IN STD_LOGIC ;
                clk             : IN STD_LOGIC ;
                aclr            : IN STD_LOGIC  := '0';
                q               : OUT STD_LOGIC_VECTOR (Nd-1 DOWNTO 0);
                rdempty         : OUT STD_LOGIC
        );
end nififo8m;



architecture a of nififo8m is

component dpram IS
        PORT
        (
                data            : IN  STD_LOGIC_VECTOR ( 7 DOWNTO 0);
                wraddress       : IN  STD_LOGIC_VECTOR (10 DOWNTO 0);
                rdaddress       : IN  STD_LOGIC_VECTOR (10 DOWNTO 0);
                wren            : IN  STD_LOGIC  := '1';
                clock           : IN  STD_LOGIC ;
                q               : OUT STD_LOGIC_VECTOR ( 7 DOWNTO 0)
        );
END component;

signal almost_full  : std_logic_vector(Na-1 downto 0);
signal almost_empty : std_logic_vector(Na-1 downto 0);
signal wpointer     : std_logic_vector(Na-1 downto 0);
signal rpointer     : std_logic_vector(Na-1 downto 0);
signal nwords       : std_logic_vector(Na-1 downto 0);

signal fifo_cmd     : std_logic_vector(   1 downto 0);
signal fifo_status  : std_logic_vector(   1 downto 0);

signal fifo_full    : std_logic;
signal fifo_empty   : std_logic;
signal wren         : std_logic;


begin

    almost_full  <= (0 => '0', others => '1');
    almost_empty <= (0 => '1', others => '0');

    fifo_cmd <= wrreq & rdreq;
    fifo_status <= fifo_full & fifo_empty;
    process(clk, aclr)
    begin
        if aclr = '1' then
             wpointer <= (others => '0');
             rpointer <= (others => '0');
             nwords   <= (others => '0');
             fifo_full  <= '0';
             fifo_empty <= '1';
        elsif clk'event and clk='1' then
                case fifo_cmd is
                when "10"   => -- write
                    if fifo_full='0' then
                                        wpointer <= wpointer+1;
                                        if nwords = almost_full then fifo_full <= '1'; end if;
                                        nwords   <= nwords  +1;
                                        fifo_empty <= '0';
                                      end if;
                when "01"   => -- read
                    if fifo_empty='0' then
                                        rpointer <= rpointer+1;
                                        if nwords = almost_empty then fifo_empty <= '1'; end if;
                                        nwords   <= nwords  -1;
                                        fifo_full <= '0';
                                       end if;
                when "11"   => -- read & write
                    case fifo_status is
                    when "00" => -- not full, not empty
                                        wpointer <= wpointer+1;
                                        rpointer <= rpointer+1;
                    when "10" => --     full, not empty
                                        nwords   <= nwords  -1;
                                        fifo_full <= '0';
                    when "01" => -- not full,     empty
                                        nwords     <= nwords  +1;
                                        fifo_empty <= '0';
                    when others => NULL; -- should not happen!!!
                    end case;
                when "00"   => NULL;
                when others => wpointer <= (others => '-');
                               rpointer <= (others => '-');
                               nwords   <= (others => '-');
                end case;
        end if;
    end process;

--    wren     <= wrreq and not fifo_full;
    wren     <= wrreq;

dpr: dpram
        PORT map
        (
                data            => data,
                wraddress       => wpointer,
                rdaddress       => rpointer,
                wren            => wren,
                clock           => clk,
                q               => q
        );

    rdempty <= fifo_empty;

end;