--E9_q[2] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|lpm_counter:devsel_cntr|alt_counter_f10ke:wysi_counter|q[2]
--operation mode is clrb_cntr

E9_q[2] = AMPP_FUNCTION(W1_$00065, W1L413, ~GND, A1L034, pci_rstn, GLOBAL(pci_clk), E9L5);


--E9_q[1] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|lpm_counter:devsel_cntr|alt_counter_f10ke:wysi_counter|q[1]
--operation mode is clrb_cntr

E9_q[1] = AMPP_FUNCTION(W1_$00065, W1L413, ~GND, A1L034, pci_rstn, GLOBAL(pci_clk), E9L3);

--E9L5 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|lpm_counter:devsel_cntr|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT
--operation mode is clrb_cntr

E9L5 = AMPP_FUNCTION(E9L3);


--E9_q[0] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|lpm_counter:devsel_cntr|alt_counter_f10ke:wysi_counter|q[0]
--operation mode is clrb_cntr

E9_q[0] = AMPP_FUNCTION(W1_$00065, W1L413, ~GND, A1L034, pci_rstn, GLOBAL(pci_clk));

--E9L3 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|lpm_counter:devsel_cntr|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT
--operation mode is clrb_cntr

E9L3 = AMPP_FUNCTION();


--E01_q[7] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[7]
--operation mode is clrb_cntr

E01_q[7] = AMPP_FUNCTION(W1_latcntr_cnt_en, W1_$00061, BB1_lat_tmr_reg[4], W1L413, pci_rstn, GLOBAL(pci_clk), E01L51);


--E01_q[6] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[6]
--operation mode is clrb_cntr

E01_q[6] = AMPP_FUNCTION(W1_latcntr_cnt_en, W1_$00061, BB1_lat_tmr_reg[3], W1L413, pci_rstn, GLOBAL(pci_clk), E01L31);

--E01L51 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|counter_cell[6]~COUT
--operation mode is clrb_cntr

E01L51 = AMPP_FUNCTION(E01L31);


--E01_q[5] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[5]
--operation mode is clrb_cntr

E01_q[5] = AMPP_FUNCTION(W1_latcntr_cnt_en, W1_$00061, BB1_lat_tmr_reg[2], W1L413, pci_rstn, GLOBAL(pci_clk), E01L11);

--E01L31 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|counter_cell[5]~COUT
--operation mode is clrb_cntr

E01L31 = AMPP_FUNCTION(E01L11);


--E01_q[4] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[4]
--operation mode is clrb_cntr

E01_q[4] = AMPP_FUNCTION(W1_latcntr_cnt_en, W1_$00061, BB1_lat_tmr_reg[1], W1L413, pci_rstn, GLOBAL(pci_clk), E01L9);

--E01L11 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|counter_cell[4]~COUT
--operation mode is clrb_cntr

E01L11 = AMPP_FUNCTION(E01L9);


--E01_q[3] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[3]
--operation mode is clrb_cntr

E01_q[3] = AMPP_FUNCTION(W1_latcntr_cnt_en, W1_$00061, BB1_lat_tmr_reg[0], W1L413, pci_rstn, GLOBAL(pci_clk), E01L7);

--E01L9 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT
--operation mode is clrb_cntr

E01L9 = AMPP_FUNCTION(E01L7);


--E01_q[2] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[2]
--operation mode is clrb_cntr

E01_q[2] = AMPP_FUNCTION(W1_latcntr_cnt_en, W1_$00061, ~GND, W1L413, pci_rstn, GLOBAL(pci_clk), E01L5);

--E01L7 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT
--operation mode is clrb_cntr

E01L7 = AMPP_FUNCTION(E01L5);


--E01_q[1] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[1]
--operation mode is clrb_cntr

E01_q[1] = AMPP_FUNCTION(W1_latcntr_cnt_en, W1_$00061, ~GND, W1L413, pci_rstn, GLOBAL(pci_clk), E01L3);

--E01L5 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT
--operation mode is clrb_cntr

E01L5 = AMPP_FUNCTION(E01L3);


--E01_q[0] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|q[0]
--operation mode is clrb_cntr

E01_q[0] = AMPP_FUNCTION(W1_latcntr_cnt_en, W1_$00061, ~GND, W1L413, pci_rstn, GLOBAL(pci_clk));

--E01L3 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|lpm_counter:latcntr|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT
--operation mode is clrb_cntr

E01L3 = AMPP_FUNCTION();


--E8_q[10] is lpm_counter:dpm_ni2f_tout_ix8|alt_counter_f10ke:wysi_counter|q[10]
--operation mode is clrb_cntr

E8_q[10]_lut_out = (E8_q[10] $ (ix2002_lc & E8L12)) & E8L32;
E8_q[10] = DFFEA(E8_q[10]_lut_out, CLK50M, , , ix2002_lc, , );


--E8_q[9] is lpm_counter:dpm_ni2f_tout_ix8|alt_counter_f10ke:wysi_counter|q[9]
--operation mode is clrb_cntr

E8_q[9]_lut_out = (E8_q[9] $ (ix2002_lc & E8L91)) & E8L32;
E8_q[9] = DFFEA(E8_q[9]_lut_out, CLK50M, , , ix2002_lc, , );

--E8L12 is lpm_counter:dpm_ni2f_tout_ix8|alt_counter_f10ke:wysi_counter|counter_cell[9]~COUT
--operation mode is clrb_cntr

E8L12 = CARRY(E8_q[9] & E8L91);


--E8_q[8] is lpm_counter:dpm_ni2f_tout_ix8|alt_counter_f10ke:wysi_counter|q[8]
--operation mode is clrb_cntr

E8_q[8]_lut_out = (E8_q[8] $ (ix2002_lc & E8L71)) & E8L32;
E8_q[8] = DFFEA(E8_q[8]_lut_out, CLK50M, , , ix2002_lc, , );

--E8L91 is lpm_counter:dpm_ni2f_tout_ix8|alt_counter_f10ke:wysi_counter|counter_cell[8]~COUT
--operation mode is clrb_cntr

E8L91 = CARRY(E8_q[8] & E8L71);


--E8_q[7] is lpm_counter:dpm_ni2f_tout_ix8|alt_counter_f10ke:wysi_counter|q[7]
--operation mode is clrb_cntr

E8_q[7]_lut_out = (E8_q[7] $ (ix2002_lc & E8L51)) & E8L32;
E8_q[7] = DFFEA(E8_q[7]_lut_out, CLK50M, , , ix2002_lc, , );

--E8L71 is lpm_counter:dpm_ni2f_tout_ix8|alt_counter_f10ke:wysi_counter|counter_cell[7]~COUT
--operation mode is clrb_cntr

E8L71 = CARRY(E8_q[7] & E8L51);


--E8_q[6] is lpm_counter:dpm_ni2f_tout_ix8|alt_counter_f10ke:wysi_counter|q[6]
--operation mode is clrb_cntr

E8_q[6]_lut_out = (E8_q[6] $ (ix2002_lc & E8L31)) & E8L32;
E8_q[6] = DFFEA(E8_q[6]_lut_out, CLK50M, , , ix2002_lc, , );

--E8L51 is lpm_counter:dpm_ni2f_tout_ix8|alt_counter_f10ke:wysi_counter|counter_cell[6]~COUT
--operation mode is clrb_cntr

E8L51 = CARRY(E8_q[6] & E8L31);


--E8_q[5] is lpm_counter:dpm_ni2f_tout_ix8|alt_counter_f10ke:wysi_counter|q[5]
--operation mode is clrb_cntr

E8_q[5]_lut_out = (E8_q[5] $ (ix2002_lc & E8L11)) & E8L32;
E8_q[5] = DFFEA(E8_q[5]_lut_out, CLK50M, , , ix2002_lc, , );

--E8L31 is lpm_counter:dpm_ni2f_tout_ix8|alt_counter_f10ke:wysi_counter|counter_cell[5]~COUT
--operation mode is clrb_cntr

E8L31 = CARRY(E8_q[5] & E8L11);


--E8_q[4] is lpm_counter:dpm_ni2f_tout_ix8|alt_counter_f10ke:wysi_counter|q[4]
--operation mode is clrb_cntr

E8_q[4]_lut_out = (E8_q[4] $ (ix2002_lc & E8L9)) & E8L32;
E8_q[4] = DFFEA(E8_q[4]_lut_out, CLK50M, , , ix2002_lc, , );

--E8L11 is lpm_counter:dpm_ni2f_tout_ix8|alt_counter_f10ke:wysi_counter|counter_cell[4]~COUT
--operation mode is clrb_cntr

E8L11 = CARRY(E8_q[4] & E8L9);


--E8_q[3] is lpm_counter:dpm_ni2f_tout_ix8|alt_counter_f10ke:wysi_counter|q[3]
--operation mode is clrb_cntr

E8_q[3]_lut_out = (E8_q[3] $ (ix2002_lc & E8L7)) & E8L32;
E8_q[3] = DFFEA(E8_q[3]_lut_out, CLK50M, , , ix2002_lc, , );

--E8L9 is lpm_counter:dpm_ni2f_tout_ix8|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT
--operation mode is clrb_cntr

E8L9 = CARRY(E8_q[3] & E8L7);


--E8_q[2] is lpm_counter:dpm_ni2f_tout_ix8|alt_counter_f10ke:wysi_counter|q[2]
--operation mode is clrb_cntr

E8_q[2]_lut_out = (E8_q[2] $ (ix2002_lc & E8L5)) & E8L32;
E8_q[2] = DFFEA(E8_q[2]_lut_out, CLK50M, , , ix2002_lc, , );

--E8L7 is lpm_counter:dpm_ni2f_tout_ix8|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT
--operation mode is clrb_cntr

E8L7 = CARRY(E8_q[2] & E8L5);


--E8_q[1] is lpm_counter:dpm_ni2f_tout_ix8|alt_counter_f10ke:wysi_counter|q[1]
--operation mode is clrb_cntr

E8_q[1]_lut_out = (E8_q[1] $ (ix2002_lc & E8L3)) & E8L32;
E8_q[1] = DFFEA(E8_q[1]_lut_out, CLK50M, , , ix2002_lc, , );

--E8L5 is lpm_counter:dpm_ni2f_tout_ix8|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT
--operation mode is clrb_cntr

E8L5 = CARRY(E8_q[1] & E8L3);


--E8_q[0] is lpm_counter:dpm_ni2f_tout_ix8|alt_counter_f10ke:wysi_counter|q[0]
--operation mode is clrb_cntr

E8_q[0]_lut_out = (ix2002_lc $ E8_q[0]) & E8L32;
E8_q[0] = DFFEA(E8_q[0]_lut_out, CLK50M, , , ix2002_lc, , );

--E8L3 is lpm_counter:dpm_ni2f_tout_ix8|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT
--operation mode is clrb_cntr

E8L3 = CARRY(E8_q[0]);


--E7_q[17] is lpm_counter:dpm_ni2f_naddr_ix7|alt_counter_f10ke:wysi_counter|q[17]
--operation mode is clrb_cntr

E7_q[17]_lut_out = (E7_q[17] $ (dpm_ni2f_reg_sm_2 & E7L53)) & A1L931;
E7_q[17] = DFFEA(E7_q[17]_lut_out, CLK50M, , , , , );


--E7_q[16] is lpm_counter:dpm_ni2f_naddr_ix7|alt_counter_f10ke:wysi_counter|q[16]
--operation mode is clrb_cntr

E7_q[16]_lut_out = (E7_q[16] $ (dpm_ni2f_reg_sm_2 & E7L33)) & A1L931;
E7_q[16] = DFFEA(E7_q[16]_lut_out, CLK50M, , , , , );

--E7L53 is lpm_counter:dpm_ni2f_naddr_ix7|alt_counter_f10ke:wysi_counter|counter_cell[16]~COUT
--operation mode is clrb_cntr

E7L53 = CARRY(E7_q[16] & E7L33);


--E7_q[15] is lpm_counter:dpm_ni2f_naddr_ix7|alt_counter_f10ke:wysi_counter|q[15]
--operation mode is clrb_cntr

E7_q[15]_lut_out = (E7_q[15] $ (dpm_ni2f_reg_sm_2 & E7L13)) & A1L931;
E7_q[15] = DFFEA(E7_q[15]_lut_out, CLK50M, , , , , );

--E7L33 is lpm_counter:dpm_ni2f_naddr_ix7|alt_counter_f10ke:wysi_counter|counter_cell[15]~COUT
--operation mode is clrb_cntr

E7L33 = CARRY(E7_q[15] & E7L13);


--E7_q[14] is lpm_counter:dpm_ni2f_naddr_ix7|alt_counter_f10ke:wysi_counter|q[14]
--operation mode is clrb_cntr

E7_q[14]_lut_out = (E7_q[14] $ (dpm_ni2f_reg_sm_2 & E7L92)) & A1L931;
E7_q[14] = DFFEA(E7_q[14]_lut_out, CLK50M, , , , , );

--E7L13 is lpm_counter:dpm_ni2f_naddr_ix7|alt_counter_f10ke:wysi_counter|counter_cell[14]~COUT
--operation mode is clrb_cntr

E7L13 = CARRY(E7_q[14] & E7L92);


--E7_q[13] is lpm_counter:dpm_ni2f_naddr_ix7|alt_counter_f10ke:wysi_counter|q[13]
--operation mode is clrb_cntr

E7_q[13]_lut_out = (E7_q[13] $ (dpm_ni2f_reg_sm_2 & E7L72)) & A1L931;
E7_q[13] = DFFEA(E7_q[13]_lut_out, CLK50M, , , , , );

--E7L92 is lpm_counter:dpm_ni2f_naddr_ix7|alt_counter_f10ke:wysi_counter|counter_cell[13]~COUT
--operation mode is clrb_cntr

E7L92 = CARRY(E7_q[13] & E7L72);


--E7_q[12] is lpm_counter:dpm_ni2f_naddr_ix7|alt_counter_f10ke:wysi_counter|q[12]
--operation mode is clrb_cntr

E7_q[12]_lut_out = (E7_q[12] $ (dpm_ni2f_reg_sm_2 & E7L52)) & A1L931;
E7_q[12] = DFFEA(E7_q[12]_lut_out, CLK50M, , , , , );

--E7L72 is lpm_counter:dpm_ni2f_naddr_ix7|alt_counter_f10ke:wysi_counter|counter_cell[12]~COUT
--operation mode is clrb_cntr

E7L72 = CARRY(E7_q[12] & E7L52);


--E7_q[11] is lpm_counter:dpm_ni2f_naddr_ix7|alt_counter_f10ke:wysi_counter|q[11]
--operation mode is clrb_cntr

E7_q[11]_lut_out = (E7_q[11] $ (dpm_ni2f_reg_sm_2 & E7L32)) & A1L931;
E7_q[11] = DFFEA(E7_q[11]_lut_out, CLK50M, , , , , );

--E7L52 is lpm_counter:dpm_ni2f_naddr_ix7|alt_counter_f10ke:wysi_counter|counter_cell[11]~COUT
--operation mode is clrb_cntr

E7L52 = CARRY(E7_q[11] & E7L32);


--E7_q[10] is lpm_counter:dpm_ni2f_naddr_ix7|alt_counter_f10ke:wysi_counter|q[10]
--operation mode is clrb_cntr

E7_q[10]_lut_out = (E7_q[10] $ (dpm_ni2f_reg_sm_2 & E7L12)) & A1L931;
E7_q[10] = DFFEA(E7_q[10]_lut_out, CLK50M, , , , , );

--E7L32 is lpm_counter:dpm_ni2f_naddr_ix7|alt_counter_f10ke:wysi_counter|counter_cell[10]~COUT
--operation mode is clrb_cntr

E7L32 = CARRY(E7_q[10] & E7L12);


--E7_q[9] is lpm_counter:dpm_ni2f_naddr_ix7|alt_counter_f10ke:wysi_counter|q[9]
--operation mode is clrb_cntr

E7_q[9]_lut_out = (E7_q[9] $ (dpm_ni2f_reg_sm_2 & E7L91)) & A1L931;
E7_q[9] = DFFEA(E7_q[9]_lut_out, CLK50M, , , , , );

--E7L12 is lpm_counter:dpm_ni2f_naddr_ix7|alt_counter_f10ke:wysi_counter|counter_cell[9]~COUT
--operation mode is clrb_cntr

E7L12 = CARRY(E7_q[9] & E7L91);


--E7_q[8] is lpm_counter:dpm_ni2f_naddr_ix7|alt_counter_f10ke:wysi_counter|q[8]
--operation mode is clrb_cntr

E7_q[8]_lut_out = (E7_q[8] $ (dpm_ni2f_reg_sm_2 & E7L71)) & A1L931;
E7_q[8] = DFFEA(E7_q[8]_lut_out, CLK50M, , , , , );

--E7L91 is lpm_counter:dpm_ni2f_naddr_ix7|alt_counter_f10ke:wysi_counter|counter_cell[8]~COUT
--operation mode is clrb_cntr

E7L91 = CARRY(E7_q[8] & E7L71);


--E7_q[7] is lpm_counter:dpm_ni2f_naddr_ix7|alt_counter_f10ke:wysi_counter|q[7]
--operation mode is clrb_cntr

E7_q[7]_lut_out = (E7_q[7] $ (dpm_ni2f_reg_sm_2 & E7L51)) & A1L931;
E7_q[7] = DFFEA(E7_q[7]_lut_out, CLK50M, , , , , );

--E7L71 is lpm_counter:dpm_ni2f_naddr_ix7|alt_counter_f10ke:wysi_counter|counter_cell[7]~COUT
--operation mode is clrb_cntr

E7L71 = CARRY(E7_q[7] & E7L51);


--E7_q[6] is lpm_counter:dpm_ni2f_naddr_ix7|alt_counter_f10ke:wysi_counter|q[6]
--operation mode is clrb_cntr

E7_q[6]_lut_out = (E7_q[6] $ (dpm_ni2f_reg_sm_2 & E7L31)) & A1L931;
E7_q[6] = DFFEA(E7_q[6]_lut_out, CLK50M, , , , , );

--E7L51 is lpm_counter:dpm_ni2f_naddr_ix7|alt_counter_f10ke:wysi_counter|counter_cell[6]~COUT
--operation mode is clrb_cntr

E7L51 = CARRY(E7_q[6] & E7L31);


--E7_q[5] is lpm_counter:dpm_ni2f_naddr_ix7|alt_counter_f10ke:wysi_counter|q[5]
--operation mode is clrb_cntr

E7_q[5]_lut_out = (E7_q[5] $ (dpm_ni2f_reg_sm_2 & E7L11)) & A1L931;
E7_q[5] = DFFEA(E7_q[5]_lut_out, CLK50M, , , , , );

--E7L31 is lpm_counter:dpm_ni2f_naddr_ix7|alt_counter_f10ke:wysi_counter|counter_cell[5]~COUT
--operation mode is clrb_cntr

E7L31 = CARRY(E7_q[5] & E7L11);


--E7_q[4] is lpm_counter:dpm_ni2f_naddr_ix7|alt_counter_f10ke:wysi_counter|q[4]
--operation mode is clrb_cntr

E7_q[4]_lut_out = (E7_q[4] $ (dpm_ni2f_reg_sm_2 & E7L9)) & A1L931;
E7_q[4] = DFFEA(E7_q[4]_lut_out, CLK50M, , , , , );

--E7L11 is lpm_counter:dpm_ni2f_naddr_ix7|alt_counter_f10ke:wysi_counter|counter_cell[4]~COUT
--operation mode is clrb_cntr

E7L11 = CARRY(E7_q[4] & E7L9);


--E7_q[3] is lpm_counter:dpm_ni2f_naddr_ix7|alt_counter_f10ke:wysi_counter|q[3]
--operation mode is clrb_cntr

E7_q[3]_lut_out = (E7_q[3] $ (dpm_ni2f_reg_sm_2 & E7L7)) & A1L931;
E7_q[3] = DFFEA(E7_q[3]_lut_out, CLK50M, , , , , );

--E7L9 is lpm_counter:dpm_ni2f_naddr_ix7|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT
--operation mode is clrb_cntr

E7L9 = CARRY(E7_q[3] & E7L7);


--E7_q[2] is lpm_counter:dpm_ni2f_naddr_ix7|alt_counter_f10ke:wysi_counter|q[2]
--operation mode is clrb_cntr

E7_q[2]_lut_out = (E7_q[2] $ (dpm_ni2f_reg_sm_2 & E7L5)) & A1L931;
E7_q[2] = DFFEA(E7_q[2]_lut_out, CLK50M, , , , , );

--E7L7 is lpm_counter:dpm_ni2f_naddr_ix7|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT
--operation mode is clrb_cntr

E7L7 = CARRY(E7_q[2] & E7L5);


--E7_q[1] is lpm_counter:dpm_ni2f_naddr_ix7|alt_counter_f10ke:wysi_counter|q[1]
--operation mode is clrb_cntr

E7_q[1]_lut_out = (E7_q[1] $ (dpm_ni2f_reg_sm_2 & E7L3)) & A1L931;
E7_q[1] = DFFEA(E7_q[1]_lut_out, CLK50M, , , , , );

--E7L5 is lpm_counter:dpm_ni2f_naddr_ix7|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT
--operation mode is clrb_cntr

E7L5 = CARRY(E7_q[1] & E7L3);


--E7_q[0] is lpm_counter:dpm_ni2f_naddr_ix7|alt_counter_f10ke:wysi_counter|q[0]
--operation mode is clrb_cntr

E7_q[0]_lut_out = (dpm_ni2f_reg_sm_2 $ E7_q[0]) & A1L931;
E7_q[0] = DFFEA(E7_q[0]_lut_out, CLK50M, , , , , );

--E7L3 is lpm_counter:dpm_ni2f_naddr_ix7|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT
--operation mode is clrb_cntr

E7L3 = CARRY(E7_q[0]);


--E6_q[5] is lpm_counter:dpm_ni2f_naddr_dup_2_ix8|alt_counter_f10ke:wysi_counter|q[5]
--operation mode is clrb_cntr

E6_q[5]_lut_out = (E6_q[5] $ (ix2007_lc & E6L11)) & E6L31;
E6_q[5] = DFFEA(E6_q[5]_lut_out, CLK50M, , , ix2007_lc, , );


--E6_q[4] is lpm_counter:dpm_ni2f_naddr_dup_2_ix8|alt_counter_f10ke:wysi_counter|q[4]
--operation mode is clrb_cntr

E6_q[4]_lut_out = (E6_q[4] $ (ix2007_lc & E6L9)) & E6L31;
E6_q[4] = DFFEA(E6_q[4]_lut_out, CLK50M, , , ix2007_lc, , );

--E6L11 is lpm_counter:dpm_ni2f_naddr_dup_2_ix8|alt_counter_f10ke:wysi_counter|counter_cell[4]~COUT
--operation mode is clrb_cntr

E6L11 = CARRY(E6_q[4] & E6L9);


--E6_q[3] is lpm_counter:dpm_ni2f_naddr_dup_2_ix8|alt_counter_f10ke:wysi_counter|q[3]
--operation mode is clrb_cntr

E6_q[3]_lut_out = (E6_q[3] $ (ix2007_lc & E6L7)) & E6L31;
E6_q[3] = DFFEA(E6_q[3]_lut_out, CLK50M, , , ix2007_lc, , );

--E6L9 is lpm_counter:dpm_ni2f_naddr_dup_2_ix8|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT
--operation mode is clrb_cntr

E6L9 = CARRY(E6_q[3] & E6L7);


--E6_q[2] is lpm_counter:dpm_ni2f_naddr_dup_2_ix8|alt_counter_f10ke:wysi_counter|q[2]
--operation mode is clrb_cntr

E6_q[2]_lut_out = (E6_q[2] $ (ix2007_lc & E6L5)) & E6L31;
E6_q[2] = DFFEA(E6_q[2]_lut_out, CLK50M, , , ix2007_lc, , );

--E6L7 is lpm_counter:dpm_ni2f_naddr_dup_2_ix8|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT
--operation mode is clrb_cntr

E6L7 = CARRY(E6_q[2] & E6L5);


--E6_q[1] is lpm_counter:dpm_ni2f_naddr_dup_2_ix8|alt_counter_f10ke:wysi_counter|q[1]
--operation mode is clrb_cntr

E6_q[1]_lut_out = (E6_q[1] $ (ix2007_lc & E6L3)) & E6L31;
E6_q[1] = DFFEA(E6_q[1]_lut_out, CLK50M, , , ix2007_lc, , );

--E6L5 is lpm_counter:dpm_ni2f_naddr_dup_2_ix8|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT
--operation mode is clrb_cntr

E6L5 = CARRY(E6_q[1] & E6L3);


--E6_q[0] is lpm_counter:dpm_ni2f_naddr_dup_2_ix8|alt_counter_f10ke:wysi_counter|q[0]
--operation mode is clrb_cntr

E6_q[0]_lut_out = (ix2007_lc $ E6_q[0]) & E6L31;
E6_q[0] = DFFEA(E6_q[0]_lut_out, CLK50M, , , ix2007_lc, , );

--E6L3 is lpm_counter:dpm_ni2f_naddr_dup_2_ix8|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT
--operation mode is clrb_cntr

E6L3 = CARRY(E6_q[0]);


--E5_q[10] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|lpm_counter:cntr2|alt_counter_f10ke:wysi_counter|q[10]
--operation mode is clrb_cntr

E5_q[10]_lut_out = (E5_q[10] $ (dpm_ni2f_reg_rdreq_fifo & E5L12)) & VCC;
E5_q[10] = DFFEA(E5_q[10]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );


--E5_q[9] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|lpm_counter:cntr2|alt_counter_f10ke:wysi_counter|q[9]
--operation mode is clrb_cntr

E5_q[9]_lut_out = (E5_q[9] $ (dpm_ni2f_reg_rdreq_fifo & E5L91)) & VCC;
E5_q[9] = DFFEA(E5_q[9]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );

--E5L12 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|lpm_counter:cntr2|alt_counter_f10ke:wysi_counter|counter_cell[9]~COUT
--operation mode is clrb_cntr

E5L12 = CARRY(E5_q[9] & E5L91);


--E5_q[8] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|lpm_counter:cntr2|alt_counter_f10ke:wysi_counter|q[8]
--operation mode is clrb_cntr

E5_q[8]_lut_out = (E5_q[8] $ (dpm_ni2f_reg_rdreq_fifo & E5L71)) & VCC;
E5_q[8] = DFFEA(E5_q[8]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );

--E5L91 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|lpm_counter:cntr2|alt_counter_f10ke:wysi_counter|counter_cell[8]~COUT
--operation mode is clrb_cntr

E5L91 = CARRY(E5_q[8] & E5L71);


--E5_q[7] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|lpm_counter:cntr2|alt_counter_f10ke:wysi_counter|q[7]
--operation mode is clrb_cntr

E5_q[7]_lut_out = (E5_q[7] $ (dpm_ni2f_reg_rdreq_fifo & E5L51)) & VCC;
E5_q[7] = DFFEA(E5_q[7]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );

--E5L71 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|lpm_counter:cntr2|alt_counter_f10ke:wysi_counter|counter_cell[7]~COUT
--operation mode is clrb_cntr

E5L71 = CARRY(E5_q[7] & E5L51);


--E5_q[6] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|lpm_counter:cntr2|alt_counter_f10ke:wysi_counter|q[6]
--operation mode is clrb_cntr

E5_q[6]_lut_out = (E5_q[6] $ (dpm_ni2f_reg_rdreq_fifo & E5L31)) & VCC;
E5_q[6] = DFFEA(E5_q[6]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );

--E5L51 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|lpm_counter:cntr2|alt_counter_f10ke:wysi_counter|counter_cell[6]~COUT
--operation mode is clrb_cntr

E5L51 = CARRY(E5_q[6] & E5L31);


--E5_q[5] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|lpm_counter:cntr2|alt_counter_f10ke:wysi_counter|q[5]
--operation mode is clrb_cntr

E5_q[5]_lut_out = (E5_q[5] $ (dpm_ni2f_reg_rdreq_fifo & E5L11)) & VCC;
E5_q[5] = DFFEA(E5_q[5]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );

--E5L31 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|lpm_counter:cntr2|alt_counter_f10ke:wysi_counter|counter_cell[5]~COUT
--operation mode is clrb_cntr

E5L31 = CARRY(E5_q[5] & E5L11);


--E5_q[4] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|lpm_counter:cntr2|alt_counter_f10ke:wysi_counter|q[4]
--operation mode is clrb_cntr

E5_q[4]_lut_out = (E5_q[4] $ (dpm_ni2f_reg_rdreq_fifo & E5L9)) & VCC;
E5_q[4] = DFFEA(E5_q[4]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );

--E5L11 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|lpm_counter:cntr2|alt_counter_f10ke:wysi_counter|counter_cell[4]~COUT
--operation mode is clrb_cntr

E5L11 = CARRY(E5_q[4] & E5L9);


--E5_q[3] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|lpm_counter:cntr2|alt_counter_f10ke:wysi_counter|q[3]
--operation mode is clrb_cntr

E5_q[3]_lut_out = (E5_q[3] $ (dpm_ni2f_reg_rdreq_fifo & E5L7)) & VCC;
E5_q[3] = DFFEA(E5_q[3]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );

--E5L9 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|lpm_counter:cntr2|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT
--operation mode is clrb_cntr

E5L9 = CARRY(E5_q[3] & E5L7);


--E5_q[2] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|lpm_counter:cntr2|alt_counter_f10ke:wysi_counter|q[2]
--operation mode is clrb_cntr

E5_q[2]_lut_out = (E5_q[2] $ (dpm_ni2f_reg_rdreq_fifo & E5L5)) & VCC;
E5_q[2] = DFFEA(E5_q[2]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );

--E5L7 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|lpm_counter:cntr2|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT
--operation mode is clrb_cntr

E5L7 = CARRY(E5_q[2] & E5L5);


--E5_q[1] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|lpm_counter:cntr2|alt_counter_f10ke:wysi_counter|q[1]
--operation mode is clrb_cntr

E5_q[1]_lut_out = (E5_q[1] $ (dpm_ni2f_reg_rdreq_fifo & E5L3)) & VCC;
E5_q[1] = DFFEA(E5_q[1]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );

--E5L5 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|lpm_counter:cntr2|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT
--operation mode is clrb_cntr

E5L5 = CARRY(E5_q[1] & E5L3);


--E5_q[0] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|lpm_counter:cntr2|alt_counter_f10ke:wysi_counter|q[0]
--operation mode is clrb_cntr

E5_q[0]_lut_out = (dpm_ni2f_reg_rdreq_fifo $ E5_q[0]) & VCC;
E5_q[0] = DFFEA(E5_q[0]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );

--E5L3 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|lpm_counter:cntr2|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT
--operation mode is clrb_cntr

E5L3 = CARRY(E5_q[0]);


--M2_flx10ke_lcell35 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_ej6:a_graycounter7|flx10ke_lcell35
--operation mode is up_dn_cntr

M2_flx10ke_lcell35_lut_out = M2_flx10ke_lcell35 $ (dpm_ni2f_reg_rdreq_fifo & !M2_flx10ke_lcell46);
M2_flx10ke_lcell35 = DFFEA(M2_flx10ke_lcell35_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );

--M2L2 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_ej6:a_graycounter7|flx10ke_lcell35~COUT
--operation mode is up_dn_cntr

M2L2 = CARRY(dpm_ni2f_reg_rdreq_fifo & M2_flx10ke_lcell46);


--M2_power_modified_counter_values[1] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_ej6:a_graycounter7|power_modified_counter_values[1]
--operation mode is up_dn_cntr

M2_power_modified_counter_values[1]_lut_out = M2_power_modified_counter_values[1] $ (R2L4 & M2L2);
M2_power_modified_counter_values[1] = DFFEA(M2_power_modified_counter_values[1]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );

--M2L4 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_ej6:a_graycounter7|flx10ke_lcell36~COUT
--operation mode is up_dn_cntr

M2L4 = CARRY(!R2L4 & M2L2);


--M2_power_modified_counter_values[2] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_ej6:a_graycounter7|power_modified_counter_values[2]
--operation mode is up_dn_cntr

M2_power_modified_counter_values[2]_lut_out = M2_power_modified_counter_values[2] $ (M2_power_modified_counter_values[1] & M2L4);
M2_power_modified_counter_values[2] = DFFEA(M2_power_modified_counter_values[2]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );

--M2L6 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_ej6:a_graycounter7|flx10ke_lcell37~COUT
--operation mode is up_dn_cntr

M2L6 = CARRY(!M2_power_modified_counter_values[1] & M2L4);


--M2_power_modified_counter_values[3] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_ej6:a_graycounter7|power_modified_counter_values[3]
--operation mode is up_dn_cntr

M2_power_modified_counter_values[3]_lut_out = M2_power_modified_counter_values[3] $ (M2_power_modified_counter_values[2] & M2L6);
M2_power_modified_counter_values[3] = DFFEA(M2_power_modified_counter_values[3]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );

--M2L8 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_ej6:a_graycounter7|flx10ke_lcell38~COUT
--operation mode is up_dn_cntr

M2L8 = CARRY(!M2_power_modified_counter_values[2] & M2L6);


--M2_power_modified_counter_values[4] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_ej6:a_graycounter7|power_modified_counter_values[4]
--operation mode is up_dn_cntr

M2_power_modified_counter_values[4]_lut_out = M2_power_modified_counter_values[4] $ (M2_power_modified_counter_values[3] & M2L8);
M2_power_modified_counter_values[4] = DFFEA(M2_power_modified_counter_values[4]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );

--M2L01 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_ej6:a_graycounter7|flx10ke_lcell39~COUT
--operation mode is up_dn_cntr

M2L01 = CARRY(!M2_power_modified_counter_values[3] & M2L8);


--M2_power_modified_counter_values[5] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_ej6:a_graycounter7|power_modified_counter_values[5]
--operation mode is up_dn_cntr

M2_power_modified_counter_values[5]_lut_out = M2_power_modified_counter_values[5] $ (M2_power_modified_counter_values[4] & M2L01);
M2_power_modified_counter_values[5] = DFFEA(M2_power_modified_counter_values[5]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );

--M2L21 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_ej6:a_graycounter7|flx10ke_lcell40~COUT
--operation mode is up_dn_cntr

M2L21 = CARRY(!M2_power_modified_counter_values[4] & M2L01);


--M2_power_modified_counter_values[6] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_ej6:a_graycounter7|power_modified_counter_values[6]
--operation mode is up_dn_cntr

M2_power_modified_counter_values[6]_lut_out = M2_power_modified_counter_values[6] $ (M2_power_modified_counter_values[5] & M2L21);
M2_power_modified_counter_values[6] = DFFEA(M2_power_modified_counter_values[6]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );

--M2L41 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_ej6:a_graycounter7|flx10ke_lcell41~COUT
--operation mode is up_dn_cntr

M2L41 = CARRY(!M2_power_modified_counter_values[5] & M2L21);


--M2_power_modified_counter_values[7] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_ej6:a_graycounter7|power_modified_counter_values[7]
--operation mode is up_dn_cntr

M2_power_modified_counter_values[7]_lut_out = M2_power_modified_counter_values[7] $ (M2_power_modified_counter_values[6] & M2L41);
M2_power_modified_counter_values[7] = DFFEA(M2_power_modified_counter_values[7]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );

--M2L61 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_ej6:a_graycounter7|flx10ke_lcell42~COUT
--operation mode is up_dn_cntr

M2L61 = CARRY(!M2_power_modified_counter_values[6] & M2L41);


--M2_power_modified_counter_values[8] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_ej6:a_graycounter7|power_modified_counter_values[8]
--operation mode is up_dn_cntr

M2_power_modified_counter_values[8]_lut_out = M2_power_modified_counter_values[8] $ (M2_power_modified_counter_values[7] & M2L61);
M2_power_modified_counter_values[8] = DFFEA(M2_power_modified_counter_values[8]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );

--M2L81 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_ej6:a_graycounter7|flx10ke_lcell43~COUT
--operation mode is up_dn_cntr

M2L81 = CARRY(!M2_power_modified_counter_values[7] & M2L61);


--M2_power_modified_counter_values[9] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_ej6:a_graycounter7|power_modified_counter_values[9]
--operation mode is up_dn_cntr

M2_power_modified_counter_values[9]_lut_out = M2_power_modified_counter_values[9] $ (M2_power_modified_counter_values[8] & M2L81);
M2_power_modified_counter_values[9] = DFFEA(M2_power_modified_counter_values[9]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );

--M2L02 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_ej6:a_graycounter7|flx10ke_lcell44~COUT
--operation mode is up_dn_cntr

M2L02 = CARRY(!M2_power_modified_counter_values[8] & M2L81);


--M2_power_modified_counter_values[10] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_ej6:a_graycounter7|power_modified_counter_values[10]
--operation mode is up_dn_cntr

M2_power_modified_counter_values[10]_lut_out = M2_power_modified_counter_values[10] $ M2L02;
M2_power_modified_counter_values[10] = DFFEA(M2_power_modified_counter_values[10]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );


--M2L32Q is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_ej6:a_graycounter7|flx10ke_lcell46~REGOUT
--operation mode is up_dn_cntr

M2L32Q_lut_out = dpm_ni2f_reg_rdreq_fifo $ M2L32Q;
M2L32Q = DFFEA(M2L32Q_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );

--M2_flx10ke_lcell46 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_ej6:a_graycounter7|flx10ke_lcell46
--operation mode is up_dn_cntr

M2_flx10ke_lcell46 = CARRY(!M2L32Q & dpm_ni2f_reg_rdreq_fifo);


--L2_power_modified_counter_values[0] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_jq5:a_graycounter3|power_modified_counter_values[0]
--operation mode is up_dn_cntr

L2_power_modified_counter_values[0]_lut_out = L2_power_modified_counter_values[0] $ !L2_flx10ke_lcell34;
L2_power_modified_counter_values[0] = DFFEA(L2_power_modified_counter_values[0]_lut_out, ADC2_D[2], !dpm_ni2f_reg_sreset120, , , , );

--L2L2 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_jq5:a_graycounter3|flx10ke_lcell23~COUT
--operation mode is up_dn_cntr

L2L2 = CARRY(L2_flx10ke_lcell34);


--L2_power_modified_counter_values[1] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_jq5:a_graycounter3|power_modified_counter_values[1]
--operation mode is up_dn_cntr

L2_power_modified_counter_values[1]_lut_out = L2_power_modified_counter_values[1] $ (L2_power_modified_counter_values[0] & L2L2);
L2_power_modified_counter_values[1] = DFFEA(L2_power_modified_counter_values[1]_lut_out, ADC2_D[2], !dpm_ni2f_reg_sreset120, , , , );

--L2L4 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_jq5:a_graycounter3|flx10ke_lcell24~COUT
--operation mode is up_dn_cntr

L2L4 = CARRY(!L2_power_modified_counter_values[0] & L2L2);


--L2_power_modified_counter_values[2] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_jq5:a_graycounter3|power_modified_counter_values[2]
--operation mode is up_dn_cntr

L2_power_modified_counter_values[2]_lut_out = L2_power_modified_counter_values[2] $ (L2_power_modified_counter_values[1] & L2L4);
L2_power_modified_counter_values[2] = DFFEA(L2_power_modified_counter_values[2]_lut_out, ADC2_D[2], !dpm_ni2f_reg_sreset120, , , , );

--L2L6 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_jq5:a_graycounter3|flx10ke_lcell25~COUT
--operation mode is up_dn_cntr

L2L6 = CARRY(!L2_power_modified_counter_values[1] & L2L4);


--L2_power_modified_counter_values[3] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_jq5:a_graycounter3|power_modified_counter_values[3]
--operation mode is up_dn_cntr

L2_power_modified_counter_values[3]_lut_out = L2_power_modified_counter_values[3] $ (L2_power_modified_counter_values[2] & L2L6);
L2_power_modified_counter_values[3] = DFFEA(L2_power_modified_counter_values[3]_lut_out, ADC2_D[2], !dpm_ni2f_reg_sreset120, , , , );

--L2L8 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_jq5:a_graycounter3|flx10ke_lcell26~COUT
--operation mode is up_dn_cntr

L2L8 = CARRY(!L2_power_modified_counter_values[2] & L2L6);


--L2_power_modified_counter_values[4] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_jq5:a_graycounter3|power_modified_counter_values[4]
--operation mode is up_dn_cntr

L2_power_modified_counter_values[4]_lut_out = L2_power_modified_counter_values[4] $ (L2_power_modified_counter_values[3] & L2L8);
L2_power_modified_counter_values[4] = DFFEA(L2_power_modified_counter_values[4]_lut_out, ADC2_D[2], !dpm_ni2f_reg_sreset120, , , , );

--L2L01 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_jq5:a_graycounter3|flx10ke_lcell27~COUT
--operation mode is up_dn_cntr

L2L01 = CARRY(!L2_power_modified_counter_values[3] & L2L8);


--L2_power_modified_counter_values[5] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_jq5:a_graycounter3|power_modified_counter_values[5]
--operation mode is up_dn_cntr

L2_power_modified_counter_values[5]_lut_out = L2_power_modified_counter_values[5] $ (L2_power_modified_counter_values[4] & L2L01);
L2_power_modified_counter_values[5] = DFFEA(L2_power_modified_counter_values[5]_lut_out, ADC2_D[2], !dpm_ni2f_reg_sreset120, , , , );

--L2L21 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_jq5:a_graycounter3|flx10ke_lcell28~COUT
--operation mode is up_dn_cntr

L2L21 = CARRY(!L2_power_modified_counter_values[4] & L2L01);


--L2_power_modified_counter_values[6] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_jq5:a_graycounter3|power_modified_counter_values[6]
--operation mode is up_dn_cntr

L2_power_modified_counter_values[6]_lut_out = L2_power_modified_counter_values[6] $ (L2_power_modified_counter_values[5] & L2L21);
L2_power_modified_counter_values[6] = DFFEA(L2_power_modified_counter_values[6]_lut_out, ADC2_D[2], !dpm_ni2f_reg_sreset120, , , , );

--L2L41 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_jq5:a_graycounter3|flx10ke_lcell29~COUT
--operation mode is up_dn_cntr

L2L41 = CARRY(!L2_power_modified_counter_values[5] & L2L21);


--L2_power_modified_counter_values[7] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_jq5:a_graycounter3|power_modified_counter_values[7]
--operation mode is up_dn_cntr

L2_power_modified_counter_values[7]_lut_out = L2_power_modified_counter_values[7] $ (L2_power_modified_counter_values[6] & L2L41);
L2_power_modified_counter_values[7] = DFFEA(L2_power_modified_counter_values[7]_lut_out, ADC2_D[2], !dpm_ni2f_reg_sreset120, , , , );

--L2L61 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_jq5:a_graycounter3|flx10ke_lcell30~COUT
--operation mode is up_dn_cntr

L2L61 = CARRY(!L2_power_modified_counter_values[6] & L2L41);


--L2_power_modified_counter_values[8] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_jq5:a_graycounter3|power_modified_counter_values[8]
--operation mode is up_dn_cntr

L2_power_modified_counter_values[8]_lut_out = L2_power_modified_counter_values[8] $ (L2_power_modified_counter_values[7] & L2L61);
L2_power_modified_counter_values[8] = DFFEA(L2_power_modified_counter_values[8]_lut_out, ADC2_D[2], !dpm_ni2f_reg_sreset120, , , , );

--L2L81 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_jq5:a_graycounter3|flx10ke_lcell31~COUT
--operation mode is up_dn_cntr

L2L81 = CARRY(!L2_power_modified_counter_values[7] & L2L61);


--L2_power_modified_counter_values[9] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_jq5:a_graycounter3|power_modified_counter_values[9]
--operation mode is up_dn_cntr

L2_power_modified_counter_values[9]_lut_out = L2_power_modified_counter_values[9] $ (L2_power_modified_counter_values[8] & L2L81);
L2_power_modified_counter_values[9] = DFFEA(L2_power_modified_counter_values[9]_lut_out, ADC2_D[2], !dpm_ni2f_reg_sreset120, , , , );

--L2L02 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_jq5:a_graycounter3|flx10ke_lcell32~COUT
--operation mode is up_dn_cntr

L2L02 = CARRY(!L2_power_modified_counter_values[8] & L2L81);


--L2_power_modified_counter_values[10] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_jq5:a_graycounter3|power_modified_counter_values[10]
--operation mode is up_dn_cntr

L2_power_modified_counter_values[10]_lut_out = L2_power_modified_counter_values[10] $ L2L02;
L2_power_modified_counter_values[10] = DFFEA(L2_power_modified_counter_values[10]_lut_out, ADC2_D[2], !dpm_ni2f_reg_sreset120, , , , );


--L2L32Q is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_jq5:a_graycounter3|flx10ke_lcell34~REGOUT
--operation mode is up_dn_cntr

L2L32Q_lut_out = !L2L32Q;
L2L32Q = DFFEA(L2L32Q_lut_out, ADC2_D[2], !dpm_ni2f_reg_sreset120, , , , );

--L2_flx10ke_lcell34 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_jq5:a_graycounter3|flx10ke_lcell34
--operation mode is up_dn_cntr

L2_flx10ke_lcell34 = CARRY(L2L32Q);


--M1_flx10ke_lcell35 is nififo:dpm_ni2f_fifo_n|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_ej6:a_graycounter7|flx10ke_lcell35
--operation mode is up_dn_cntr

M1_flx10ke_lcell35_lut_out = M1_flx10ke_lcell35 $ (dpm_ni2f_reg_rdreq_fifo & !M1_flx10ke_lcell46);
M1_flx10ke_lcell35 = DFFEA(M1_flx10ke_lcell35_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );

--M1L2 is nififo:dpm_ni2f_fifo_n|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_ej6:a_graycounter7|flx10ke_lcell35~COUT
--operation mode is up_dn_cntr

M1L2 = CARRY(dpm_ni2f_reg_rdreq_fifo & M1_flx10ke_lcell46);


--M1_power_modified_counter_values[1] is nififo:dpm_ni2f_fifo_n|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_ej6:a_graycounter7|power_modified_counter_values[1]
--operation mode is up_dn_cntr

M1_power_modified_counter_values[1]_lut_out = M1_power_modified_counter_values[1] $ (R1L4 & M1L2);
M1_power_modified_counter_values[1] = DFFEA(M1_power_modified_counter_values[1]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );

--M1L4 is nififo:dpm_ni2f_fifo_n|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_ej6:a_graycounter7|flx10ke_lcell36~COUT
--operation mode is up_dn_cntr

M1L4 = CARRY(!R1L4 & M1L2);


--M1_power_modified_counter_values[2] is nififo:dpm_ni2f_fifo_n|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_ej6:a_graycounter7|power_modified_counter_values[2]
--operation mode is up_dn_cntr

M1_power_modified_counter_values[2]_lut_out = M1_power_modified_counter_values[2] $ (M1_power_modified_counter_values[1] & M1L4);
M1_power_modified_counter_values[2] = DFFEA(M1_power_modified_counter_values[2]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );

--M1L6 is nififo:dpm_ni2f_fifo_n|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_ej6:a_graycounter7|flx10ke_lcell37~COUT
--operation mode is up_dn_cntr

M1L6 = CARRY(!M1_power_modified_counter_values[1] & M1L4);


--M1_power_modified_counter_values[3] is nififo:dpm_ni2f_fifo_n|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_ej6:a_graycounter7|power_modified_counter_values[3]
--operation mode is up_dn_cntr

M1_power_modified_counter_values[3]_lut_out = M1_power_modified_counter_values[3] $ (M1_power_modified_counter_values[2] & M1L6);
M1_power_modified_counter_values[3] = DFFEA(M1_power_modified_counter_values[3]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );

--M1L8 is nififo:dpm_ni2f_fifo_n|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_ej6:a_graycounter7|flx10ke_lcell38~COUT
--operation mode is up_dn_cntr

M1L8 = CARRY(!M1_power_modified_counter_values[2] & M1L6);


--M1_power_modified_counter_values[4] is nififo:dpm_ni2f_fifo_n|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_ej6:a_graycounter7|power_modified_counter_values[4]
--operation mode is up_dn_cntr

M1_power_modified_counter_values[4]_lut_out = M1_power_modified_counter_values[4] $ (M1_power_modified_counter_values[3] & M1L8);
M1_power_modified_counter_values[4] = DFFEA(M1_power_modified_counter_values[4]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );

--M1L01 is nififo:dpm_ni2f_fifo_n|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_ej6:a_graycounter7|flx10ke_lcell39~COUT
--operation mode is up_dn_cntr

M1L01 = CARRY(!M1_power_modified_counter_values[3] & M1L8);


--M1_power_modified_counter_values[5] is nififo:dpm_ni2f_fifo_n|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_ej6:a_graycounter7|power_modified_counter_values[5]
--operation mode is up_dn_cntr

M1_power_modified_counter_values[5]_lut_out = M1_power_modified_counter_values[5] $ (M1_power_modified_counter_values[4] & M1L01);
M1_power_modified_counter_values[5] = DFFEA(M1_power_modified_counter_values[5]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );

--M1L21 is nififo:dpm_ni2f_fifo_n|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_ej6:a_graycounter7|flx10ke_lcell40~COUT
--operation mode is up_dn_cntr

M1L21 = CARRY(!M1_power_modified_counter_values[4] & M1L01);


--M1_power_modified_counter_values[6] is nififo:dpm_ni2f_fifo_n|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_ej6:a_graycounter7|power_modified_counter_values[6]
--operation mode is up_dn_cntr

M1_power_modified_counter_values[6]_lut_out = M1_power_modified_counter_values[6] $ (M1_power_modified_counter_values[5] & M1L21);
M1_power_modified_counter_values[6] = DFFEA(M1_power_modified_counter_values[6]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );

--M1L41 is nififo:dpm_ni2f_fifo_n|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_ej6:a_graycounter7|flx10ke_lcell41~COUT
--operation mode is up_dn_cntr

M1L41 = CARRY(!M1_power_modified_counter_values[5] & M1L21);


--M1_power_modified_counter_values[7] is nififo:dpm_ni2f_fifo_n|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_ej6:a_graycounter7|power_modified_counter_values[7]
--operation mode is up_dn_cntr

M1_power_modified_counter_values[7]_lut_out = M1_power_modified_counter_values[7] $ (M1_power_modified_counter_values[6] & M1L41);
M1_power_modified_counter_values[7] = DFFEA(M1_power_modified_counter_values[7]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );

--M1L61 is nififo:dpm_ni2f_fifo_n|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_ej6:a_graycounter7|flx10ke_lcell42~COUT
--operation mode is up_dn_cntr

M1L61 = CARRY(!M1_power_modified_counter_values[6] & M1L41);


--M1_power_modified_counter_values[8] is nififo:dpm_ni2f_fifo_n|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_ej6:a_graycounter7|power_modified_counter_values[8]
--operation mode is up_dn_cntr

M1_power_modified_counter_values[8]_lut_out = M1_power_modified_counter_values[8] $ (M1_power_modified_counter_values[7] & M1L61);
M1_power_modified_counter_values[8] = DFFEA(M1_power_modified_counter_values[8]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );

--M1L81 is nififo:dpm_ni2f_fifo_n|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_ej6:a_graycounter7|flx10ke_lcell43~COUT
--operation mode is up_dn_cntr

M1L81 = CARRY(!M1_power_modified_counter_values[7] & M1L61);


--M1_power_modified_counter_values[9] is nififo:dpm_ni2f_fifo_n|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_ej6:a_graycounter7|power_modified_counter_values[9]
--operation mode is up_dn_cntr

M1_power_modified_counter_values[9]_lut_out = M1_power_modified_counter_values[9] $ (M1_power_modified_counter_values[8] & M1L81);
M1_power_modified_counter_values[9] = DFFEA(M1_power_modified_counter_values[9]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );

--M1L02 is nififo:dpm_ni2f_fifo_n|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_ej6:a_graycounter7|flx10ke_lcell44~COUT
--operation mode is up_dn_cntr

M1L02 = CARRY(!M1_power_modified_counter_values[8] & M1L81);


--M1_power_modified_counter_values[10] is nififo:dpm_ni2f_fifo_n|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_ej6:a_graycounter7|power_modified_counter_values[10]
--operation mode is up_dn_cntr

M1_power_modified_counter_values[10]_lut_out = M1_power_modified_counter_values[10] $ M1L02;
M1_power_modified_counter_values[10] = DFFEA(M1_power_modified_counter_values[10]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );


--M1L32Q is nififo:dpm_ni2f_fifo_n|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_ej6:a_graycounter7|flx10ke_lcell46~REGOUT
--operation mode is up_dn_cntr

M1L32Q_lut_out = dpm_ni2f_reg_rdreq_fifo $ M1L32Q;
M1L32Q = DFFEA(M1L32Q_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );

--M1_flx10ke_lcell46 is nififo:dpm_ni2f_fifo_n|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_ej6:a_graycounter7|flx10ke_lcell46
--operation mode is up_dn_cntr

M1_flx10ke_lcell46 = CARRY(!M1L32Q & dpm_ni2f_reg_rdreq_fifo);


--L1_power_modified_counter_values[0] is nififo:dpm_ni2f_fifo_n|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_jq5:a_graycounter3|power_modified_counter_values[0]
--operation mode is up_dn_cntr

L1_power_modified_counter_values[0]_lut_out = L1_power_modified_counter_values[0] $ !L1_flx10ke_lcell34;
L1_power_modified_counter_values[0] = DFFEA(L1_power_modified_counter_values[0]_lut_out, !ADC2_D[2], !dpm_ni2f_reg_sreset120, , , , );

--L1L2 is nififo:dpm_ni2f_fifo_n|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_jq5:a_graycounter3|flx10ke_lcell23~COUT
--operation mode is up_dn_cntr

L1L2 = CARRY(L1_flx10ke_lcell34);


--L1_power_modified_counter_values[1] is nififo:dpm_ni2f_fifo_n|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_jq5:a_graycounter3|power_modified_counter_values[1]
--operation mode is up_dn_cntr

L1_power_modified_counter_values[1]_lut_out = L1_power_modified_counter_values[1] $ (L1_power_modified_counter_values[0] & L1L2);
L1_power_modified_counter_values[1] = DFFEA(L1_power_modified_counter_values[1]_lut_out, !ADC2_D[2], !dpm_ni2f_reg_sreset120, , , , );

--L1L4 is nififo:dpm_ni2f_fifo_n|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_jq5:a_graycounter3|flx10ke_lcell24~COUT
--operation mode is up_dn_cntr

L1L4 = CARRY(!L1_power_modified_counter_values[0] & L1L2);


--L1_power_modified_counter_values[2] is nififo:dpm_ni2f_fifo_n|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_jq5:a_graycounter3|power_modified_counter_values[2]
--operation mode is up_dn_cntr

L1_power_modified_counter_values[2]_lut_out = L1_power_modified_counter_values[2] $ (L1_power_modified_counter_values[1] & L1L4);
L1_power_modified_counter_values[2] = DFFEA(L1_power_modified_counter_values[2]_lut_out, !ADC2_D[2], !dpm_ni2f_reg_sreset120, , , , );

--L1L6 is nififo:dpm_ni2f_fifo_n|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_jq5:a_graycounter3|flx10ke_lcell25~COUT
--operation mode is up_dn_cntr

L1L6 = CARRY(!L1_power_modified_counter_values[1] & L1L4);


--L1_power_modified_counter_values[3] is nififo:dpm_ni2f_fifo_n|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_jq5:a_graycounter3|power_modified_counter_values[3]
--operation mode is up_dn_cntr

L1_power_modified_counter_values[3]_lut_out = L1_power_modified_counter_values[3] $ (L1_power_modified_counter_values[2] & L1L6);
L1_power_modified_counter_values[3] = DFFEA(L1_power_modified_counter_values[3]_lut_out, !ADC2_D[2], !dpm_ni2f_reg_sreset120, , , , );

--L1L8 is nififo:dpm_ni2f_fifo_n|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_jq5:a_graycounter3|flx10ke_lcell26~COUT
--operation mode is up_dn_cntr

L1L8 = CARRY(!L1_power_modified_counter_values[2] & L1L6);


--L1_power_modified_counter_values[4] is nififo:dpm_ni2f_fifo_n|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_jq5:a_graycounter3|power_modified_counter_values[4]
--operation mode is up_dn_cntr

L1_power_modified_counter_values[4]_lut_out = L1_power_modified_counter_values[4] $ (L1_power_modified_counter_values[3] & L1L8);
L1_power_modified_counter_values[4] = DFFEA(L1_power_modified_counter_values[4]_lut_out, !ADC2_D[2], !dpm_ni2f_reg_sreset120, , , , );

--L1L01 is nififo:dpm_ni2f_fifo_n|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_jq5:a_graycounter3|flx10ke_lcell27~COUT
--operation mode is up_dn_cntr

L1L01 = CARRY(!L1_power_modified_counter_values[3] & L1L8);


--L1_power_modified_counter_values[5] is nififo:dpm_ni2f_fifo_n|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_jq5:a_graycounter3|power_modified_counter_values[5]
--operation mode is up_dn_cntr

L1_power_modified_counter_values[5]_lut_out = L1_power_modified_counter_values[5] $ (L1_power_modified_counter_values[4] & L1L01);
L1_power_modified_counter_values[5] = DFFEA(L1_power_modified_counter_values[5]_lut_out, !ADC2_D[2], !dpm_ni2f_reg_sreset120, , , , );

--L1L21 is nififo:dpm_ni2f_fifo_n|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_jq5:a_graycounter3|flx10ke_lcell28~COUT
--operation mode is up_dn_cntr

L1L21 = CARRY(!L1_power_modified_counter_values[4] & L1L01);


--L1_power_modified_counter_values[6] is nififo:dpm_ni2f_fifo_n|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_jq5:a_graycounter3|power_modified_counter_values[6]
--operation mode is up_dn_cntr

L1_power_modified_counter_values[6]_lut_out = L1_power_modified_counter_values[6] $ (L1_power_modified_counter_values[5] & L1L21);
L1_power_modified_counter_values[6] = DFFEA(L1_power_modified_counter_values[6]_lut_out, !ADC2_D[2], !dpm_ni2f_reg_sreset120, , , , );

--L1L41 is nififo:dpm_ni2f_fifo_n|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_jq5:a_graycounter3|flx10ke_lcell29~COUT
--operation mode is up_dn_cntr

L1L41 = CARRY(!L1_power_modified_counter_values[5] & L1L21);


--L1_power_modified_counter_values[7] is nififo:dpm_ni2f_fifo_n|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_jq5:a_graycounter3|power_modified_counter_values[7]
--operation mode is up_dn_cntr

L1_power_modified_counter_values[7]_lut_out = L1_power_modified_counter_values[7] $ (L1_power_modified_counter_values[6] & L1L41);
L1_power_modified_counter_values[7] = DFFEA(L1_power_modified_counter_values[7]_lut_out, !ADC2_D[2], !dpm_ni2f_reg_sreset120, , , , );

--L1L61 is nififo:dpm_ni2f_fifo_n|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_jq5:a_graycounter3|flx10ke_lcell30~COUT
--operation mode is up_dn_cntr

L1L61 = CARRY(!L1_power_modified_counter_values[6] & L1L41);


--L1_power_modified_counter_values[8] is nififo:dpm_ni2f_fifo_n|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_jq5:a_graycounter3|power_modified_counter_values[8]
--operation mode is up_dn_cntr

L1_power_modified_counter_values[8]_lut_out = L1_power_modified_counter_values[8] $ (L1_power_modified_counter_values[7] & L1L61);
L1_power_modified_counter_values[8] = DFFEA(L1_power_modified_counter_values[8]_lut_out, !ADC2_D[2], !dpm_ni2f_reg_sreset120, , , , );

--L1L81 is nififo:dpm_ni2f_fifo_n|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_jq5:a_graycounter3|flx10ke_lcell31~COUT
--operation mode is up_dn_cntr

L1L81 = CARRY(!L1_power_modified_counter_values[7] & L1L61);


--L1_power_modified_counter_values[9] is nififo:dpm_ni2f_fifo_n|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_jq5:a_graycounter3|power_modified_counter_values[9]
--operation mode is up_dn_cntr

L1_power_modified_counter_values[9]_lut_out = L1_power_modified_counter_values[9] $ (L1_power_modified_counter_values[8] & L1L81);
L1_power_modified_counter_values[9] = DFFEA(L1_power_modified_counter_values[9]_lut_out, !ADC2_D[2], !dpm_ni2f_reg_sreset120, , , , );

--L1L02 is nififo:dpm_ni2f_fifo_n|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_jq5:a_graycounter3|flx10ke_lcell32~COUT
--operation mode is up_dn_cntr

L1L02 = CARRY(!L1_power_modified_counter_values[8] & L1L81);


--L1_power_modified_counter_values[10] is nififo:dpm_ni2f_fifo_n|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_jq5:a_graycounter3|power_modified_counter_values[10]
--operation mode is up_dn_cntr

L1_power_modified_counter_values[10]_lut_out = L1_power_modified_counter_values[10] $ L1L02;
L1_power_modified_counter_values[10] = DFFEA(L1_power_modified_counter_values[10]_lut_out, !ADC2_D[2], !dpm_ni2f_reg_sreset120, , , , );


--L1L32Q is nififo:dpm_ni2f_fifo_n|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_jq5:a_graycounter3|flx10ke_lcell34~REGOUT
--operation mode is up_dn_cntr

L1L32Q_lut_out = !L1L32Q;
L1L32Q = DFFEA(L1L32Q_lut_out, !ADC2_D[2], !dpm_ni2f_reg_sreset120, , , , );

--L1_flx10ke_lcell34 is nififo:dpm_ni2f_fifo_n|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_graycounter_jq5:a_graycounter3|flx10ke_lcell34
--operation mode is up_dn_cntr

L1_flx10ke_lcell34 = CARRY(L1L32Q);


--E1_q[15] is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|q[15]
--operation mode is up_dn_cntr

E1_q[15]_lut_out = E1_q[15] $ E1L13;
E1_q[15] = DFFEA(E1_q[15]_lut_out, GLOBAL(pci_clk), , , , , );


--E1_q[14] is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|q[14]
--operation mode is up_dn_cntr

E1_q[14]_lut_out = E1_q[14] $ E1L92;
E1_q[14] = DFFEA(E1_q[14]_lut_out, GLOBAL(pci_clk), , , , , );

--E1L13 is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[14]~COUT
--operation mode is up_dn_cntr

E1L13 = CARRY(E1_q[14] & E1L92);


--E1_q[13] is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|q[13]
--operation mode is up_dn_cntr

E1_q[13]_lut_out = E1_q[13] $ E1L72;
E1_q[13] = DFFEA(E1_q[13]_lut_out, GLOBAL(pci_clk), , , , , );

--E1L92 is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[13]~COUT
--operation mode is up_dn_cntr

E1L92 = CARRY(E1_q[13] & E1L72);


--E1_q[12] is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|q[12]
--operation mode is up_dn_cntr

E1_q[12]_lut_out = E1_q[12] $ E1L52;
E1_q[12] = DFFEA(E1_q[12]_lut_out, GLOBAL(pci_clk), , , , , );

--E1L72 is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[12]~COUT
--operation mode is up_dn_cntr

E1L72 = CARRY(E1_q[12] & E1L52);


--E1_q[11] is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|q[11]
--operation mode is up_dn_cntr

E1_q[11]_lut_out = E1_q[11] $ E1L32;
E1_q[11] = DFFEA(E1_q[11]_lut_out, GLOBAL(pci_clk), , , , , );

--E1L52 is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[11]~COUT
--operation mode is up_dn_cntr

E1L52 = CARRY(E1_q[11] & E1L32);


--E1_q[10] is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|q[10]
--operation mode is up_dn_cntr

E1_q[10]_lut_out = E1_q[10] $ E1L12;
E1_q[10] = DFFEA(E1_q[10]_lut_out, GLOBAL(pci_clk), , , , , );

--E1L32 is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[10]~COUT
--operation mode is up_dn_cntr

E1L32 = CARRY(E1_q[10] & E1L12);


--E1_q[9] is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|q[9]
--operation mode is up_dn_cntr

E1_q[9]_lut_out = E1_q[9] $ E1L91;
E1_q[9] = DFFEA(E1_q[9]_lut_out, GLOBAL(pci_clk), , , , , );

--E1L12 is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[9]~COUT
--operation mode is up_dn_cntr

E1L12 = CARRY(E1_q[9] & E1L91);


--E1_q[8] is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|q[8]
--operation mode is up_dn_cntr

E1_q[8]_lut_out = E1_q[8] $ E1L71;
E1_q[8] = DFFEA(E1_q[8]_lut_out, GLOBAL(pci_clk), , , , , );

--E1L91 is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[8]~COUT
--operation mode is up_dn_cntr

E1L91 = CARRY(E1_q[8] & E1L71);


--E1_q[7] is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|q[7]
--operation mode is up_dn_cntr

E1_q[7]_lut_out = E1_q[7] $ E1L51;
E1_q[7] = DFFEA(E1_q[7]_lut_out, GLOBAL(pci_clk), , , , , );

--E1L71 is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[7]~COUT
--operation mode is up_dn_cntr

E1L71 = CARRY(E1_q[7] & E1L51);


--E1_q[6] is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|q[6]
--operation mode is up_dn_cntr

E1_q[6]_lut_out = E1_q[6] $ E1L31;
E1_q[6] = DFFEA(E1_q[6]_lut_out, GLOBAL(pci_clk), , , , , );

--E1L51 is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[6]~COUT
--operation mode is up_dn_cntr

E1L51 = CARRY(E1_q[6] & E1L31);


--E1_q[5] is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|q[5]
--operation mode is up_dn_cntr

E1_q[5]_lut_out = E1_q[5] $ E1L11;
E1_q[5] = DFFEA(E1_q[5]_lut_out, GLOBAL(pci_clk), , , , , );

--E1L31 is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[5]~COUT
--operation mode is up_dn_cntr

E1L31 = CARRY(E1_q[5] & E1L11);


--E1_q[4] is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|q[4]
--operation mode is up_dn_cntr

E1_q[4]_lut_out = E1_q[4] $ E1L9;
E1_q[4] = DFFEA(E1_q[4]_lut_out, GLOBAL(pci_clk), , , , , );

--E1L11 is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[4]~COUT
--operation mode is up_dn_cntr

E1L11 = CARRY(E1_q[4] & E1L9);


--E1_q[3] is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|q[3]
--operation mode is up_dn_cntr

E1_q[3]_lut_out = E1_q[3] $ E1L7;
E1_q[3] = DFFEA(E1_q[3]_lut_out, GLOBAL(pci_clk), , , , , );

--E1L9 is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT
--operation mode is up_dn_cntr

E1L9 = CARRY(E1_q[3] & E1L7);


--E1_q[2] is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|q[2]
--operation mode is up_dn_cntr

E1_q[2]_lut_out = E1_q[2] $ E1L5;
E1_q[2] = DFFEA(E1_q[2]_lut_out, GLOBAL(pci_clk), , , , , );

--E1L7 is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT
--operation mode is up_dn_cntr

E1L7 = CARRY(E1_q[2] & E1L5);


--E1_q[1] is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|q[1]
--operation mode is up_dn_cntr

E1_q[1]_lut_out = E1_q[1] $ E1L3;
E1_q[1] = DFFEA(E1_q[1]_lut_out, GLOBAL(pci_clk), , , , , );

--E1L5 is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT
--operation mode is up_dn_cntr

E1L5 = CARRY(E1_q[1] & E1L3);


--E1_q[0] is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|q[0]
--operation mode is up_dn_cntr

E1_q[0]_lut_out = !E1_q[0];
E1_q[0] = DFFEA(E1_q[0]_lut_out, GLOBAL(pci_clk), , , , , );

--E1L3 is lpm_counter:dpm_cdiv|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT
--operation mode is up_dn_cntr

E1L3 = CARRY(E1_q[0]);


--Y1L62 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pg:parity_gen|parc[11]~7
--operation mode is arithmetic

Y1L62 = AMPP_FUNCTION(pci_cben_3, pci_cben_2, Y1_parc[10]);

--Y1_parc[11] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pg:parity_gen|parc[11]
--operation mode is arithmetic

Y1_parc[11] = AMPP_FUNCTION(pci_cben_3, pci_cben_2, Y1_parc[10]);


--Z1L43 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|$00214~11
--operation mode is arithmetic

Z1L43 = AMPP_FUNCTION(A1L734, Z1_LW_DONE_lc[1]);

--Z1_$00214 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|$00214
--operation mode is arithmetic

Z1_$00214 = AMPP_FUNCTION(A1L734, Z1_LW_DONE_lc[1]);


--Z1L82 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|$00209~11
--operation mode is arithmetic

Z1L82 = AMPP_FUNCTION(A1L734, Z1_LW_LXFR_lc[3], Z1_$00210);

--Z1_$00209 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|$00209
--operation mode is arithmetic

Z1_$00209 = AMPP_FUNCTION(A1L734, Z1_LW_LXFR_lc[3], Z1_$00210);


--Y1L42 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pg:parity_gen|parc[10]~8
--operation mode is arithmetic

Y1L42 = AMPP_FUNCTION(Y1_par[9], Y1_par[8]);

--Y1_parc[10] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pg:parity_gen|parc[10]
--operation mode is arithmetic

Y1_parc[10] = AMPP_FUNCTION(Y1_par[9], Y1_par[8]);


--W1L85 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00259~11
--operation mode is arithmetic

W1L85 = AMPP_FUNCTION(A1L944, W1_MR_LWAIT_lc1);

--W1_$00259 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00259
--operation mode is arithmetic

W1_$00259 = AMPP_FUNCTION(A1L944, W1_MR_LWAIT_lc1);


--W1L06 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00262~11
--operation mode is arithmetic

W1L06 = AMPP_FUNCTION(A1L944, W1_MR_LLWAIT_r1_lc1);

--W1_$00262 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00262
--operation mode is arithmetic

W1_$00262 = AMPP_FUNCTION(A1L944, W1_MR_LLWAIT_r1_lc1);


--W1L26 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00263~11
--operation mode is arithmetic

W1L26 = AMPP_FUNCTION(A1L944, W1_MR_LPXFR);

--W1_$00263 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00263
--operation mode is arithmetic

W1_$00263 = AMPP_FUNCTION(A1L944, W1_MR_LPXFR);


--W1L46 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00266~9
--operation mode is arithmetic

W1L46 = AMPP_FUNCTION(A1L944, W1_MR_LLXFR_r2_d_lc1);

--W1_$00266 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00266
--operation mode is arithmetic

W1_$00266 = AMPP_FUNCTION(A1L944, W1_MR_LLXFR_r2_d_lc1);


--W1L66 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00269~11
--operation mode is arithmetic

W1L66 = AMPP_FUNCTION(A1L944, W1_MR_END_d_lc2);

--W1_$00269 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00269
--operation mode is arithmetic

W1_$00269 = AMPP_FUNCTION(A1L944, W1_MR_END_d_lc2);


--W1L21 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00077~11
--operation mode is arithmetic

W1L21 = AMPP_FUNCTION(A1L734, W1_no_op_reg[7]);

--W1_$00077 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00077
--operation mode is arithmetic

W1_$00077 = AMPP_FUNCTION(A1L734, W1_no_op_reg[7]);


--Z1L84 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|$00236~18
--operation mode is arithmetic

Z1L84 = AMPP_FUNCTION(A1L234, A1L734, Z1_$00237);

--Z1_$00236 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|$00236
--operation mode is arithmetic

Z1_$00236 = AMPP_FUNCTION(A1L234, A1L734, Z1_$00237);


--Z1L23 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|$00211~18
--operation mode is arithmetic

Z1L23 = AMPP_FUNCTION(A1L734, Z1_LW_LXFR);

--Z1_$00211 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|$00211
--operation mode is arithmetic

Z1_$00211 = AMPP_FUNCTION(A1L734, Z1_LW_LXFR);


--Z1L93 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|$00225~18
--operation mode is arithmetic

Z1L93 = AMPP_FUNCTION(A1L234, A1L734, Z1_$00226);

--Z1_$00225 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|$00225
--operation mode is arithmetic

Z1_$00225 = AMPP_FUNCTION(A1L234, A1L734, Z1_$00226);


--Z1L01 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|$00137~11
--operation mode is arithmetic

Z1L01 = AMPP_FUNCTION(Z1_lt_ldata_ack_r, Z1_io_cyc, Z1_$00138);

--Z1_$00137 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|$00137
--operation mode is arithmetic

Z1_$00137 = AMPP_FUNCTION(Z1_lt_ldata_ack_r, Z1_io_cyc, Z1_$00138);


--W1L81 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00088~4
--operation mode is arithmetic

W1L81 = AMPP_FUNCTION(A1L944, W1_wr_rdn);

--W1_$00088 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00088
--operation mode is arithmetic

W1_$00088 = AMPP_FUNCTION(A1L944, W1_wr_rdn);


--W1L41 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00078~11
--operation mode is arithmetic

W1L41 = AMPP_FUNCTION(A1L734, BB1_cmd_reg[2]);

--W1_$00078 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00078
--operation mode is arithmetic

W1_$00078 = AMPP_FUNCTION(A1L734, BB1_cmd_reg[2]);


--W1L35 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00244~18
--operation mode is arithmetic

W1L35 = AMPP_FUNCTION(A1L944, W1_MW_LAST);

--W1_$00244 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00244
--operation mode is arithmetic

W1_$00244 = AMPP_FUNCTION(A1L944, W1_MW_LAST);


--Z1L05 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|$00237~1
--operation mode is arithmetic

Z1L05 = AMPP_FUNCTION(Z1_LR_PXFR_lc[2]);

--Z1_$00237 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|$00237
--operation mode is arithmetic

Z1_$00237 = AMPP_FUNCTION(Z1_LR_PXFR_lc[2]);


--Z1L34 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|$00230~18
--operation mode is arithmetic

Z1L34 = AMPP_FUNCTION(A1L234, A1L734, Z1_$00231);

--Z1_$00230 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|$00230
--operation mode is arithmetic

Z1_$00230 = AMPP_FUNCTION(A1L234, A1L734, Z1_$00231);


--Z1L14 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|$00226~1
--operation mode is arithmetic

Z1L14 = AMPP_FUNCTION(Z1_LR_LXFR_lc[4]);

--Z1_$00226 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|$00226
--operation mode is arithmetic

Z1_$00226 = AMPP_FUNCTION(Z1_LR_LXFR_lc[4]);


--Z1L21 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|$00138~3
--operation mode is arithmetic

Z1L21 = AMPP_FUNCTION(AB3_REG, Z1_lt_rdynR_R);

--Z1_$00138 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|$00138
--operation mode is arithmetic

Z1_$00138 = AMPP_FUNCTION(AB3_REG, Z1_lt_rdynR_R);


--Y2L42 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pg:parity_gen64|parc[10]~8
--operation mode is arithmetic

Y2L42 = AMPP_FUNCTION(Y2_par[9], Y2_par[8]);

--Y2_parc[10] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pg:parity_gen64|parc[10]
--operation mode is arithmetic

Y2_parc[10] = AMPP_FUNCTION(Y2_par[9], Y2_par[8]);


--Z1L5 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|$00103~11
--operation mode is arithmetic

Z1L5 = AMPP_FUNCTION(A1L734, Z1_no_op_reg[1]);

--Z1_$00103 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|$00103
--operation mode is arithmetic

Z1_$00103 = AMPP_FUNCTION(A1L734, Z1_no_op_reg[1]);


--W1L65 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00253~11
--operation mode is arithmetic

W1L65 = AMPP_FUNCTION(A1L944, W1_no_op_reg[5]);

--W1_$00253 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00253
--operation mode is arithmetic

W1_$00253 = AMPP_FUNCTION(A1L944, W1_no_op_reg[5]);


--W1L61 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00080~11
--operation mode is arithmetic

W1L61 = AMPP_FUNCTION(A1L944, W1_trdy_det_set);

--W1_$00080 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00080
--operation mode is arithmetic

W1_$00080 = AMPP_FUNCTION(A1L944, W1_trdy_det_set);


--W1L6 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00064~11
--operation mode is arithmetic

W1L6 = AMPP_FUNCTION(pci_gntn, W1L202);

--W1_$00064 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00064
--operation mode is arithmetic

W1_$00064 = AMPP_FUNCTION(pci_gntn, W1L202);


--dpm_dec_reg_rdata_LED_8 is dpm_dec_reg_rdata_LED_8
--operation mode is normal

dpm_dec_reg_rdata_LED_8_lut_out = U1_low_ad_IR_data[8] & (U1L232 # U1L032) # !U1_low_ad_IR_data[8] & !U1L232 & U1L032;
dpm_dec_reg_rdata_LED_8 = DFFEA(dpm_dec_reg_rdata_LED_8_lut_out, GLOBAL(pci_clk), pci_rstn, , A1L271, , );


--dpm_ni2f_reg_not_empty is dpm_ni2f_reg_not_empty
--operation mode is normal

dpm_ni2f_reg_not_empty_lut_out = dpm_ni2f_reg_sm_0;
dpm_ni2f_reg_not_empty = DFFEA(dpm_ni2f_reg_not_empty_lut_out, CLK50M, !ix2000_lc, , ix2005_lc, , );


--dpm_ni2f_reg_cdata_0 is dpm_ni2f_reg_cdata_0
--operation mode is normal

dpm_ni2f_reg_cdata_0_lut_out = R1_q[0] # !dpm_ni2f_reg_sm_2;
dpm_ni2f_reg_cdata_0 = DFFEA(dpm_ni2f_reg_cdata_0_lut_out, CLK50M, , , ix2008_lc, , );


--dpm_ni2f_reg_cdata_1 is dpm_ni2f_reg_cdata_1
--operation mode is normal

dpm_ni2f_reg_cdata_1_lut_out = !dpm_ni2f_reg_sm_2 # !R1_q[1];
dpm_ni2f_reg_cdata_1 = DFFEA(dpm_ni2f_reg_cdata_1_lut_out, CLK50M, , , ix2008_lc, , );


--sg_reg_mx_q is sg_reg_mx_q
--operation mode is normal

sg_reg_mx_q_lut_out = !sg_reg_mx_q;
sg_reg_mx_q = DFFEA(sg_reg_mx_q_lut_out, E1_q[15], , , , , );


--dpm_ni2f_reg_addr_0 is dpm_ni2f_reg_addr_0
--operation mode is normal

dpm_ni2f_reg_addr_0_lut_out = dpm_ni2f_reg_sm_5 # dpm_ni2f_reg_sm_2 & E7_q[0];
dpm_ni2f_reg_addr_0 = DFFEA(dpm_ni2f_reg_addr_0_lut_out, CLK50M, , , A1L381, , );


--dpm_ni2f_reg_addr_1 is dpm_ni2f_reg_addr_1
--operation mode is normal

dpm_ni2f_reg_addr_1_lut_out = E7_q[1] & (dpm_ni2f_reg_sm_2 # Z1L212) # !E7_q[1] & !dpm_ni2f_reg_sm_2 & Z1L212;
dpm_ni2f_reg_addr_1 = DFFEA(dpm_ni2f_reg_addr_1_lut_out, CLK50M, , , A1L381, , );


--dpm_ni2f_reg_addr_2 is dpm_ni2f_reg_addr_2
--operation mode is normal

dpm_ni2f_reg_addr_2_lut_out = E7_q[2] & (dpm_ni2f_reg_sm_2 # Z1L312) # !E7_q[2] & !dpm_ni2f_reg_sm_2 & Z1L312;
dpm_ni2f_reg_addr_2 = DFFEA(dpm_ni2f_reg_addr_2_lut_out, CLK50M, , , A1L381, , );


--dpm_ni2f_reg_addr_3 is dpm_ni2f_reg_addr_3
--operation mode is normal

dpm_ni2f_reg_addr_3_lut_out = E7_q[3] & (dpm_ni2f_reg_sm_2 # Z1L412) # !E7_q[3] & !dpm_ni2f_reg_sm_2 & Z1L412;
dpm_ni2f_reg_addr_3 = DFFEA(dpm_ni2f_reg_addr_3_lut_out, CLK50M, , , A1L381, , );


--dpm_ni2f_reg_addr_4 is dpm_ni2f_reg_addr_4
--operation mode is normal

dpm_ni2f_reg_addr_4_lut_out = E7_q[4] & (dpm_ni2f_reg_sm_2 # Z1L512) # !E7_q[4] & !dpm_ni2f_reg_sm_2 & Z1L512;
dpm_ni2f_reg_addr_4 = DFFEA(dpm_ni2f_reg_addr_4_lut_out, CLK50M, , , A1L381, , );


--dpm_ni2f_reg_addr_5 is dpm_ni2f_reg_addr_5
--operation mode is normal

dpm_ni2f_reg_addr_5_lut_out = E7_q[5] & (dpm_ni2f_reg_sm_2 # Z1L612) # !E7_q[5] & !dpm_ni2f_reg_sm_2 & Z1L612;
dpm_ni2f_reg_addr_5 = DFFEA(dpm_ni2f_reg_addr_5_lut_out, CLK50M, , , A1L381, , );


--dpm_ni2f_reg_addr_6 is dpm_ni2f_reg_addr_6
--operation mode is normal

dpm_ni2f_reg_addr_6_lut_out = E7_q[6] & (dpm_ni2f_reg_sm_2 # Z1L712) # !E7_q[6] & !dpm_ni2f_reg_sm_2 & Z1L712;
dpm_ni2f_reg_addr_6 = DFFEA(dpm_ni2f_reg_addr_6_lut_out, CLK50M, , , A1L381, , );


--dpm_ni2f_reg_addr_7 is dpm_ni2f_reg_addr_7
--operation mode is normal

dpm_ni2f_reg_addr_7_lut_out = E7_q[7] & (dpm_ni2f_reg_sm_2 # Z1L812) # !E7_q[7] & !dpm_ni2f_reg_sm_2 & Z1L812;
dpm_ni2f_reg_addr_7 = DFFEA(dpm_ni2f_reg_addr_7_lut_out, CLK50M, , , A1L381, , );


--dpm_ni2f_reg_addr_8 is dpm_ni2f_reg_addr_8
--operation mode is normal

dpm_ni2f_reg_addr_8_lut_out = E7_q[8] & (dpm_ni2f_reg_sm_2 # Z1L912) # !E7_q[8] & !dpm_ni2f_reg_sm_2 & Z1L912;
dpm_ni2f_reg_addr_8 = DFFEA(dpm_ni2f_reg_addr_8_lut_out, CLK50M, , , A1L381, , );


--dpm_ni2f_reg_addr_9 is dpm_ni2f_reg_addr_9
--operation mode is normal

dpm_ni2f_reg_addr_9_lut_out = E7_q[9] & (dpm_ni2f_reg_sm_2 # Z1L022) # !E7_q[9] & !dpm_ni2f_reg_sm_2 & Z1L022;
dpm_ni2f_reg_addr_9 = DFFEA(dpm_ni2f_reg_addr_9_lut_out, CLK50M, , , A1L381, , );


--dpm_ni2f_reg_addr_10 is dpm_ni2f_reg_addr_10
--operation mode is normal

dpm_ni2f_reg_addr_10_lut_out = E7_q[10] & (dpm_ni2f_reg_sm_2 # Z1L122) # !E7_q[10] & !dpm_ni2f_reg_sm_2 & Z1L122;
dpm_ni2f_reg_addr_10 = DFFEA(dpm_ni2f_reg_addr_10_lut_out, CLK50M, , , A1L381, , );


--dpm_ni2f_reg_addr_11 is dpm_ni2f_reg_addr_11
--operation mode is normal

dpm_ni2f_reg_addr_11_lut_out = E7_q[11] & (dpm_ni2f_reg_sm_2 # Z1L222) # !E7_q[11] & !dpm_ni2f_reg_sm_2 & Z1L222;
dpm_ni2f_reg_addr_11 = DFFEA(dpm_ni2f_reg_addr_11_lut_out, CLK50M, , , A1L381, , );


--dpm_ni2f_reg_addr_12 is dpm_ni2f_reg_addr_12
--operation mode is normal

dpm_ni2f_reg_addr_12_lut_out = E7_q[12] & (dpm_ni2f_reg_sm_2 # Z1L322) # !E7_q[12] & !dpm_ni2f_reg_sm_2 & Z1L322;
dpm_ni2f_reg_addr_12 = DFFEA(dpm_ni2f_reg_addr_12_lut_out, CLK50M, , , A1L381, , );


--dpm_ni2f_reg_addr_13 is dpm_ni2f_reg_addr_13
--operation mode is normal

dpm_ni2f_reg_addr_13_lut_out = E7_q[13] & (dpm_ni2f_reg_sm_2 # Z1L422) # !E7_q[13] & !dpm_ni2f_reg_sm_2 & Z1L422;
dpm_ni2f_reg_addr_13 = DFFEA(dpm_ni2f_reg_addr_13_lut_out, CLK50M, , , A1L381, , );


--dpm_ni2f_reg_addr_14 is dpm_ni2f_reg_addr_14
--operation mode is normal

dpm_ni2f_reg_addr_14_lut_out = E7_q[14] & (dpm_ni2f_reg_sm_2 # Z1L522) # !E7_q[14] & !dpm_ni2f_reg_sm_2 & Z1L522;
dpm_ni2f_reg_addr_14 = DFFEA(dpm_ni2f_reg_addr_14_lut_out, CLK50M, , , A1L381, , );


--dpm_ni2f_reg_addr_15 is dpm_ni2f_reg_addr_15
--operation mode is normal

dpm_ni2f_reg_addr_15_lut_out = E7_q[15] & (dpm_ni2f_reg_sm_2 # Z1L622) # !E7_q[15] & !dpm_ni2f_reg_sm_2 & Z1L622;
dpm_ni2f_reg_addr_15 = DFFEA(dpm_ni2f_reg_addr_15_lut_out, CLK50M, , , A1L381, , );


--dpm_ni2f_reg_addr_16 is dpm_ni2f_reg_addr_16
--operation mode is normal

dpm_ni2f_reg_addr_16_lut_out = E7_q[16] & (dpm_ni2f_reg_sm_2 # Z1L722) # !E7_q[16] & !dpm_ni2f_reg_sm_2 & Z1L722;
dpm_ni2f_reg_addr_16 = DFFEA(dpm_ni2f_reg_addr_16_lut_out, CLK50M, , , A1L381, , );


--dpm_ni2f_reg_addr_17 is dpm_ni2f_reg_addr_17
--operation mode is normal

dpm_ni2f_reg_addr_17_lut_out = E7_q[17] & (dpm_ni2f_reg_sm_2 # Z1L822) # !E7_q[17] & !dpm_ni2f_reg_sm_2 & Z1L822;
dpm_ni2f_reg_addr_17 = DFFEA(dpm_ni2f_reg_addr_17_lut_out, CLK50M, , , A1L381, , );


--dpm_ni2f_reg_we_n is dpm_ni2f_reg_we_n
--operation mode is normal

dpm_ni2f_reg_we_n_lut_out = dpm_ni2f_reg_sm_2 & (dpm_ni2f_reg_rdreq_fifo # !dpm_ni2f_reg_sm_1) # !dpm_ni2f_reg_sm_2 & dpm_ni2f_reg_sm_1 & dpm_ni2f_reg_rdreq_fifo;
dpm_ni2f_reg_we_n = DFFEA(dpm_ni2f_reg_we_n_lut_out, CLK50M, !ix2000_lc, , , , );


--dpm_ni2f_reg_ce_n is dpm_ni2f_reg_ce_n
--operation mode is normal

dpm_ni2f_reg_ce_n_lut_out = !dpm_ni2f_reg_sm_11 & dpm_ni2f_reg_sm_0 & (dpm_ni2f_reg_rdreq_fifo # !dpm_ni2f_reg_sm_1);
dpm_ni2f_reg_ce_n = DFFEA(dpm_ni2f_reg_ce_n_lut_out, CLK50M, !ix2000_lc, , , , );


--dpm_ni2f_reg_clk_sram_i is dpm_ni2f_reg_clk_sram_i
--operation mode is normal

dpm_ni2f_reg_clk_sram_i_lut_out = !A1L891;
dpm_ni2f_reg_clk_sram_i = DFFEA(dpm_ni2f_reg_clk_sram_i_lut_out, CLK50M, !ix2000_lc, , , , );


--dpm_ni2f_reg_re_n is dpm_ni2f_reg_re_n
--operation mode is normal

dpm_ni2f_reg_re_n_lut_out = (!dpm_ni2f_reg_sm_1 & dpm_ni2f_reg_sm_0) & CASCADE(ix2055);
dpm_ni2f_reg_re_n = DFFEA(dpm_ni2f_reg_re_n_lut_out, CLK50M, !ix2000_lc, , , , );


--U1_low_ad_IR_data[8] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_IR_data[8]
--operation mode is normal

U1_low_ad_IR_data[8] = AMPP_FUNCTION(U1_ad_IR_ce_data, pci_ad_8, pci_rstn, GLOBAL(pci_clk));


--dpm_ni2f_reg_sm_0 is dpm_ni2f_reg_sm_0
--operation mode is normal

dpm_ni2f_reg_sm_0_lut_out = (dpm_ni2f_reg_pci_rd_req_s # !dpm_ni2f_reg_sm_11 & (dpm_ni2f_reg_rdempty_s # dpm_ni2f_reg_sm_0)) & CASCADE(ix2057);
dpm_ni2f_reg_sm_0 = DFFEA(dpm_ni2f_reg_sm_0_lut_out, CLK50M, !ix2000_lc, , , , );


--dpm_ni2f_reg_sm_2 is dpm_ni2f_reg_sm_2
--operation mode is normal

dpm_ni2f_reg_sm_2_lut_out = dpm_ni2f_reg_sm_1 & dpm_ni2f_reg_rdreq_fifo;
dpm_ni2f_reg_sm_2 = DFFEA(dpm_ni2f_reg_sm_2_lut_out, CLK50M, !ix2000_lc, , , , );


--R1_q[0] is nififo:dpm_ni2f_fifo_n|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|altdpram:dpram4|q[0]
R1_q[0]_data_in = ADC1_D[0];
R1_q[0]_clock_0 = !ADC2_D[2];
R1_q[0]_clock_1 = CLK50M;
R1_q[0]_clear_0 = dpm_ni2f_reg_sreset120;
R1_q[0]_clock_enable_1 = dpm_ni2f_reg_rdreq_fifo;
R1_q[0]_write_address = WR_ADDR(L1_power_modified_counter_values[0], L1_power_modified_counter_values[1], L1_power_modified_counter_values[2], L1_power_modified_counter_values[3], L1_power_modified_counter_values[4], L1_power_modified_counter_values[5], L1_power_modified_counter_values[6], L1_power_modified_counter_values[7], L1_power_modified_counter_values[8], L1_power_modified_counter_values[9], L1_power_modified_counter_values[10]);
R1_q[0]_read_address = RD_ADDR(R1L4, M1_power_modified_counter_values[1], M1_power_modified_counter_values[2], M1_power_modified_counter_values[3], M1_power_modified_counter_values[4], M1_power_modified_counter_values[5], M1_power_modified_counter_values[6], M1_power_modified_counter_values[7], M1_power_modified_counter_values[8], M1_power_modified_counter_values[9], M1_power_modified_counter_values[10]);
R1_q[0] = MEMORY_SEGMENT(R1_q[0]_data_in, VCC, R1_q[0]_clock_0, R1_q[0]_clock_1, R1_q[0]_clear_0, , R1_q[0]_clock_enable_1, VCC, R1_q[0]_write_address, R1_q[0]_read_address);


--R1_q[1] is nififo:dpm_ni2f_fifo_n|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|altdpram:dpram4|q[1]
R1_q[1]_data_in = ADC1_D[1];
R1_q[1]_clock_0 = !ADC2_D[2];
R1_q[1]_clock_1 = CLK50M;
R1_q[1]_clear_0 = dpm_ni2f_reg_sreset120;
R1_q[1]_clock_enable_1 = dpm_ni2f_reg_rdreq_fifo;
R1_q[1]_write_address = WR_ADDR(L1_power_modified_counter_values[0], L1_power_modified_counter_values[1], L1_power_modified_counter_values[2], L1_power_modified_counter_values[3], L1_power_modified_counter_values[4], L1_power_modified_counter_values[5], L1_power_modified_counter_values[6], L1_power_modified_counter_values[7], L1_power_modified_counter_values[8], L1_power_modified_counter_values[9], L1_power_modified_counter_values[10]);
R1_q[1]_read_address = RD_ADDR(R1L4, M1_power_modified_counter_values[1], M1_power_modified_counter_values[2], M1_power_modified_counter_values[3], M1_power_modified_counter_values[4], M1_power_modified_counter_values[5], M1_power_modified_counter_values[6], M1_power_modified_counter_values[7], M1_power_modified_counter_values[8], M1_power_modified_counter_values[9], M1_power_modified_counter_values[10]);
R1_q[1] = MEMORY_SEGMENT(R1_q[1]_data_in, VCC, R1_q[1]_clock_0, R1_q[1]_clock_1, R1_q[1]_clear_0, , R1_q[1]_clock_enable_1, VCC, R1_q[1]_write_address, R1_q[1]_read_address);


--W1_req_or is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|req_or
--operation mode is normal

W1_req_or = AMPP_FUNCTION(W1_req_or_lc[1], pci_gntn, W1_req_or_lc[2], pci_rstn, GLOBAL(pci_clk));


--X1_serr_or is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pk:parity_Chk|serr_or
--operation mode is normal

X1_serr_or = AMPP_FUNCTION(X1_serr_or_lc, A1L044, X1_xxlad[11], pci_rstn, GLOBAL(pci_clk));


--ix2237_lc is ix2237_lc
--operation mode is normal

ix2237_lc = sg_reg_mx_q & ix2051_lc # !sg_reg_mx_q & ix2050_lc;


--ix2236_lc is ix2236_lc
--operation mode is normal

ix2236_lc = sg_reg_mx_q & ix2049_lc # !sg_reg_mx_q & ix2048_lc;


--ix2235_lc is ix2235_lc
--operation mode is normal

ix2235_lc = sg_reg_mx_q & ix2047_lc # !sg_reg_mx_q & ix2046_lc;


--ix2234_lc is ix2234_lc
--operation mode is normal

ix2234_lc = sg_reg_mx_q & ix2045_lc # !sg_reg_mx_q & ix2044_lc;


--ix2233_lc is ix2233_lc
--operation mode is normal

ix2233_lc = sg_reg_mx_q & ix2043_lc # !sg_reg_mx_q & ix2042_lc;


--ix2232_lc is ix2232_lc
--operation mode is normal

ix2232_lc = sg_reg_mx_q & ix2041_lc # !sg_reg_mx_q & ix2040_lc;


--ix2231_lc is ix2231_lc
--operation mode is normal

ix2231_lc = sg_reg_mx_q & ix2039_lc # !sg_reg_mx_q & ix2038_lc;


--dpm_ni2f_reg_sm_5 is dpm_ni2f_reg_sm_5
--operation mode is normal

dpm_ni2f_reg_sm_5_lut_out = dpm_ni2f_reg_sm_4;
dpm_ni2f_reg_sm_5 = DFFEA(dpm_ni2f_reg_sm_5_lut_out, CLK50M, !ix2000_lc, , , , );


--dpm_ni2f_reg_sm_1 is dpm_ni2f_reg_sm_1
--operation mode is normal

dpm_ni2f_reg_sm_1_lut_out = !A1L871;
dpm_ni2f_reg_sm_1 = DFFEA(dpm_ni2f_reg_sm_1_lut_out, CLK50M, !ix2000_lc, , , , );


--dpm_ni2f_reg_rdreq_fifo is dpm_ni2f_reg_rdreq_fifo
--operation mode is normal

dpm_ni2f_reg_rdreq_fifo_lut_out = H2_b_non_empty & (ix2067_lc # dpm_ni2f_reg_sm_2);
dpm_ni2f_reg_rdreq_fifo = DFFEA(dpm_ni2f_reg_rdreq_fifo_lut_out, CLK50M, , , ix2003_lc, , );


--dpm_ni2f_reg_sm_11 is dpm_ni2f_reg_sm_11
--operation mode is normal

dpm_ni2f_reg_sm_11_lut_out = dpm_ni2f_reg_sm_10 # dpm_ni2f_reg_sm_11 & dpm_ni2f_reg_pci_rd_req_s;
dpm_ni2f_reg_sm_11 = DFFEA(dpm_ni2f_reg_sm_11_lut_out, CLK50M, !ix2000_lc, , , , );


--U1_high_ad_IR_data[8] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_IR_data[8]
--operation mode is normal

U1_high_ad_IR_data[8] = AMPP_FUNCTION(U1_ad_IR_ce_data, W1_ad_oer, U1_high_ad_or[40], Z1_adoe, pci_rstn, GLOBAL(pci_clk));


--U1L032 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|l_dato[40]~50
--operation mode is normal

U1L032 = AMPP_FUNCTION(U1_high_ad_IR_data[8], U1_low_ad_IR_data[8], U1_local_dat_sel);


--Z1_lt_ldata_ack_r is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_ldata_ack_r
--operation mode is normal

Z1_lt_ldata_ack_r = AMPP_FUNCTION(Z1_lt_ldata_ack_r_ena, Z1_lt_ldata_ack_r_d[1], Z1_lt_ldata_ack_r_d[5], Z1_lt_ldata_ack_r, pci_rstn, GLOBAL(pci_clk));


--W1_lm_ldata_ack is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|lm_ldata_ack
--operation mode is normal

W1_lm_ldata_ack = AMPP_FUNCTION(W1_lm_ldata_ack_ena3, W1_MS_ENA, W1_lm_ldata_ack_lc[4], pci_gntn, pci_rstn, GLOBAL(pci_clk));


--U1L232 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|l_ldat_ack~6
--operation mode is normal

U1L232 = AMPP_FUNCTION(Z1_lt_ldata_ack_r, W1_lm_ldata_ack, Z1_$00109);


--dpm_dec_reg_soft_rst_n is dpm_dec_reg_soft_rst_n
--operation mode is normal

dpm_dec_reg_soft_rst_n_lut_out = !A1L471;
dpm_dec_reg_soft_rst_n = DFFEA(dpm_dec_reg_soft_rst_n_lut_out, GLOBAL(pci_clk), pci_rstn, , , , );


--ix2000_lc is ix2000_lc
--operation mode is normal

ix2000_lc = !dpm_dec_reg_soft_rst_n # !pci_rstn;


--ix2005_lc is ix2005_lc
--operation mode is normal

ix2005_lc = dpm_ni2f_reg_sm_0 # !dpm_dec_reg_soft_rst_n;


--dpm_ni2f_reg_sreset120 is dpm_ni2f_reg_sreset120
--operation mode is normal

dpm_ni2f_reg_sreset120_lut_out = !dpm_dec_reg_soft_rst_n;
dpm_ni2f_reg_sreset120 = DFFEA(dpm_ni2f_reg_sreset120_lut_out, CLK50M, , , , , );


--ix2008_lc is ix2008_lc
--operation mode is normal

ix2008_lc = dpm_ni2f_reg_sm_2 # dpm_ni2f_reg_sreset120;


--U1_low_ad_or[0] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_or[0]
--operation mode is normal

U1_low_ad_or[0] = AMPP_FUNCTION(V1_ad_ce[0], A1L171, U1_mstr_trg_low, U1L563, pci_rstn, GLOBAL(pci_clk));


--Z1_adoe is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|adoe
--operation mode is normal

Z1_adoe = AMPP_FUNCTION(Z1_TS_IDLE_NOT, Z1_TS_TURN_AR, AB5_REG, pci_rstn, GLOBAL(pci_clk), Z1L2);


--W1_ad_oer is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|ad_oer
--operation mode is normal

W1_ad_oer = AMPP_FUNCTION(A1L744, A1L944, GND, W1_ad_oer_lc3, !pci_rstn, GLOBAL(pci_clk), W1L48);


--U1_ad_tri_oe is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|ad_tri_oe
--operation mode is normal

U1_ad_tri_oe = AMPP_FUNCTION(Z1_adoe, W1_ad_oer);


--U1_low_ad_or[1] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_or[1]
--operation mode is normal

U1_low_ad_or[1] = AMPP_FUNCTION(V1_ad_ce[1], A1L071, U1_mstr_trg_low, U1L663, pci_rstn, GLOBAL(pci_clk));


--U1_low_ad_or[2] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_or[2]
--operation mode is normal

U1_low_ad_or[2] = AMPP_FUNCTION(V1_ad_ce[2], A1L961, U1_mstr_trg_low, U1L763, pci_rstn, GLOBAL(pci_clk));


--U1_low_ad_or[3] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_or[3]
--operation mode is normal

U1_low_ad_or[3] = AMPP_FUNCTION(V1_ad_ce[3], A1L861, U1_mstr_trg_low, U1L863, pci_rstn, GLOBAL(pci_clk));


--U1_low_ad_or[4] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_or[4]
--operation mode is normal

U1_low_ad_or[4] = AMPP_FUNCTION(V1_ad_ce[4], A1L761, U1_mstr_trg_low, U1L963, pci_rstn, GLOBAL(pci_clk));


--U1_low_ad_or[5] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_or[5]
--operation mode is normal

U1_low_ad_or[5] = AMPP_FUNCTION(V1_ad_ce[5], A1L661, U1_mstr_trg_low, U1L073, pci_rstn, GLOBAL(pci_clk));


--U1_low_ad_or[6] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_or[6]
--operation mode is normal

U1_low_ad_or[6] = AMPP_FUNCTION(V1_ad_ce[6], A1L561, U1_mstr_trg_low, U1L173, pci_rstn, GLOBAL(pci_clk));


--U1_low_ad_or[7] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_or[7]
--operation mode is normal

U1_low_ad_or[7] = AMPP_FUNCTION(V1_ad_ce[7], A1L461, U1_mstr_trg_low, U1L273, pci_rstn, GLOBAL(pci_clk));


--U1_low_ad_or[8] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_or[8]
--operation mode is normal

U1_low_ad_or[8] = AMPP_FUNCTION(V1_ad_ce[8], U1_mstr_trg_low, A1L361, U1L373, pci_rstn, GLOBAL(pci_clk));


--U1_low_ad_or[9] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_or[9]
--operation mode is normal

U1_low_ad_or[9] = AMPP_FUNCTION(V1_ad_ce[9], A1L261, U1_mstr_trg_low, U1L473, pci_rstn, GLOBAL(pci_clk));


--U1_low_ad_or[10] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_or[10]
--operation mode is normal

U1_low_ad_or[10] = AMPP_FUNCTION(V1_ad_ce[10], U1_mstr_trg_low, A1L161, U1L573, pci_rstn, GLOBAL(pci_clk));


--U1_low_ad_or[11] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_or[11]
--operation mode is normal

U1_low_ad_or[11] = AMPP_FUNCTION(V1_ad_ce[11], U1_mstr_trg_low, A1L061, U1L673, pci_rstn, GLOBAL(pci_clk));


--U1_low_ad_or[12] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_or[12]
--operation mode is normal

U1_low_ad_or[12] = AMPP_FUNCTION(V1_ad_ce[12], U1_mstr_trg_low, A1L951, U1L773, pci_rstn, GLOBAL(pci_clk));


--U1_low_ad_or[13] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_or[13]
--operation mode is normal

U1_low_ad_or[13] = AMPP_FUNCTION(V1_ad_ce[13], U1_mstr_trg_low, A1L851, U1L873, pci_rstn, GLOBAL(pci_clk));


--U1_low_ad_or[14] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_or[14]
--operation mode is normal

U1_low_ad_or[14] = AMPP_FUNCTION(V1_ad_ce[14], U1_mstr_trg_low, A1L751, U1L973, pci_rstn, GLOBAL(pci_clk));


--U1_low_ad_or[15] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_or[15]
--operation mode is normal

U1_low_ad_or[15] = AMPP_FUNCTION(V1_ad_ce[15], U1_mstr_trg_low, A1L651, U1L083, pci_rstn, GLOBAL(pci_clk));


--U1_low_ad_or[16] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_or[16]
--operation mode is normal

U1_low_ad_or[16] = AMPP_FUNCTION(V1_ad_ce[16], U1_mstr_trg_low, A1L551, U1L183, pci_rstn, GLOBAL(pci_clk));


--U1_low_ad_or[17] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_or[17]
--operation mode is normal

U1_low_ad_or[17] = AMPP_FUNCTION(V1_ad_ce[17], U1_mstr_trg_low, A1L451, U1L283, pci_rstn, GLOBAL(pci_clk));


--U1_low_ad_or[18] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_or[18]
--operation mode is normal

U1_low_ad_or[18] = AMPP_FUNCTION(V1_ad_ce[18], U1_mstr_trg_low, A1L351, U1L383, pci_rstn, GLOBAL(pci_clk));


--U1_low_ad_or[19] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_or[19]
--operation mode is normal

U1_low_ad_or[19] = AMPP_FUNCTION(V1_ad_ce[19], U1_mstr_trg_low, A1L251, U1L483, pci_rstn, GLOBAL(pci_clk));


--U1_low_ad_or[20] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_or[20]
--operation mode is normal

U1_low_ad_or[20] = AMPP_FUNCTION(V1_ad_ce[20], U1_mstr_trg_low, A1L151, U1L583, pci_rstn, GLOBAL(pci_clk));


--U1_low_ad_or[21] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_or[21]
--operation mode is normal

U1_low_ad_or[21] = AMPP_FUNCTION(V1_ad_ce[21], U1_mstr_trg_low, A1L051, U1L683, pci_rstn, GLOBAL(pci_clk));


--U1_low_ad_or[22] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_or[22]
--operation mode is normal

U1_low_ad_or[22] = AMPP_FUNCTION(V1_ad_ce[22], U1_mstr_trg_low, A1L941, U1L783, pci_rstn, GLOBAL(pci_clk));


--U1_low_ad_or[23] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_or[23]
--operation mode is normal

U1_low_ad_or[23] = AMPP_FUNCTION(V1_ad_ce[23], U1_mstr_trg_low, A1L841, U1L883, pci_rstn, GLOBAL(pci_clk));


--U1_low_ad_or[24] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_or[24]
--operation mode is normal

U1_low_ad_or[24] = AMPP_FUNCTION(V1_ad_ce[24], U1_mstr_trg_low, A1L741, U1L983, pci_rstn, GLOBAL(pci_clk));


--U1_low_ad_or[25] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_or[25]
--operation mode is normal

U1_low_ad_or[25] = AMPP_FUNCTION(V1_ad_ce[25], U1_mstr_trg_low, A1L641, U1L093, pci_rstn, GLOBAL(pci_clk));


--U1_low_ad_or[26] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_or[26]
--operation mode is normal

U1_low_ad_or[26] = AMPP_FUNCTION(V1_ad_ce[26], U1_mstr_trg_low, A1L541, U1L193, pci_rstn, GLOBAL(pci_clk));


--U1_low_ad_or[27] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_or[27]
--operation mode is normal

U1_low_ad_or[27] = AMPP_FUNCTION(V1_ad_ce[27], U1_mstr_trg_low, A1L441, U1L293, pci_rstn, GLOBAL(pci_clk));


--U1_low_ad_or[28] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_or[28]
--operation mode is normal

U1_low_ad_or[28] = AMPP_FUNCTION(V1_ad_ce[28], ix2011_lc, U1_mstr_trg_low, U1L393, pci_rstn, GLOBAL(pci_clk));


--U1_low_ad_or[29] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_or[29]
--operation mode is normal

U1_low_ad_or[29] = AMPP_FUNCTION(V1_ad_ce[29], ix2010_lc, U1_mstr_trg_low, U1L493, pci_rstn, GLOBAL(pci_clk));


--U1_low_ad_or[30] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_or[30]
--operation mode is normal

U1_low_ad_or[30] = AMPP_FUNCTION(V1_ad_ce[30], U1_mstr_trg_low, A1L341, U1L593, pci_rstn, GLOBAL(pci_clk));


--U1_low_ad_or[31] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_or[31]
--operation mode is normal

U1_low_ad_or[31] = AMPP_FUNCTION(V1_ad_ce[31], U1_mstr_trg_low, A1L241, U1L693, pci_rstn, GLOBAL(pci_clk));


--U1_low_cben_or[0] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_cben_or[0]
--operation mode is normal

U1_low_cben_or[0] = AMPP_FUNCTION(U1_mstr_cbe_ce, U1_low_mstr_cbe_out_lc1[0], pci_rstn, GLOBAL(pci_clk));


--W1_cbe_oer_not is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|cbe_oer_not
--operation mode is normal

W1_cbe_oer_not = AMPP_FUNCTION(A1L744, A1L944, GND, W1_cbe_oer_r3_d, !pci_rstn, GLOBAL(pci_clk), W1L38);


--U1_low_cben_or[1] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_cben_or[1]
--operation mode is normal

U1_low_cben_or[1] = AMPP_FUNCTION(U1_mstr_cbe_ce, U1_low_mstr_cbe_out_lc1[1], pci_rstn, GLOBAL(pci_clk));


--U1_low_cben_or[2] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_cben_or[2]
--operation mode is normal

U1_low_cben_or[2] = AMPP_FUNCTION(U1_mstr_cbe_ce, U1_low_mstr_cbe_out_lc1[2], pci_rstn, GLOBAL(pci_clk));


--U1_low_cben_or[3] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_cben_or[3]
--operation mode is normal

U1_low_cben_or[3] = AMPP_FUNCTION(U1_mstr_cbe_ce, U1_low_mstr_cbe_out_lc1[3], pci_rstn, GLOBAL(pci_clk));


--Z1_devsel_OR_not is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|devsel_OR_not
--operation mode is normal

Z1_devsel_OR_not = AMPP_FUNCTION(Z1L911, Z1_TS_ADR_VLD, GND, X1_serr_or, !pci_rstn, GLOBAL(pci_clk), Z1L76);


--Z1_targ_oeR_reg is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|targ_oeR_reg
--operation mode is normal

Z1_targ_oeR_reg = AMPP_FUNCTION(Z1_targ_oeR_reg_lc[4], BB1_mbar_hit, Z1_TS_IDLE_NOT, pci_rstn, GLOBAL(pci_clk));


--W1_frame_or_not is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|frame_or_not
--operation mode is normal

W1_frame_or_not = AMPP_FUNCTION(W1_dac_cyc_strobe, W1_MS_ENA, GND, pci_gntn, !pci_rstn, GLOBAL(pci_clk), W1L77);


--W1_irdy_or_not is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|irdy_or_not
--operation mode is normal

W1_irdy_or_not = AMPP_FUNCTION(W1_irdy_or_lc[5], A1L034, GND, W1L92, !pci_rstn, GLOBAL(pci_clk), W1L13);


--W1_irdy_oer is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|irdy_oer
--operation mode is normal

W1_irdy_oer = AMPP_FUNCTION(W1_irdy_oer_lc1, W1_MS_ENA, pci_gntn, pci_rstn, GLOBAL(pci_clk));


--U1_par_or is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|par_or
--operation mode is normal

U1_par_or = AMPP_FUNCTION(pci_cben_0, pci_cben_1, pci_rstn, GLOBAL(pci_clk), Y1_parc[11]);


--U1_par_oeR is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|par_oeR
--operation mode is normal

U1_par_oeR = AMPP_FUNCTION(U1_mstr_par_oe_lc2, W1_MS_ENA, pci_gntn, pci_rstn, GLOBAL(pci_clk));


--X1_perr_or_not is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pk:parity_Chk|perr_or_not
--operation mode is normal

X1_perr_or_not = AMPP_FUNCTION(X1_perr_or_not_lc1, A1L044, GND, X1_xxl[11], !pci_rstn, GLOBAL(pci_clk), X1L3);


--U1_perr_oe_r is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|perr_oe_r
--operation mode is normal

U1_perr_oe_r = AMPP_FUNCTION(W1_perr_oer, AB5_REG, Z1_TS_IDLE_NOT, Z1_TURN_AR_R, pci_rstn, GLOBAL(pci_clk));


--Z1_stop_OR_NOT is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|stop_OR_NOT
--operation mode is normal

Z1_stop_OR_NOT = AMPP_FUNCTION(Z1_stop_or_lc[6], Z1_stop_or_lc[5], GND, A1L234, !pci_rstn, GLOBAL(pci_clk), Z1L26);


--Z1_trdy_OR_NOT is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|trdy_OR_NOT
--operation mode is normal

Z1_trdy_OR_NOT = AMPP_FUNCTION(Z1L363, GND, A1L234, !pci_rstn, GLOBAL(pci_clk), Z1L36);


--dpm_dec_reg_rdata_LED_7 is dpm_dec_reg_rdata_LED_7
--operation mode is normal

dpm_dec_reg_rdata_LED_7_lut_out = U1_low_ad_IR_data[7] & (U1L232 # U1L922) # !U1_low_ad_IR_data[7] & !U1L232 & U1L922;
dpm_dec_reg_rdata_LED_7 = DFFEA(dpm_dec_reg_rdata_LED_7_lut_out, GLOBAL(pci_clk), pci_rstn, , A1L271, , );


--dpm_dec_reg_rdata_LED_6 is dpm_dec_reg_rdata_LED_6
--operation mode is normal

dpm_dec_reg_rdata_LED_6_lut_out = U1_low_ad_IR_data[6] & (U1L232 # U1L822) # !U1_low_ad_IR_data[6] & !U1L232 & U1L822;
dpm_dec_reg_rdata_LED_6 = DFFEA(dpm_dec_reg_rdata_LED_6_lut_out, GLOBAL(pci_clk), pci_rstn, , A1L271, , );


--dpm_dec_reg_rdata_LED_5 is dpm_dec_reg_rdata_LED_5
--operation mode is normal

dpm_dec_reg_rdata_LED_5_lut_out = U1_low_ad_IR_data[5] & (U1L232 # U1L722) # !U1_low_ad_IR_data[5] & !U1L232 & U1L722;
dpm_dec_reg_rdata_LED_5 = DFFEA(dpm_dec_reg_rdata_LED_5_lut_out, GLOBAL(pci_clk), pci_rstn, , A1L271, , );


--dpm_dec_reg_rdata_LED_4 is dpm_dec_reg_rdata_LED_4
--operation mode is normal

dpm_dec_reg_rdata_LED_4_lut_out = U1_low_ad_IR_data[4] & (U1L232 # U1L622) # !U1_low_ad_IR_data[4] & !U1L232 & U1L622;
dpm_dec_reg_rdata_LED_4 = DFFEA(dpm_dec_reg_rdata_LED_4_lut_out, GLOBAL(pci_clk), pci_rstn, , A1L271, , );


--ix2050_lc is ix2050_lc
--operation mode is normal

ix2050_lc = dpm_dec_reg_rdata_LED_4 & !dpm_dec_reg_rdata_LED_7 & (dpm_dec_reg_rdata_LED_6 $ !dpm_dec_reg_rdata_LED_5) # !dpm_dec_reg_rdata_LED_4 & !dpm_dec_reg_rdata_LED_5 & (dpm_dec_reg_rdata_LED_7 $ !dpm_dec_reg_rdata_LED_6);


--dpm_dec_reg_rdata_LED_3 is dpm_dec_reg_rdata_LED_3
--operation mode is normal

dpm_dec_reg_rdata_LED_3_lut_out = U1_low_ad_IR_data[3] & (U1L232 # U1L522) # !U1_low_ad_IR_data[3] & !U1L232 & U1L522;
dpm_dec_reg_rdata_LED_3 = DFFEA(dpm_dec_reg_rdata_LED_3_lut_out, GLOBAL(pci_clk), pci_rstn, , A1L271, , );


--dpm_dec_reg_rdata_LED_2 is dpm_dec_reg_rdata_LED_2
--operation mode is normal

dpm_dec_reg_rdata_LED_2_lut_out = U1_low_ad_IR_data[2] & (U1L232 # U1L422) # !U1_low_ad_IR_data[2] & !U1L232 & U1L422;
dpm_dec_reg_rdata_LED_2 = DFFEA(dpm_dec_reg_rdata_LED_2_lut_out, GLOBAL(pci_clk), pci_rstn, , A1L271, , );


--dpm_dec_reg_rdata_LED_1 is dpm_dec_reg_rdata_LED_1
--operation mode is normal

dpm_dec_reg_rdata_LED_1_lut_out = U1_low_ad_IR_data[1] & (U1L232 # U1L322) # !U1_low_ad_IR_data[1] & !U1L232 & U1L322;
dpm_dec_reg_rdata_LED_1 = DFFEA(dpm_dec_reg_rdata_LED_1_lut_out, GLOBAL(pci_clk), pci_rstn, , A1L271, , );


--dpm_dec_reg_rdata_LED_0 is dpm_dec_reg_rdata_LED_0
--operation mode is normal

dpm_dec_reg_rdata_LED_0_lut_out = U1_low_ad_IR_data[0] & (U1L232 # U1L222) # !U1_low_ad_IR_data[0] & !U1L232 & U1L222;
dpm_dec_reg_rdata_LED_0 = DFFEA(dpm_dec_reg_rdata_LED_0_lut_out, GLOBAL(pci_clk), pci_rstn, , A1L271, , );


--ix2051_lc is ix2051_lc
--operation mode is normal

ix2051_lc = dpm_dec_reg_rdata_LED_0 & !dpm_dec_reg_rdata_LED_3 & (dpm_dec_reg_rdata_LED_2 $ !dpm_dec_reg_rdata_LED_1) # !dpm_dec_reg_rdata_LED_0 & !dpm_dec_reg_rdata_LED_1 & (dpm_dec_reg_rdata_LED_3 $ !dpm_dec_reg_rdata_LED_2);


--ix2048_lc is ix2048_lc
--operation mode is normal

ix2048_lc = dpm_dec_reg_rdata_LED_6 & dpm_dec_reg_rdata_LED_4 & (dpm_dec_reg_rdata_LED_7 $ dpm_dec_reg_rdata_LED_5) # !dpm_dec_reg_rdata_LED_6 & !dpm_dec_reg_rdata_LED_7 & (dpm_dec_reg_rdata_LED_5 # dpm_dec_reg_rdata_LED_4);


--ix2049_lc is ix2049_lc
--operation mode is normal

ix2049_lc = dpm_dec_reg_rdata_LED_2 & dpm_dec_reg_rdata_LED_0 & (dpm_dec_reg_rdata_LED_3 $ dpm_dec_reg_rdata_LED_1) # !dpm_dec_reg_rdata_LED_2 & !dpm_dec_reg_rdata_LED_3 & (dpm_dec_reg_rdata_LED_1 # dpm_dec_reg_rdata_LED_0);


--ix2046_lc is ix2046_lc
--operation mode is normal

ix2046_lc = dpm_dec_reg_rdata_LED_5 & !dpm_dec_reg_rdata_LED_7 & dpm_dec_reg_rdata_LED_4 # !dpm_dec_reg_rdata_LED_5 & (dpm_dec_reg_rdata_LED_6 & !dpm_dec_reg_rdata_LED_7 # !dpm_dec_reg_rdata_LED_6 & dpm_dec_reg_rdata_LED_4);


--ix2047_lc is ix2047_lc
--operation mode is normal

ix2047_lc = dpm_dec_reg_rdata_LED_1 & !dpm_dec_reg_rdata_LED_3 & dpm_dec_reg_rdata_LED_0 # !dpm_dec_reg_rdata_LED_1 & (dpm_dec_reg_rdata_LED_2 & !dpm_dec_reg_rdata_LED_3 # !dpm_dec_reg_rdata_LED_2 & dpm_dec_reg_rdata_LED_0);


--ix2044_lc is ix2044_lc
--operation mode is normal

ix2044_lc = dpm_dec_reg_rdata_LED_4 & (dpm_dec_reg_rdata_LED_6 $ !dpm_dec_reg_rdata_LED_5) # !dpm_dec_reg_rdata_LED_4 & (dpm_dec_reg_rdata_LED_7 & !dpm_dec_reg_rdata_LED_6 & dpm_dec_reg_rdata_LED_5 # !dpm_dec_reg_rdata_LED_7 & dpm_dec_reg_rdata_LED_6 & !dpm_dec_reg_rdata_LED_5);


--ix2045_lc is ix2045_lc
--operation mode is normal

ix2045_lc = dpm_dec_reg_rdata_LED_0 & (dpm_dec_reg_rdata_LED_2 $ !dpm_dec_reg_rdata_LED_1) # !dpm_dec_reg_rdata_LED_0 & (dpm_dec_reg_rdata_LED_3 & !dpm_dec_reg_rdata_LED_2 & dpm_dec_reg_rdata_LED_1 # !dpm_dec_reg_rdata_LED_3 & dpm_dec_reg_rdata_LED_2 & !dpm_dec_reg_rdata_LED_1);


--ix2042_lc is ix2042_lc
--operation mode is normal

ix2042_lc = dpm_dec_reg_rdata_LED_7 & dpm_dec_reg_rdata_LED_6 & (dpm_dec_reg_rdata_LED_5 # !dpm_dec_reg_rdata_LED_4) # !dpm_dec_reg_rdata_LED_7 & !dpm_dec_reg_rdata_LED_6 & dpm_dec_reg_rdata_LED_5 & !dpm_dec_reg_rdata_LED_4;


--ix2043_lc is ix2043_lc
--operation mode is normal

ix2043_lc = dpm_dec_reg_rdata_LED_3 & dpm_dec_reg_rdata_LED_2 & (dpm_dec_reg_rdata_LED_1 # !dpm_dec_reg_rdata_LED_0) # !dpm_dec_reg_rdata_LED_3 & !dpm_dec_reg_rdata_LED_2 & dpm_dec_reg_rdata_LED_1 & !dpm_dec_reg_rdata_LED_0;


--ix2040_lc is ix2040_lc
--operation mode is normal

ix2040_lc = dpm_dec_reg_rdata_LED_7 & (dpm_dec_reg_rdata_LED_4 & dpm_dec_reg_rdata_LED_5 # !dpm_dec_reg_rdata_LED_4 & dpm_dec_reg_rdata_LED_6) # !dpm_dec_reg_rdata_LED_7 & dpm_dec_reg_rdata_LED_6 & (dpm_dec_reg_rdata_LED_5 $ dpm_dec_reg_rdata_LED_4);


--ix2041_lc is ix2041_lc
--operation mode is normal

ix2041_lc = dpm_dec_reg_rdata_LED_3 & (dpm_dec_reg_rdata_LED_0 & dpm_dec_reg_rdata_LED_1 # !dpm_dec_reg_rdata_LED_0 & dpm_dec_reg_rdata_LED_2) # !dpm_dec_reg_rdata_LED_3 & dpm_dec_reg_rdata_LED_2 & (dpm_dec_reg_rdata_LED_1 $ dpm_dec_reg_rdata_LED_0);


--ix2038_lc is ix2038_lc
--operation mode is normal

ix2038_lc = dpm_dec_reg_rdata_LED_7 & dpm_dec_reg_rdata_LED_4 & (dpm_dec_reg_rdata_LED_6 $ dpm_dec_reg_rdata_LED_5) # !dpm_dec_reg_rdata_LED_7 & !dpm_dec_reg_rdata_LED_5 & (dpm_dec_reg_rdata_LED_6 $ dpm_dec_reg_rdata_LED_4);


--ix2039_lc is ix2039_lc
--operation mode is normal

ix2039_lc = dpm_dec_reg_rdata_LED_3 & dpm_dec_reg_rdata_LED_0 & (dpm_dec_reg_rdata_LED_2 $ dpm_dec_reg_rdata_LED_1) # !dpm_dec_reg_rdata_LED_3 & !dpm_dec_reg_rdata_LED_1 & (dpm_dec_reg_rdata_LED_2 $ dpm_dec_reg_rdata_LED_0);


--dpm_ni2f_reg_sm_4 is dpm_ni2f_reg_sm_4
--operation mode is normal

dpm_ni2f_reg_sm_4_lut_out = dpm_ni2f_reg_sm_3;
dpm_ni2f_reg_sm_4 = DFFEA(dpm_ni2f_reg_sm_4_lut_out, CLK50M, !ix2000_lc, , , , );


--U1_ad_ir_address[2] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|ad_ir_address[2]
--operation mode is normal

U1_ad_ir_address[2] = AMPP_FUNCTION(U1_ad_IR_ce_address, pci_ad_2, pci_rstn, GLOBAL(pci_clk));


--Z1_no_op_reg[1] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|no_op_reg[1]
--operation mode is normal

Z1_no_op_reg[1] = AMPP_FUNCTION(pci_rstn, GLOBAL(pci_clk));


--Z1L212 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_adr[2]~17
--operation mode is normal

Z1L212 = AMPP_FUNCTION(U1_ad_ir_address[2], Z1_no_op_reg[1]);


--U1_ad_ir_address[3] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|ad_ir_address[3]
--operation mode is normal

U1_ad_ir_address[3] = AMPP_FUNCTION(U1_ad_IR_ce_address, pci_ad_3, pci_rstn, GLOBAL(pci_clk));


--Z1L312 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_adr[3]~16
--operation mode is normal

Z1L312 = AMPP_FUNCTION(Z1_no_op_reg[1], U1_ad_ir_address[3]);


--U1_ad_ir_address[4] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|ad_ir_address[4]
--operation mode is normal

U1_ad_ir_address[4] = AMPP_FUNCTION(U1_ad_IR_ce_address, pci_ad_4, pci_rstn, GLOBAL(pci_clk));


--Z1L412 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_adr[4]~15
--operation mode is normal

Z1L412 = AMPP_FUNCTION(Z1_no_op_reg[1], U1_ad_ir_address[4]);


--U1_ad_ir_address[5] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|ad_ir_address[5]
--operation mode is normal

U1_ad_ir_address[5] = AMPP_FUNCTION(U1_ad_IR_ce_address, pci_ad_5, pci_rstn, GLOBAL(pci_clk));


--Z1L512 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_adr[5]~14
--operation mode is normal

Z1L512 = AMPP_FUNCTION(Z1_no_op_reg[1], U1_ad_ir_address[5]);


--U1_ad_ir_address[6] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|ad_ir_address[6]
--operation mode is normal

U1_ad_ir_address[6] = AMPP_FUNCTION(U1_ad_IR_ce_address, pci_ad_6, pci_rstn, GLOBAL(pci_clk));


--Z1L612 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_adr[6]~13
--operation mode is normal

Z1L612 = AMPP_FUNCTION(Z1_no_op_reg[1], U1_ad_ir_address[6]);


--U1_ad_ir_address[7] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|ad_ir_address[7]
--operation mode is normal

U1_ad_ir_address[7] = AMPP_FUNCTION(U1_ad_IR_ce_address, pci_ad_7, pci_rstn, GLOBAL(pci_clk));


--Z1L712 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_adr[7]~12
--operation mode is normal

Z1L712 = AMPP_FUNCTION(Z1_no_op_reg[1], U1_ad_ir_address[7]);


--U1_ad_ir_address[8] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|ad_ir_address[8]
--operation mode is normal

U1_ad_ir_address[8] = AMPP_FUNCTION(U1_ad_IR_ce_address, pci_ad_8, pci_rstn, GLOBAL(pci_clk));


--Z1L812 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_adr[8]~11
--operation mode is normal

Z1L812 = AMPP_FUNCTION(Z1_no_op_reg[1], U1_ad_ir_address[8]);


--U1_ad_ir_address[9] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|ad_ir_address[9]
--operation mode is normal

U1_ad_ir_address[9] = AMPP_FUNCTION(U1_ad_IR_ce_address, pci_ad_9, pci_rstn, GLOBAL(pci_clk));


--Z1L912 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_adr[9]~10
--operation mode is normal

Z1L912 = AMPP_FUNCTION(Z1_no_op_reg[1], U1_ad_ir_address[9]);


--U1_ad_ir_address[10] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|ad_ir_address[10]
--operation mode is normal

U1_ad_ir_address[10] = AMPP_FUNCTION(U1_ad_IR_ce_address, pci_ad_10, pci_rstn, GLOBAL(pci_clk));


--Z1L022 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_adr[10]~9
--operation mode is normal

Z1L022 = AMPP_FUNCTION(Z1_no_op_reg[1], U1_ad_ir_address[10]);


--U1_ad_ir_address[11] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|ad_ir_address[11]
--operation mode is normal

U1_ad_ir_address[11] = AMPP_FUNCTION(U1_ad_IR_ce_address, pci_ad_11, pci_rstn, GLOBAL(pci_clk));


--Z1L122 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_adr[11]~8
--operation mode is normal

Z1L122 = AMPP_FUNCTION(Z1_no_op_reg[1], U1_ad_ir_address[11]);


--U1_ad_ir_address[12] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|ad_ir_address[12]
--operation mode is normal

U1_ad_ir_address[12] = AMPP_FUNCTION(U1_ad_IR_ce_address, pci_ad_12, pci_rstn, GLOBAL(pci_clk));


--Z1L222 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_adr[12]~7
--operation mode is normal

Z1L222 = AMPP_FUNCTION(Z1_no_op_reg[1], U1_ad_ir_address[12]);


--U1_ad_ir_address[13] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|ad_ir_address[13]
--operation mode is normal

U1_ad_ir_address[13] = AMPP_FUNCTION(U1_ad_IR_ce_address, pci_ad_13, pci_rstn, GLOBAL(pci_clk));


--Z1L322 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_adr[13]~6
--operation mode is normal

Z1L322 = AMPP_FUNCTION(Z1_no_op_reg[1], U1_ad_ir_address[13]);


--U1_ad_ir_address[14] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|ad_ir_address[14]
--operation mode is normal

U1_ad_ir_address[14] = AMPP_FUNCTION(U1_ad_IR_ce_address, pci_ad_14, pci_rstn, GLOBAL(pci_clk));


--Z1L422 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_adr[14]~5
--operation mode is normal

Z1L422 = AMPP_FUNCTION(Z1_no_op_reg[1], U1_ad_ir_address[14]);


--U1_ad_ir_address[15] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|ad_ir_address[15]
--operation mode is normal

U1_ad_ir_address[15] = AMPP_FUNCTION(U1_ad_IR_ce_address, pci_ad_15, pci_rstn, GLOBAL(pci_clk));


--Z1L522 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_adr[15]~4
--operation mode is normal

Z1L522 = AMPP_FUNCTION(Z1_no_op_reg[1], U1_ad_ir_address[15]);


--U1_ad_ir_address[16] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|ad_ir_address[16]
--operation mode is normal

U1_ad_ir_address[16] = AMPP_FUNCTION(U1_ad_IR_ce_address, pci_ad_16, pci_rstn, GLOBAL(pci_clk));


--Z1L622 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_adr[16]~3
--operation mode is normal

Z1L622 = AMPP_FUNCTION(Z1_no_op_reg[1], U1_ad_ir_address[16]);


--U1_ad_ir_address[17] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|ad_ir_address[17]
--operation mode is normal

U1_ad_ir_address[17] = AMPP_FUNCTION(U1_ad_IR_ce_address, pci_ad_17, pci_rstn, GLOBAL(pci_clk));


--Z1L722 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_adr[17]~2
--operation mode is normal

Z1L722 = AMPP_FUNCTION(Z1_no_op_reg[1], U1_ad_ir_address[17]);


--U1_ad_ir_address[18] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|ad_ir_address[18]
--operation mode is normal

U1_ad_ir_address[18] = AMPP_FUNCTION(U1_ad_IR_ce_address, pci_ad_18, pci_rstn, GLOBAL(pci_clk));


--Z1L822 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_adr[18]~1
--operation mode is normal

Z1L822 = AMPP_FUNCTION(Z1_no_op_reg[1], U1_ad_ir_address[18]);


--H2_b_non_empty is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_fefifo_v1d:a_fefifo5|b_non_empty
--operation mode is normal

H2_b_non_empty_lut_out = H2L9 # Q11_dffe51a[0] & !H2_b_non_empty & !H2_b_one;
H2_b_non_empty = DFFEA(H2_b_non_empty_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );


--dpm_ni2f_reg_sm_10 is dpm_ni2f_reg_sm_10
--operation mode is normal

dpm_ni2f_reg_sm_10_lut_out = dpm_ni2f_reg_sm_9;
dpm_ni2f_reg_sm_10 = DFFEA(dpm_ni2f_reg_sm_10_lut_out, CLK50M, !ix2000_lc, , , , );


--dpm_ni2f_reg_pci_rd_req_s is dpm_ni2f_reg_pci_rd_req_s
--operation mode is normal

dpm_ni2f_reg_pci_rd_req_s_lut_out = (Z1L922 & !U1_cben_ir_address[0] & Z1L012 & Z1L572) & CASCADE(ix2064);
dpm_ni2f_reg_pci_rd_req_s = DFFEA(dpm_ni2f_reg_pci_rd_req_s_lut_out, CLK50M, , , , , );


--dpm_ni2f_reg_cdata_2 is dpm_ni2f_reg_cdata_2
--operation mode is normal

dpm_ni2f_reg_cdata_2_lut_out = R1_q[2] # !dpm_ni2f_reg_sm_2;
dpm_ni2f_reg_cdata_2 = DFFEA(dpm_ni2f_reg_cdata_2_lut_out, CLK50M, , , ix2008_lc, , );


--dpm_ni2f_reg_cdata_3 is dpm_ni2f_reg_cdata_3
--operation mode is normal

dpm_ni2f_reg_cdata_3_lut_out = !dpm_ni2f_reg_sm_2 # !R1_q[3];
dpm_ni2f_reg_cdata_3 = DFFEA(dpm_ni2f_reg_cdata_3_lut_out, CLK50M, , , ix2008_lc, , );


--dpm_ni2f_reg_cdata_4 is dpm_ni2f_reg_cdata_4
--operation mode is normal

dpm_ni2f_reg_cdata_4_lut_out = R1_q[4] # !dpm_ni2f_reg_sm_2;
dpm_ni2f_reg_cdata_4 = DFFEA(dpm_ni2f_reg_cdata_4_lut_out, CLK50M, , , ix2008_lc, , );


--dpm_ni2f_reg_cdata_5 is dpm_ni2f_reg_cdata_5
--operation mode is normal

dpm_ni2f_reg_cdata_5_lut_out = !dpm_ni2f_reg_sm_2 # !R1_q[5];
dpm_ni2f_reg_cdata_5 = DFFEA(dpm_ni2f_reg_cdata_5_lut_out, CLK50M, , , ix2008_lc, , );


--dpm_ni2f_reg_cdata_6 is dpm_ni2f_reg_cdata_6
--operation mode is normal

dpm_ni2f_reg_cdata_6_lut_out = R1_q[6] # !dpm_ni2f_reg_sm_2;
dpm_ni2f_reg_cdata_6 = DFFEA(dpm_ni2f_reg_cdata_6_lut_out, CLK50M, , , ix2008_lc, , );


--dpm_ni2f_reg_cdata_7 is dpm_ni2f_reg_cdata_7
--operation mode is normal

dpm_ni2f_reg_cdata_7_lut_out = R1_q[7] # !dpm_ni2f_reg_sm_2;
dpm_ni2f_reg_cdata_7 = DFFEA(dpm_ni2f_reg_cdata_7_lut_out, CLK50M, , , ix2008_lc, , );


--dpm_ni2f_reg_cdata_8 is dpm_ni2f_reg_cdata_8
--operation mode is normal

dpm_ni2f_reg_cdata_8_lut_out = R2_q[0] # !dpm_ni2f_reg_sm_2;
dpm_ni2f_reg_cdata_8 = DFFEA(dpm_ni2f_reg_cdata_8_lut_out, CLK50M, , , ix2008_lc, , );


--dpm_ni2f_reg_cdata_9 is dpm_ni2f_reg_cdata_9
--operation mode is normal

dpm_ni2f_reg_cdata_9_lut_out = !dpm_ni2f_reg_sm_2 # !R2_q[1];
dpm_ni2f_reg_cdata_9 = DFFEA(dpm_ni2f_reg_cdata_9_lut_out, CLK50M, , , ix2008_lc, , );


--dpm_ni2f_reg_cdata_10 is dpm_ni2f_reg_cdata_10
--operation mode is normal

dpm_ni2f_reg_cdata_10_lut_out = R2_q[2] # !dpm_ni2f_reg_sm_2;
dpm_ni2f_reg_cdata_10 = DFFEA(dpm_ni2f_reg_cdata_10_lut_out, CLK50M, , , ix2008_lc, , );


--dpm_ni2f_reg_cdata_11 is dpm_ni2f_reg_cdata_11
--operation mode is normal

dpm_ni2f_reg_cdata_11_lut_out = !dpm_ni2f_reg_sm_2 # !R2_q[3];
dpm_ni2f_reg_cdata_11 = DFFEA(dpm_ni2f_reg_cdata_11_lut_out, CLK50M, , , ix2008_lc, , );


--dpm_ni2f_reg_cdata_12 is dpm_ni2f_reg_cdata_12
--operation mode is normal

dpm_ni2f_reg_cdata_12_lut_out = R2_q[4] # !dpm_ni2f_reg_sm_2;
dpm_ni2f_reg_cdata_12 = DFFEA(dpm_ni2f_reg_cdata_12_lut_out, CLK50M, , , ix2008_lc, , );


--dpm_ni2f_reg_cdata_13 is dpm_ni2f_reg_cdata_13
--operation mode is normal

dpm_ni2f_reg_cdata_13_lut_out = !dpm_ni2f_reg_sm_2 # !R2_q[5];
dpm_ni2f_reg_cdata_13 = DFFEA(dpm_ni2f_reg_cdata_13_lut_out, CLK50M, , , ix2008_lc, , );


--dpm_ni2f_reg_cdata_14 is dpm_ni2f_reg_cdata_14
--operation mode is normal

dpm_ni2f_reg_cdata_14_lut_out = R2_q[6] # !dpm_ni2f_reg_sm_2;
dpm_ni2f_reg_cdata_14 = DFFEA(dpm_ni2f_reg_cdata_14_lut_out, CLK50M, , , ix2008_lc, , );


--dpm_ni2f_reg_cdata_15 is dpm_ni2f_reg_cdata_15
--operation mode is normal

dpm_ni2f_reg_cdata_15_lut_out = R2_q[7] # !dpm_ni2f_reg_sm_2;
dpm_ni2f_reg_cdata_15 = DFFEA(dpm_ni2f_reg_cdata_15_lut_out, CLK50M, , , ix2008_lc, , );


--dpm_ni2f_reg_sm_3 is dpm_ni2f_reg_sm_3
--operation mode is normal

dpm_ni2f_reg_sm_3_lut_out = dpm_ni2f_reg_pci_rd_req_s & !dpm_ni2f_reg_rdempty_s & !dpm_ni2f_reg_sm_0;
dpm_ni2f_reg_sm_3 = DFFEA(dpm_ni2f_reg_sm_3_lut_out, CLK50M, !ix2000_lc, , , , );


--ix2055 is ix2055
--operation mode is normal

ix2055 = !dpm_ni2f_reg_sm_11 & !dpm_ni2f_reg_sm_4 & !dpm_ni2f_reg_sm_3 & !dpm_ni2f_reg_sm_2;


--U1_high_ad_or[40] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_or[40]
--operation mode is normal

U1_high_ad_or[40] = AMPP_FUNCTION(V1_ad_ce[40], A1L361, U1_mstr_trg_hi_ad, U1_high_ad_out_lc[8], pci_rstn, GLOBAL(pci_clk));


--W1_tgt_64_response_reg is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|tgt_64_response_reg
--operation mode is normal

W1_tgt_64_response_reg = AMPP_FUNCTION(W1_tgt_64_response_reg, Z1_targ_oeR_reg, W1L664, W1_tgt_64_response_reset, pci_rstn, GLOBAL(pci_clk));


--W1_lm_hdata_ack is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|lm_hdata_ack
--operation mode is normal

W1_lm_hdata_ack = AMPP_FUNCTION(W1_lm_hdata_ack_ena2, W1L652, pci_rstn, GLOBAL(pci_clk));


--U1L1 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|_~1196
--operation mode is normal

U1L1 = AMPP_FUNCTION(W1_lm_ldata_ack, W1_tgt_64_response_reg, W1_lm_hdata_ack, Z1_$00109);


--Z1_lt_hdata_ack_r is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_hdata_ack_r
--operation mode is normal

Z1_lt_hdata_ack_r = AMPP_FUNCTION(Z1_lt_hdata_ack_r_ena, Z1_lt_hdata_ack_r_d[1], Z1_lt_hdata_ack_r_d[4], Z1_lt_hdata_ack_r, pci_rstn, GLOBAL(pci_clk));


--U1_local_dat_sel is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|local_dat_sel
--operation mode is normal

U1_local_dat_sel = AMPP_FUNCTION(U1L1, Z1_lt_ldata_ack_r, Z1_$00109, Z1_lt_hdata_ack_r);


--W1_MS_ENA is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MS_ENA
--operation mode is normal

W1_MS_ENA = AMPP_FUNCTION(W1_MS_ENA_d_lc, W1_l_req_vld, W1_MS_PARK, pci_gntn, pci_rstn, GLOBAL(pci_clk));


--Z1_LR_IDLE_NOT is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|LR_IDLE_NOT
--operation mode is normal

Z1_LR_IDLE_NOT = AMPP_FUNCTION(Z1_LR_DONE, Z1_LR_IDLE_NOT, Z1_LR_IDLE_lc1, pci_rstn, GLOBAL(pci_clk));


--Z1_LW_IDLE_NOT is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|LW_IDLE_NOT
--operation mode is normal

Z1_LW_IDLE_NOT = AMPP_FUNCTION(Z1_LW_DONE, Z1_LW_IDLE_NOT, Z1_LW_IDLE_lc1, pci_rstn, GLOBAL(pci_clk));


--Z1_$00109 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|$00109
--operation mode is normal

Z1_$00109 = AMPP_FUNCTION(Z1_LR_IDLE_NOT, Z1_LW_IDLE_NOT, W1_mstr_actv_lc);


--U1_cben_ir_address[3] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|cben_ir_address[3]
--operation mode is normal

U1_cben_ir_address[3] = AMPP_FUNCTION(U1_cben_IR_ce_address, pci_cben_3, pci_rstn, GLOBAL(pci_clk));


--U1_cben_ir_address[2] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|cben_ir_address[2]
--operation mode is normal

U1_cben_ir_address[2] = AMPP_FUNCTION(U1_cben_IR_ce_address, pci_cben_2, pci_rstn, GLOBAL(pci_clk));


--ix2069_lc is ix2069_lc
--operation mode is normal

ix2069_lc = U1_cben_ir_address[2] # !U1_cben_ir_address[3];

--A1L182 is ix2069_lc~0
--operation mode is normal

A1L182 = U1_cben_ir_address[2] # !U1_cben_ir_address[3];


--U1_cben_ir_address[0] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|cben_ir_address[0]
--operation mode is normal

U1_cben_ir_address[0] = AMPP_FUNCTION(U1_cben_IR_ce_address, pci_cben_0, pci_rstn, GLOBAL(pci_clk));


--Z1_lt_ack_R_r4 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_ack_R_r4
--operation mode is normal

Z1_lt_ack_R_r4 = AMPP_FUNCTION(Z1_LR_PXFR, A1L234, Z1_rd_backoff, pci_rstn, GLOBAL(pci_clk), Z1L41);


--Z1_lt_ack_R_r3 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_ack_R_r3
--operation mode is normal

Z1_lt_ack_R_r3 = AMPP_FUNCTION(Z1_lt_ack_R_r3_lc3, A1L234, Z1_rd_backoff, pci_rstn, GLOBAL(pci_clk), Z1L31);


--Z1_lt_ack_R_r1 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_ack_R_r1
--operation mode is normal

Z1_lt_ack_R_r1 = AMPP_FUNCTION(Z1_lt_ack_R_r1_lc[7], Z1_lt_ack_R_r1_lc[8], Z1_lt_ack_R_r1_lc[9], A1L234, pci_rstn, GLOBAL(pci_clk));


--Z1_lt_ack_R_r2 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_ack_R_r2
--operation mode is normal

Z1_lt_ack_R_r2 = AMPP_FUNCTION(Z1L35, A1L734, pci_rstn, GLOBAL(pci_clk));


--Z1L012 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_ack_R~18
--operation mode is normal

Z1L012 = AMPP_FUNCTION(Z1_lt_ack_R_r4, Z1_lt_ack_R_r3, Z1_lt_ack_R_r1, Z1_lt_ack_R_r2);


--Z1_TS_IDLE_NOT is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|TS_IDLE_NOT
--operation mode is normal

Z1_TS_IDLE_NOT = AMPP_FUNCTION(Z1_TS_IDLE_d_lc, Z1_TS_IDLE_d_lc1, BB1_mbar_hit, pci_rstn, GLOBAL(pci_clk));


--BB1_bar_hitR[0] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|bar_hitR[0]
--operation mode is normal

BB1_bar_hitR[0] = AMPP_FUNCTION(BB1_bar_hit[0], BB1_bar_hitR[0], Z1_bar_hit_rst, pci_rstn, GLOBAL(pci_clk));


--Z1L572 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_tsr[0]~0
--operation mode is normal

Z1L572 = AMPP_FUNCTION(Z1_TS_IDLE_NOT, BB1_bar_hitR[0]);


--A1L271 is ix1997_lc~0
--operation mode is normal

A1L271 = (U1_cben_ir_address[0] & Z1L012 & Z1L572 & ix2053_lc) & CASCADE(A1L182);


--dpm_ni2f_reg_end_marker32 is dpm_ni2f_reg_end_marker32
--operation mode is normal

dpm_ni2f_reg_end_marker32_lut_out = dpm_ni2f_reg_clk_sram_i & (ix2065_lc # dpm_ni2f_reg_end_marker32);
dpm_ni2f_reg_end_marker32 = DFFEA(dpm_ni2f_reg_end_marker32_lut_out, CLK50M, , , ix2009_lc, , );


--dpm_ni2f_reg_timeout is dpm_ni2f_reg_timeout
--operation mode is normal

dpm_ni2f_reg_timeout_lut_out = !dpm_ni2f_reg_sm_2;
dpm_ni2f_reg_timeout = DFFEA(dpm_ni2f_reg_timeout_lut_out, CLK50M, , , ix2006_lc, , );


--ix2057 is ix2057
--operation mode is normal

ix2057 = dpm_ni2f_reg_rdreq_fifo # !dpm_ni2f_reg_end_marker32 & !dpm_ni2f_reg_timeout # !dpm_ni2f_reg_sm_1;


--dpm_ni2f_reg_rdempty_s is dpm_ni2f_reg_rdempty_s
--operation mode is normal

dpm_ni2f_reg_rdempty_s_lut_out = H2_b_non_empty;
dpm_ni2f_reg_rdempty_s = DFFEA(dpm_ni2f_reg_rdempty_s_lut_out, CLK50M, !ix2000_lc, , , , );


--W1_perr_oer is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|perr_oer
--operation mode is normal

W1_perr_oer = AMPP_FUNCTION(W1_MS_DXFR, W1_MS_TAR, W1_wr_rdn, pci_rstn, GLOBAL(pci_clk));


--AB5_REG is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_sr:wr_rdn_FF|REG
--operation mode is normal

AB5_REG = AMPP_FUNCTION(Z1L57, AB5_REG, Z1_LW_IDLE_NOT, Z1_TS_IDLE_NOT, pci_rstn, GLOBAL(pci_clk));


--Z1_TURN_AR_R is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|TURN_AR_R
--operation mode is normal

Z1_TURN_AR_R = AMPP_FUNCTION(Z1_TS_TURN_AR, pci_rstn, GLOBAL(pci_clk));


--W1_MS_REQ is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MS_REQ
--operation mode is normal

W1_MS_REQ = AMPP_FUNCTION(W1_MS_REQ_d_lc[1], pci_gntn, W1_MS_REQ_d_lc[2], pci_rstn, GLOBAL(pci_clk));


--W1_MS_IDLE_not is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MS_IDLE_not
--operation mode is normal

W1_MS_IDLE_not = AMPP_FUNCTION(W1_MS_TAR, pci_gntn, W1_MS_IDLE_lc1, W1_l_req_vld, pci_rstn, GLOBAL(pci_clk));


--W1_req_or_lc[1] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|req_or_lc[1]
--operation mode is normal

W1_req_or_lc[1] = AMPP_FUNCTION(W1_MS_REQ, W1_l_req_vld, W1_MS_IDLE_not);


--W1_MS_PARK is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MS_PARK
--operation mode is normal

W1_MS_PARK = AMPP_FUNCTION(W1_MS_IDLE_lc1, pci_gntn, W1_l_req_vld, pci_rstn, GLOBAL(pci_clk));


--W1_req_or_lc[2] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|req_or_lc[2]
--operation mode is normal

W1_req_or_lc[2] = AMPP_FUNCTION(W1_MS_ENA, W1_l_req_vld, W1_MS_PARK);


--BB1_cmd_reg[6] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|cmd_reg[6]
--operation mode is normal

BB1_cmd_reg[6] = AMPP_FUNCTION(BB1L59, U1_low_ad_IR_data[6], pci_rstn, GLOBAL(pci_clk));


--BB1_cmd_reg[8] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|cmd_reg[8]
--operation mode is normal

BB1_cmd_reg[8] = AMPP_FUNCTION(BB1L69, U1_low_ad_IR_data[8], pci_rstn, GLOBAL(pci_clk));


--X1_serr_or_lc is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pk:parity_Chk|serr_or_lc
--operation mode is normal

X1_serr_or_lc = AMPP_FUNCTION(BB1_cmd_reg[6], U1_trg_serr_vld, BB1_cmd_reg[8]);


--X1_xxlad[11] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pk:parity_Chk|xxlad[11]
--operation mode is normal

X1_xxlad[11] = AMPP_FUNCTION(X1_xxlad[10], X1_xxlad[9], X1_xxlad[8]);


--U1_low_ad_IR_data[7] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_IR_data[7]
--operation mode is normal

U1_low_ad_IR_data[7] = AMPP_FUNCTION(U1_ad_IR_ce_data, pci_ad_7, pci_rstn, GLOBAL(pci_clk));


--U1_low_ad_IR_data[6] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_IR_data[6]
--operation mode is normal

U1_low_ad_IR_data[6] = AMPP_FUNCTION(U1_ad_IR_ce_data, pci_ad_6, pci_rstn, GLOBAL(pci_clk));


--U1_low_ad_IR_data[5] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_IR_data[5]
--operation mode is normal

U1_low_ad_IR_data[5] = AMPP_FUNCTION(U1_ad_IR_ce_data, pci_ad_5, pci_rstn, GLOBAL(pci_clk));


--U1_low_ad_IR_data[4] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_IR_data[4]
--operation mode is normal

U1_low_ad_IR_data[4] = AMPP_FUNCTION(U1_ad_IR_ce_data, pci_ad_4, pci_rstn, GLOBAL(pci_clk));


--U1_low_ad_IR_data[3] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_IR_data[3]
--operation mode is normal

U1_low_ad_IR_data[3] = AMPP_FUNCTION(U1_ad_IR_ce_data, pci_ad_3, pci_rstn, GLOBAL(pci_clk));


--U1_low_ad_IR_data[2] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_IR_data[2]
--operation mode is normal

U1_low_ad_IR_data[2] = AMPP_FUNCTION(U1_ad_IR_ce_data, pci_ad_2, pci_rstn, GLOBAL(pci_clk));


--U1_low_ad_IR_data[1] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_IR_data[1]
--operation mode is normal

U1_low_ad_IR_data[1] = AMPP_FUNCTION(U1_ad_IR_ce_data, pci_ad_1, pci_rstn, GLOBAL(pci_clk));


--U1_low_ad_IR_data[0] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_IR_data[0]
--operation mode is normal

U1_low_ad_IR_data[0] = AMPP_FUNCTION(U1_ad_IR_ce_data, pci_ad_0, pci_rstn, GLOBAL(pci_clk));


--A1L381 is ix2004_lc~0
--operation mode is normal

A1L381 = (ix2066_lc # dpm_ni2f_reg_pci_rd_req_s & !dpm_ni2f_reg_rdempty_s & !dpm_ni2f_reg_sm_0) & CASCADE(A1L671);


--Q11_dffe51a[10] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|dffpipe_ab3:dffpipe20|dffe51a[10]
--operation mode is normal

Q11_dffe51a[10]_lut_out = !N3L1;
Q11_dffe51a[10] = DFFEA(Q11_dffe51a[10]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );


--Q11_dffe51a[9] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|dffpipe_ab3:dffpipe20|dffe51a[9]
--operation mode is normal

Q11_dffe51a[9]_lut_out = !N3_add_sub_cella[9];
Q11_dffe51a[9] = DFFEA(Q11_dffe51a[9]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );


--Q11_dffe51a[8] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|dffpipe_ab3:dffpipe20|dffe51a[8]
--operation mode is normal

Q11_dffe51a[8]_lut_out = !N3_add_sub_cella[8];
Q11_dffe51a[8] = DFFEA(Q11_dffe51a[8]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );


--Q11_dffe51a[7] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|dffpipe_ab3:dffpipe20|dffe51a[7]
--operation mode is normal

Q11_dffe51a[7]_lut_out = !N3_add_sub_cella[7];
Q11_dffe51a[7] = DFFEA(Q11_dffe51a[7]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );


--H2L6 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_fefifo_v1d:a_fefifo5|b_non_empty~314
--operation mode is normal

H2L6 = Q11_dffe51a[10] # Q11_dffe51a[9] # Q11_dffe51a[8] # Q11_dffe51a[7];


--Q11_dffe51a[6] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|dffpipe_ab3:dffpipe20|dffe51a[6]
--operation mode is normal

Q11_dffe51a[6]_lut_out = !N3_add_sub_cella[6];
Q11_dffe51a[6] = DFFEA(Q11_dffe51a[6]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );


--Q11_dffe51a[5] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|dffpipe_ab3:dffpipe20|dffe51a[5]
--operation mode is normal

Q11_dffe51a[5]_lut_out = !N3_add_sub_cella[5];
Q11_dffe51a[5] = DFFEA(Q11_dffe51a[5]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );


--Q11_dffe51a[4] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|dffpipe_ab3:dffpipe20|dffe51a[4]
--operation mode is normal

Q11_dffe51a[4]_lut_out = !N3_add_sub_cella[4];
Q11_dffe51a[4] = DFFEA(Q11_dffe51a[4]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );


--Q11_dffe51a[3] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|dffpipe_ab3:dffpipe20|dffe51a[3]
--operation mode is normal

Q11_dffe51a[3]_lut_out = !N3_add_sub_cella[3];
Q11_dffe51a[3] = DFFEA(Q11_dffe51a[3]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );


--H2L7 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_fefifo_v1d:a_fefifo5|b_non_empty~315
--operation mode is normal

H2L7 = Q11_dffe51a[6] # Q11_dffe51a[5] # Q11_dffe51a[4] # Q11_dffe51a[3];


--Q11_dffe51a[1] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|dffpipe_ab3:dffpipe20|dffe51a[1]
--operation mode is normal

Q11_dffe51a[1]_lut_out = !N3_add_sub_cella[1];
Q11_dffe51a[1] = DFFEA(Q11_dffe51a[1]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );


--Q11_dffe51a[2] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|dffpipe_ab3:dffpipe20|dffe51a[2]
--operation mode is normal

Q11_dffe51a[2]_lut_out = !N3_add_sub_cella[2];
Q11_dffe51a[2] = DFFEA(Q11_dffe51a[2]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );


--H2L8 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_fefifo_v1d:a_fefifo5|b_non_empty~316
--operation mode is normal

H2L8 = H2L6 # H2L7 # Q11_dffe51a[1] # Q11_dffe51a[2];


--H2_b_one is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_fefifo_v1d:a_fefifo5|b_one
--operation mode is normal

H2_b_one_lut_out = H2L1 & H2_b_non_empty & !H2_b_one;
H2_b_one = DFFEA(H2_b_one_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );


--H2_llreq is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_fefifo_v1d:a_fefifo5|llreq
--operation mode is normal

H2_llreq_lut_out = dpm_ni2f_reg_rdreq_fifo;
H2_llreq = DFFEA(H2_llreq_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );


--Q11_dffe51a[0] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|dffpipe_ab3:dffpipe20|dffe51a[0]
--operation mode is normal

Q11_dffe51a[0]_lut_out = N3_add_sub_cella[0];
Q11_dffe51a[0] = DFFEA(Q11_dffe51a[0]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );


--H2L2 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_fefifo_v1d:a_fefifo5|_~172
--operation mode is normal

H2L2 = H2L4 & (Q11_dffe51a[1] & H2_llreq & !Q11_dffe51a[0] # !Q11_dffe51a[1] & !H2_llreq & Q11_dffe51a[0]);


--H2L1 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_fefifo_v1d:a_fefifo5|_~3
--operation mode is normal

H2L1 = H2L2 & !Q11_dffe51a[3] & !Q11_dffe51a[2];


--H2L9 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_fefifo_v1d:a_fefifo5|b_non_empty~317
--operation mode is normal

H2L9 = H2L8 & (H2_b_one # !H2L1 # !H2_b_non_empty) # !H2L8 & H2_b_non_empty & !H2L1;


--ix2067_lc is ix2067_lc
--operation mode is normal

ix2067_lc = dpm_ni2f_reg_sm_1 & !dpm_ni2f_reg_rdreq_fifo;


--ix2003_lc is ix2003_lc
--operation mode is normal

ix2003_lc = pci_rstn & dpm_dec_reg_soft_rst_n & (dpm_ni2f_reg_sm_2 # dpm_ni2f_reg_sm_1);


--dpm_ni2f_reg_sm_9 is dpm_ni2f_reg_sm_9
--operation mode is normal

dpm_ni2f_reg_sm_9_lut_out = dpm_ni2f_reg_sm_8;
dpm_ni2f_reg_sm_9 = DFFEA(dpm_ni2f_reg_sm_9_lut_out, CLK50M, !ix2000_lc, , , , );


--dpm_ni2f_reg_sm_7 is dpm_ni2f_reg_sm_7
--operation mode is normal

dpm_ni2f_reg_sm_7_lut_out = dpm_ni2f_reg_sm_6;
dpm_ni2f_reg_sm_7 = DFFEA(dpm_ni2f_reg_sm_7_lut_out, CLK50M, !ix2000_lc, , , , );


--ix2068 is ix2068
--operation mode is normal

ix2068 = !dpm_ni2f_reg_sm_7 & !dpm_ni2f_reg_sm_5;


--A1L891 is ix2012_lc~0
--operation mode is normal

A1L891 = (!dpm_ni2f_reg_sm_9 & !dpm_ni2f_reg_sm_3 & !dpm_ni2f_reg_sm_2) & CASCADE(ix2068);


--R1_q[2] is nififo:dpm_ni2f_fifo_n|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|altdpram:dpram4|q[2]
R1_q[2]_data_in = ADC1_D[2];
R1_q[2]_clock_0 = !ADC2_D[2];
R1_q[2]_clock_1 = CLK50M;
R1_q[2]_clear_0 = dpm_ni2f_reg_sreset120;
R1_q[2]_clock_enable_1 = dpm_ni2f_reg_rdreq_fifo;
R1_q[2]_write_address = WR_ADDR(L1_power_modified_counter_values[0], L1_power_modified_counter_values[1], L1_power_modified_counter_values[2], L1_power_modified_counter_values[3], L1_power_modified_counter_values[4], L1_power_modified_counter_values[5], L1_power_modified_counter_values[6], L1_power_modified_counter_values[7], L1_power_modified_counter_values[8], L1_power_modified_counter_values[9], L1_power_modified_counter_values[10]);
R1_q[2]_read_address = RD_ADDR(R1L4, M1_power_modified_counter_values[1], M1_power_modified_counter_values[2], M1_power_modified_counter_values[3], M1_power_modified_counter_values[4], M1_power_modified_counter_values[5], M1_power_modified_counter_values[6], M1_power_modified_counter_values[7], M1_power_modified_counter_values[8], M1_power_modified_counter_values[9], M1_power_modified_counter_values[10]);
R1_q[2] = MEMORY_SEGMENT(R1_q[2]_data_in, VCC, R1_q[2]_clock_0, R1_q[2]_clock_1, R1_q[2]_clear_0, , R1_q[2]_clock_enable_1, VCC, R1_q[2]_write_address, R1_q[2]_read_address);


--R1_q[3] is nififo:dpm_ni2f_fifo_n|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|altdpram:dpram4|q[3]
R1_q[3]_data_in = ADC1_D[3];
R1_q[3]_clock_0 = !ADC2_D[2];
R1_q[3]_clock_1 = CLK50M;
R1_q[3]_clear_0 = dpm_ni2f_reg_sreset120;
R1_q[3]_clock_enable_1 = dpm_ni2f_reg_rdreq_fifo;
R1_q[3]_write_address = WR_ADDR(L1_power_modified_counter_values[0], L1_power_modified_counter_values[1], L1_power_modified_counter_values[2], L1_power_modified_counter_values[3], L1_power_modified_counter_values[4], L1_power_modified_counter_values[5], L1_power_modified_counter_values[6], L1_power_modified_counter_values[7], L1_power_modified_counter_values[8], L1_power_modified_counter_values[9], L1_power_modified_counter_values[10]);
R1_q[3]_read_address = RD_ADDR(R1L4, M1_power_modified_counter_values[1], M1_power_modified_counter_values[2], M1_power_modified_counter_values[3], M1_power_modified_counter_values[4], M1_power_modified_counter_values[5], M1_power_modified_counter_values[6], M1_power_modified_counter_values[7], M1_power_modified_counter_values[8], M1_power_modified_counter_values[9], M1_power_modified_counter_values[10]);
R1_q[3] = MEMORY_SEGMENT(R1_q[3]_data_in, VCC, R1_q[3]_clock_0, R1_q[3]_clock_1, R1_q[3]_clear_0, , R1_q[3]_clock_enable_1, VCC, R1_q[3]_write_address, R1_q[3]_read_address);


--R1_q[4] is nififo:dpm_ni2f_fifo_n|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|altdpram:dpram4|q[4]
R1_q[4]_data_in = ADC1_D[4];
R1_q[4]_clock_0 = !ADC2_D[2];
R1_q[4]_clock_1 = CLK50M;
R1_q[4]_clear_0 = dpm_ni2f_reg_sreset120;
R1_q[4]_clock_enable_1 = dpm_ni2f_reg_rdreq_fifo;
R1_q[4]_write_address = WR_ADDR(L1_power_modified_counter_values[0], L1_power_modified_counter_values[1], L1_power_modified_counter_values[2], L1_power_modified_counter_values[3], L1_power_modified_counter_values[4], L1_power_modified_counter_values[5], L1_power_modified_counter_values[6], L1_power_modified_counter_values[7], L1_power_modified_counter_values[8], L1_power_modified_counter_values[9], L1_power_modified_counter_values[10]);
R1_q[4]_read_address = RD_ADDR(R1L4, M1_power_modified_counter_values[1], M1_power_modified_counter_values[2], M1_power_modified_counter_values[3], M1_power_modified_counter_values[4], M1_power_modified_counter_values[5], M1_power_modified_counter_values[6], M1_power_modified_counter_values[7], M1_power_modified_counter_values[8], M1_power_modified_counter_values[9], M1_power_modified_counter_values[10]);
R1_q[4] = MEMORY_SEGMENT(R1_q[4]_data_in, VCC, R1_q[4]_clock_0, R1_q[4]_clock_1, R1_q[4]_clear_0, , R1_q[4]_clock_enable_1, VCC, R1_q[4]_write_address, R1_q[4]_read_address);


--R1_q[5] is nififo:dpm_ni2f_fifo_n|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|altdpram:dpram4|q[5]
R1_q[5]_data_in = ADC1_D[5];
R1_q[5]_clock_0 = !ADC2_D[2];
R1_q[5]_clock_1 = CLK50M;
R1_q[5]_clear_0 = dpm_ni2f_reg_sreset120;
R1_q[5]_clock_enable_1 = dpm_ni2f_reg_rdreq_fifo;
R1_q[5]_write_address = WR_ADDR(L1_power_modified_counter_values[0], L1_power_modified_counter_values[1], L1_power_modified_counter_values[2], L1_power_modified_counter_values[3], L1_power_modified_counter_values[4], L1_power_modified_counter_values[5], L1_power_modified_counter_values[6], L1_power_modified_counter_values[7], L1_power_modified_counter_values[8], L1_power_modified_counter_values[9], L1_power_modified_counter_values[10]);
R1_q[5]_read_address = RD_ADDR(R1L4, M1_power_modified_counter_values[1], M1_power_modified_counter_values[2], M1_power_modified_counter_values[3], M1_power_modified_counter_values[4], M1_power_modified_counter_values[5], M1_power_modified_counter_values[6], M1_power_modified_counter_values[7], M1_power_modified_counter_values[8], M1_power_modified_counter_values[9], M1_power_modified_counter_values[10]);
R1_q[5] = MEMORY_SEGMENT(R1_q[5]_data_in, VCC, R1_q[5]_clock_0, R1_q[5]_clock_1, R1_q[5]_clear_0, , R1_q[5]_clock_enable_1, VCC, R1_q[5]_write_address, R1_q[5]_read_address);


--R1_q[6] is nififo:dpm_ni2f_fifo_n|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|altdpram:dpram4|q[6]
R1_q[6]_data_in = ADC1_D[6];
R1_q[6]_clock_0 = !ADC2_D[2];
R1_q[6]_clock_1 = CLK50M;
R1_q[6]_clear_0 = dpm_ni2f_reg_sreset120;
R1_q[6]_clock_enable_1 = dpm_ni2f_reg_rdreq_fifo;
R1_q[6]_write_address = WR_ADDR(L1_power_modified_counter_values[0], L1_power_modified_counter_values[1], L1_power_modified_counter_values[2], L1_power_modified_counter_values[3], L1_power_modified_counter_values[4], L1_power_modified_counter_values[5], L1_power_modified_counter_values[6], L1_power_modified_counter_values[7], L1_power_modified_counter_values[8], L1_power_modified_counter_values[9], L1_power_modified_counter_values[10]);
R1_q[6]_read_address = RD_ADDR(R1L4, M1_power_modified_counter_values[1], M1_power_modified_counter_values[2], M1_power_modified_counter_values[3], M1_power_modified_counter_values[4], M1_power_modified_counter_values[5], M1_power_modified_counter_values[6], M1_power_modified_counter_values[7], M1_power_modified_counter_values[8], M1_power_modified_counter_values[9], M1_power_modified_counter_values[10]);
R1_q[6] = MEMORY_SEGMENT(R1_q[6]_data_in, VCC, R1_q[6]_clock_0, R1_q[6]_clock_1, R1_q[6]_clear_0, , R1_q[6]_clock_enable_1, VCC, R1_q[6]_write_address, R1_q[6]_read_address);


--R1_q[7] is nififo:dpm_ni2f_fifo_n|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|altdpram:dpram4|q[7]
R1_q[7]_data_in = ADC2_D[0];
R1_q[7]_clock_0 = !ADC2_D[2];
R1_q[7]_clock_1 = CLK50M;
R1_q[7]_clear_0 = dpm_ni2f_reg_sreset120;
R1_q[7]_clock_enable_1 = dpm_ni2f_reg_rdreq_fifo;
R1_q[7]_write_address = WR_ADDR(L1_power_modified_counter_values[0], L1_power_modified_counter_values[1], L1_power_modified_counter_values[2], L1_power_modified_counter_values[3], L1_power_modified_counter_values[4], L1_power_modified_counter_values[5], L1_power_modified_counter_values[6], L1_power_modified_counter_values[7], L1_power_modified_counter_values[8], L1_power_modified_counter_values[9], L1_power_modified_counter_values[10]);
R1_q[7]_read_address = RD_ADDR(R1L4, M1_power_modified_counter_values[1], M1_power_modified_counter_values[2], M1_power_modified_counter_values[3], M1_power_modified_counter_values[4], M1_power_modified_counter_values[5], M1_power_modified_counter_values[6], M1_power_modified_counter_values[7], M1_power_modified_counter_values[8], M1_power_modified_counter_values[9], M1_power_modified_counter_values[10]);
R1_q[7] = MEMORY_SEGMENT(R1_q[7]_data_in, VCC, R1_q[7]_clock_0, R1_q[7]_clock_1, R1_q[7]_clear_0, , R1_q[7]_clock_enable_1, VCC, R1_q[7]_write_address, R1_q[7]_read_address);


--R2_q[0] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|altdpram:dpram4|q[0]
R2_q[0]_data_in = ADC1_D[0];
R2_q[0]_clock_0 = ADC2_D[2];
R2_q[0]_clock_1 = CLK50M;
R2_q[0]_clear_0 = dpm_ni2f_reg_sreset120;
R2_q[0]_clock_enable_1 = dpm_ni2f_reg_rdreq_fifo;
R2_q[0]_write_address = WR_ADDR(L2_power_modified_counter_values[0], L2_power_modified_counter_values[1], L2_power_modified_counter_values[2], L2_power_modified_counter_values[3], L2_power_modified_counter_values[4], L2_power_modified_counter_values[5], L2_power_modified_counter_values[6], L2_power_modified_counter_values[7], L2_power_modified_counter_values[8], L2_power_modified_counter_values[9], L2_power_modified_counter_values[10]);
R2_q[0]_read_address = RD_ADDR(R2L4, M2_power_modified_counter_values[1], M2_power_modified_counter_values[2], M2_power_modified_counter_values[3], M2_power_modified_counter_values[4], M2_power_modified_counter_values[5], M2_power_modified_counter_values[6], M2_power_modified_counter_values[7], M2_power_modified_counter_values[8], M2_power_modified_counter_values[9], M2_power_modified_counter_values[10]);
R2_q[0] = MEMORY_SEGMENT(R2_q[0]_data_in, VCC, R2_q[0]_clock_0, R2_q[0]_clock_1, R2_q[0]_clear_0, , R2_q[0]_clock_enable_1, VCC, R2_q[0]_write_address, R2_q[0]_read_address);


--R2_q[1] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|altdpram:dpram4|q[1]
R2_q[1]_data_in = ADC1_D[1];
R2_q[1]_clock_0 = ADC2_D[2];
R2_q[1]_clock_1 = CLK50M;
R2_q[1]_clear_0 = dpm_ni2f_reg_sreset120;
R2_q[1]_clock_enable_1 = dpm_ni2f_reg_rdreq_fifo;
R2_q[1]_write_address = WR_ADDR(L2_power_modified_counter_values[0], L2_power_modified_counter_values[1], L2_power_modified_counter_values[2], L2_power_modified_counter_values[3], L2_power_modified_counter_values[4], L2_power_modified_counter_values[5], L2_power_modified_counter_values[6], L2_power_modified_counter_values[7], L2_power_modified_counter_values[8], L2_power_modified_counter_values[9], L2_power_modified_counter_values[10]);
R2_q[1]_read_address = RD_ADDR(R2L4, M2_power_modified_counter_values[1], M2_power_modified_counter_values[2], M2_power_modified_counter_values[3], M2_power_modified_counter_values[4], M2_power_modified_counter_values[5], M2_power_modified_counter_values[6], M2_power_modified_counter_values[7], M2_power_modified_counter_values[8], M2_power_modified_counter_values[9], M2_power_modified_counter_values[10]);
R2_q[1] = MEMORY_SEGMENT(R2_q[1]_data_in, VCC, R2_q[1]_clock_0, R2_q[1]_clock_1, R2_q[1]_clear_0, , R2_q[1]_clock_enable_1, VCC, R2_q[1]_write_address, R2_q[1]_read_address);


--R2_q[2] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|altdpram:dpram4|q[2]
R2_q[2]_data_in = ADC1_D[2];
R2_q[2]_clock_0 = ADC2_D[2];
R2_q[2]_clock_1 = CLK50M;
R2_q[2]_clear_0 = dpm_ni2f_reg_sreset120;
R2_q[2]_clock_enable_1 = dpm_ni2f_reg_rdreq_fifo;
R2_q[2]_write_address = WR_ADDR(L2_power_modified_counter_values[0], L2_power_modified_counter_values[1], L2_power_modified_counter_values[2], L2_power_modified_counter_values[3], L2_power_modified_counter_values[4], L2_power_modified_counter_values[5], L2_power_modified_counter_values[6], L2_power_modified_counter_values[7], L2_power_modified_counter_values[8], L2_power_modified_counter_values[9], L2_power_modified_counter_values[10]);
R2_q[2]_read_address = RD_ADDR(R2L4, M2_power_modified_counter_values[1], M2_power_modified_counter_values[2], M2_power_modified_counter_values[3], M2_power_modified_counter_values[4], M2_power_modified_counter_values[5], M2_power_modified_counter_values[6], M2_power_modified_counter_values[7], M2_power_modified_counter_values[8], M2_power_modified_counter_values[9], M2_power_modified_counter_values[10]);
R2_q[2] = MEMORY_SEGMENT(R2_q[2]_data_in, VCC, R2_q[2]_clock_0, R2_q[2]_clock_1, R2_q[2]_clear_0, , R2_q[2]_clock_enable_1, VCC, R2_q[2]_write_address, R2_q[2]_read_address);


--R2_q[3] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|altdpram:dpram4|q[3]
R2_q[3]_data_in = ADC1_D[3];
R2_q[3]_clock_0 = ADC2_D[2];
R2_q[3]_clock_1 = CLK50M;
R2_q[3]_clear_0 = dpm_ni2f_reg_sreset120;
R2_q[3]_clock_enable_1 = dpm_ni2f_reg_rdreq_fifo;
R2_q[3]_write_address = WR_ADDR(L2_power_modified_counter_values[0], L2_power_modified_counter_values[1], L2_power_modified_counter_values[2], L2_power_modified_counter_values[3], L2_power_modified_counter_values[4], L2_power_modified_counter_values[5], L2_power_modified_counter_values[6], L2_power_modified_counter_values[7], L2_power_modified_counter_values[8], L2_power_modified_counter_values[9], L2_power_modified_counter_values[10]);
R2_q[3]_read_address = RD_ADDR(R2L4, M2_power_modified_counter_values[1], M2_power_modified_counter_values[2], M2_power_modified_counter_values[3], M2_power_modified_counter_values[4], M2_power_modified_counter_values[5], M2_power_modified_counter_values[6], M2_power_modified_counter_values[7], M2_power_modified_counter_values[8], M2_power_modified_counter_values[9], M2_power_modified_counter_values[10]);
R2_q[3] = MEMORY_SEGMENT(R2_q[3]_data_in, VCC, R2_q[3]_clock_0, R2_q[3]_clock_1, R2_q[3]_clear_0, , R2_q[3]_clock_enable_1, VCC, R2_q[3]_write_address, R2_q[3]_read_address);


--R2_q[4] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|altdpram:dpram4|q[4]
R2_q[4]_data_in = ADC1_D[4];
R2_q[4]_clock_0 = ADC2_D[2];
R2_q[4]_clock_1 = CLK50M;
R2_q[4]_clear_0 = dpm_ni2f_reg_sreset120;
R2_q[4]_clock_enable_1 = dpm_ni2f_reg_rdreq_fifo;
R2_q[4]_write_address = WR_ADDR(L2_power_modified_counter_values[0], L2_power_modified_counter_values[1], L2_power_modified_counter_values[2], L2_power_modified_counter_values[3], L2_power_modified_counter_values[4], L2_power_modified_counter_values[5], L2_power_modified_counter_values[6], L2_power_modified_counter_values[7], L2_power_modified_counter_values[8], L2_power_modified_counter_values[9], L2_power_modified_counter_values[10]);
R2_q[4]_read_address = RD_ADDR(R2L4, M2_power_modified_counter_values[1], M2_power_modified_counter_values[2], M2_power_modified_counter_values[3], M2_power_modified_counter_values[4], M2_power_modified_counter_values[5], M2_power_modified_counter_values[6], M2_power_modified_counter_values[7], M2_power_modified_counter_values[8], M2_power_modified_counter_values[9], M2_power_modified_counter_values[10]);
R2_q[4] = MEMORY_SEGMENT(R2_q[4]_data_in, VCC, R2_q[4]_clock_0, R2_q[4]_clock_1, R2_q[4]_clear_0, , R2_q[4]_clock_enable_1, VCC, R2_q[4]_write_address, R2_q[4]_read_address);


--R2_q[5] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|altdpram:dpram4|q[5]
R2_q[5]_data_in = ADC1_D[5];
R2_q[5]_clock_0 = ADC2_D[2];
R2_q[5]_clock_1 = CLK50M;
R2_q[5]_clear_0 = dpm_ni2f_reg_sreset120;
R2_q[5]_clock_enable_1 = dpm_ni2f_reg_rdreq_fifo;
R2_q[5]_write_address = WR_ADDR(L2_power_modified_counter_values[0], L2_power_modified_counter_values[1], L2_power_modified_counter_values[2], L2_power_modified_counter_values[3], L2_power_modified_counter_values[4], L2_power_modified_counter_values[5], L2_power_modified_counter_values[6], L2_power_modified_counter_values[7], L2_power_modified_counter_values[8], L2_power_modified_counter_values[9], L2_power_modified_counter_values[10]);
R2_q[5]_read_address = RD_ADDR(R2L4, M2_power_modified_counter_values[1], M2_power_modified_counter_values[2], M2_power_modified_counter_values[3], M2_power_modified_counter_values[4], M2_power_modified_counter_values[5], M2_power_modified_counter_values[6], M2_power_modified_counter_values[7], M2_power_modified_counter_values[8], M2_power_modified_counter_values[9], M2_power_modified_counter_values[10]);
R2_q[5] = MEMORY_SEGMENT(R2_q[5]_data_in, VCC, R2_q[5]_clock_0, R2_q[5]_clock_1, R2_q[5]_clear_0, , R2_q[5]_clock_enable_1, VCC, R2_q[5]_write_address, R2_q[5]_read_address);


--R2_q[6] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|altdpram:dpram4|q[6]
R2_q[6]_data_in = ADC1_D[6];
R2_q[6]_clock_0 = ADC2_D[2];
R2_q[6]_clock_1 = CLK50M;
R2_q[6]_clear_0 = dpm_ni2f_reg_sreset120;
R2_q[6]_clock_enable_1 = dpm_ni2f_reg_rdreq_fifo;
R2_q[6]_write_address = WR_ADDR(L2_power_modified_counter_values[0], L2_power_modified_counter_values[1], L2_power_modified_counter_values[2], L2_power_modified_counter_values[3], L2_power_modified_counter_values[4], L2_power_modified_counter_values[5], L2_power_modified_counter_values[6], L2_power_modified_counter_values[7], L2_power_modified_counter_values[8], L2_power_modified_counter_values[9], L2_power_modified_counter_values[10]);
R2_q[6]_read_address = RD_ADDR(R2L4, M2_power_modified_counter_values[1], M2_power_modified_counter_values[2], M2_power_modified_counter_values[3], M2_power_modified_counter_values[4], M2_power_modified_counter_values[5], M2_power_modified_counter_values[6], M2_power_modified_counter_values[7], M2_power_modified_counter_values[8], M2_power_modified_counter_values[9], M2_power_modified_counter_values[10]);
R2_q[6] = MEMORY_SEGMENT(R2_q[6]_data_in, VCC, R2_q[6]_clock_0, R2_q[6]_clock_1, R2_q[6]_clear_0, , R2_q[6]_clock_enable_1, VCC, R2_q[6]_write_address, R2_q[6]_read_address);


--R2_q[7] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|altdpram:dpram4|q[7]
R2_q[7]_data_in = ADC2_D[0];
R2_q[7]_clock_0 = ADC2_D[2];
R2_q[7]_clock_1 = CLK50M;
R2_q[7]_clear_0 = dpm_ni2f_reg_sreset120;
R2_q[7]_clock_enable_1 = dpm_ni2f_reg_rdreq_fifo;
R2_q[7]_write_address = WR_ADDR(L2_power_modified_counter_values[0], L2_power_modified_counter_values[1], L2_power_modified_counter_values[2], L2_power_modified_counter_values[3], L2_power_modified_counter_values[4], L2_power_modified_counter_values[5], L2_power_modified_counter_values[6], L2_power_modified_counter_values[7], L2_power_modified_counter_values[8], L2_power_modified_counter_values[9], L2_power_modified_counter_values[10]);
R2_q[7]_read_address = RD_ADDR(R2L4, M2_power_modified_counter_values[1], M2_power_modified_counter_values[2], M2_power_modified_counter_values[3], M2_power_modified_counter_values[4], M2_power_modified_counter_values[5], M2_power_modified_counter_values[6], M2_power_modified_counter_values[7], M2_power_modified_counter_values[8], M2_power_modified_counter_values[9], M2_power_modified_counter_values[10]);
R2_q[7] = MEMORY_SEGMENT(R2_q[7]_data_in, VCC, R2_q[7]_clock_0, R2_q[7]_clock_1, R2_q[7]_clear_0, , R2_q[7]_clock_enable_1, VCC, R2_q[7]_write_address, R2_q[7]_read_address);


--Z1_ack64_OR_not is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|ack64_OR_not
--operation mode is normal

Z1_ack64_OR_not = AMPP_FUNCTION(Z1_devsel_OR_lc[1], Z1_trans64_R, GND, A1L234, !pci_rstn, GLOBAL(pci_clk), Z1L71);


--W1L664 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|tgt_64_response_reg~36
--operation mode is normal

W1L664 = AMPP_FUNCTION(W1_tgt_64_response_set, Z1_ack64_OR_not);


--U1_ad_IR_ce_data is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|ad_IR_ce_data
--operation mode is normal

U1_ad_IR_ce_data = AMPP_FUNCTION(U1_mstr_ad_IR_ce_D, U1_trg_ad_IR_ce_D);


--Z1_lt_ldata_ack_r_d[5] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_ldata_ack_r_d[5]
--operation mode is normal

Z1_lt_ldata_ack_r_d[5] = AMPP_FUNCTION(Z1_lt_ldata_ack_r_prn3, Z1_lt_ldata_ack_r_d[3], Z1_lt_ldata_ack_r_d[4], W1_mstr_actv_lc);


--Z1_LW_DONE is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|LW_DONE
--operation mode is normal

Z1_LW_DONE = AMPP_FUNCTION(Z1_LW_DONE_lc[2], Z1_LW_LXFR, pci_rstn, GLOBAL(pci_clk), Z1_$00214);


--Z1_lt_ldata_ack_r_d[1] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_ldata_ack_r_d[1]
--operation mode is normal

Z1_lt_ldata_ack_r_d[1] = AMPP_FUNCTION(Z1_LW_DONE, Z1_LW_IDLE_NOT);


--W1_MS_ADR is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MS_ADR
--operation mode is normal

W1_MS_ADR = AMPP_FUNCTION(W1_MS_ENA, pci_gntn, pci_rstn, GLOBAL(pci_clk));


--W1_lm_ldata_ack_lc[4] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|lm_ldata_ack_lc[4]
--operation mode is normal

W1_lm_ldata_ack_lc[4] = AMPP_FUNCTION(W1_MS_ADR, W1_lm_ldata_ack_lc[3], W1L562, W1L662);


--Z1_LR_DONE is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|LR_DONE
--operation mode is normal

Z1_LR_DONE = AMPP_FUNCTION(A1L234, Z1_LR_DONE_lc[2], Z1_LR_DONE_lc[1], pci_rstn, GLOBAL(pci_clk));


--W1_MW_IDLE_not is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MW_IDLE_not
--operation mode is normal

W1_MW_IDLE_not = AMPP_FUNCTION(W1_MW_END, W1_MW_IDLE_lc1, pci_gntn, W1_MW_IDLE_not, pci_rstn, GLOBAL(pci_clk));


--W1_MR_IDLE_not is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MR_IDLE_not
--operation mode is normal

W1_MR_IDLE_not = AMPP_FUNCTION(W1_MR_END, W1_MR_IDLE_not, W1_MR_IDLE_lc1, pci_rstn, GLOBAL(pci_clk));


--W1_mstr_actv_lc is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|mstr_actv_lc
--operation mode is normal

W1_mstr_actv_lc = AMPP_FUNCTION(W1_MW_IDLE_not, W1_MR_IDLE_not);


--Z1L03 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|$00210~2
--operation mode is arithmetic

Z1L03 = AMPP_FUNCTION(Z1_TS_TURN_AR, Z1_LW_LXFR);

--Z1_$00210 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|$00210
--operation mode is arithmetic

Z1_$00210 = AMPP_FUNCTION(Z1_TS_TURN_AR, Z1_LW_LXFR);


--Z1_LW_LXFR is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|LW_LXFR
--operation mode is normal

Z1_LW_LXFR = AMPP_FUNCTION(Z1_LW_LXFR_lc[1], Z1_LW_LXFR_lc[2], pci_rstn, GLOBAL(pci_clk), Z1_$00209);


--Z1_TS_DISC is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|TS_DISC
--operation mode is normal

Z1_TS_DISC = AMPP_FUNCTION(Z1_TS_DISC, Z1_TS_DISC_d_lc2, A1L234, Z1L073, pci_rstn, GLOBAL(pci_clk));


--Z1L35 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|_~40
--operation mode is normal

Z1L35 = AMPP_FUNCTION(Z1L03, Z1_LW_LXFR, Z1_TS_DISC, Z1_trdy_OR_NOT);


--U1_ad_ir_address[19] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|ad_ir_address[19]
--operation mode is normal

U1_ad_ir_address[19] = AMPP_FUNCTION(U1_ad_IR_ce_address, pci_ad_19, pci_rstn, GLOBAL(pci_clk));


--Z1L922 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_adr[19]~0
--operation mode is normal

Z1L922 = AMPP_FUNCTION(Z1_no_op_reg[1], U1_ad_ir_address[19]);


--U1_cben_ir_address[1] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|cben_ir_address[1]
--operation mode is normal

U1_cben_ir_address[1] = AMPP_FUNCTION(U1_cben_IR_ce_address, pci_cben_1, pci_rstn, GLOBAL(pci_clk));


--ix2053_lc is ix2053_lc
--operation mode is normal

ix2053_lc = !Z1L922 & !Z1L512 & Z1L412 & U1_cben_ir_address[1];


--U1_mstr_trg_low is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|mstr_trg_low
--operation mode is normal

U1_mstr_trg_low = AMPP_FUNCTION(U1_mstr_trg_low_ad_out_sel, U1_trg_cfg_cyc_out, U1_mstr_trg_hr_dat_sel);


--Z1L2 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|$00086~0
--operation mode is normal

Z1L2 = AMPP_FUNCTION(Z1_stop_OR_NOT, Z1_trdy_OR_NOT, A1L234);


--Z1_TS_TURN_AR is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|TS_TURN_AR
--operation mode is normal

Z1_TS_TURN_AR = AMPP_FUNCTION(A1L234, Z1_TS_TURN_AR_d_lc1, Z1_TS_DISC, Z1_low_dword_discard, pci_rstn, GLOBAL(pci_clk));


--W1_cbe_oer_r2_d is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|cbe_oer_r2_d
--operation mode is normal

W1_cbe_oer_r2_d = AMPP_FUNCTION(W1_MS_ENA, W1_MS_PARK);


--W1L48 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|_~325
--operation mode is normal

W1L48 = AMPP_FUNCTION(W1_ad_oer_lc2d, W1_cbe_oer_r2_d, W1_ad_oer_lc2a, pci_gntn);


--dpm_ni2f_reg_sram_qH_12 is dpm_ni2f_reg_sram_qH_12
--operation mode is normal

dpm_ni2f_reg_sram_qH_12_lut_out = SRAM_IO_12;
dpm_ni2f_reg_sram_qH_12 = DFFEA(dpm_ni2f_reg_sram_qH_12_lut_out, CLK50M, , , dpm_ni2f_reg_sm_10, , );


--dpm_ni2f_reg_sram_qH_13 is dpm_ni2f_reg_sram_qH_13
--operation mode is normal

dpm_ni2f_reg_sram_qH_13_lut_out = SRAM_IO_13;
dpm_ni2f_reg_sram_qH_13 = DFFEA(dpm_ni2f_reg_sram_qH_13_lut_out, CLK50M, , , dpm_ni2f_reg_sm_10, , );


--W1_MS_ADR2 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MS_ADR2
--operation mode is normal

W1_MS_ADR2 = AMPP_FUNCTION(W1_MS_ADR, W1_dac_cyc_reg, pci_rstn, GLOBAL(pci_clk));


--W1_dac_cyc_reg is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|dac_cyc_reg
--operation mode is normal

W1_dac_cyc_reg = AMPP_FUNCTION(W1_MS_IDLE_not, W1_dac_cmd, W1_lm_adr_ack_R, W1_dac_cyc_reg, pci_rstn, GLOBAL(pci_clk));


--U1_mstr_cbe_ce is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|mstr_cbe_ce
--operation mode is normal

U1_mstr_cbe_ce = AMPP_FUNCTION(W1_MS_ENA, W1_MS_ADR, W1_MS_ADR2, W1_dac_cyc_reg);


--W1L38 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|_~316
--operation mode is normal

W1L38 = AMPP_FUNCTION(W1_cbe_oer_r1_lc3, W1_cbe_oer_r1_lc1, W1_cbe_oer_r2_d, pci_gntn);


--Z1L76 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|_~189
--operation mode is normal

Z1L76 = AMPP_FUNCTION(A1L734, Z1_devsel_OR_lc[3], Z1_devsel_OR_lc[1], A1L234);


--Z1_TS_ADR_VLD is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|TS_ADR_VLD
--operation mode is normal

Z1_TS_ADR_VLD = AMPP_FUNCTION(BB1_mbar_hit, Z1L311, Z1_TS_IDLE_NOT, pci_rstn, GLOBAL(pci_clk));


--Z1_targ_oeR_reg_lc[4] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|targ_oeR_reg_lc[4]
--operation mode is normal

Z1_targ_oeR_reg_lc[4] = AMPP_FUNCTION(Z1_targ_oeR_reg_lc[3], Z1_adr_phase_lc1, Z1_targ_oeR_reg_lc[2], Z1_targ_oeR_reg_lc[1]);


--W1L62 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00159~2
--operation mode is arithmetic

W1L62 = AMPP_FUNCTION(A1L944, W1_frame_or_lc3);

--W1_$00159 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00159
--operation mode is arithmetic

W1_$00159 = AMPP_FUNCTION(A1L944, W1_frame_or_lc3);


--W1L82 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00165~2
--operation mode is arithmetic

W1L82 = AMPP_FUNCTION(A1L744, W1_frame_or_lc2);

--W1_$00165 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00165
--operation mode is arithmetic

W1_$00165 = AMPP_FUNCTION(A1L744, W1_frame_or_lc2);


--W1L77 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|_~230
--operation mode is normal

W1L77 = AMPP_FUNCTION(W1L651, W1L82, W1_$00159);


--W1_dac_cyc_strobe is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|dac_cyc_strobe
--operation mode is normal

W1_dac_cyc_strobe = AMPP_FUNCTION(W1_MS_ENA, W1_dac_cmd, pci_gntn, pci_rstn, GLOBAL(pci_clk));


--W1_MS_DXFR is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MS_DXFR
--operation mode is normal

W1_MS_DXFR = AMPP_FUNCTION(W1_ms_dxfr_lc1, W1_ms_dxfr_lc2, W1L02, pci_rstn, GLOBAL(pci_clk));


--W1_irdy_oer_lc1 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|irdy_oer_lc1
--operation mode is normal

W1_irdy_oer_lc1 = AMPP_FUNCTION(W1_MS_ADR, W1_MS_ADR2, W1_MS_DXFR);


--U1_mstr_par_oe_lc2 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|mstr_par_oe_lc2
--operation mode is normal

U1_mstr_par_oe_lc2 = AMPP_FUNCTION(W1_MS_ADR, W1_MS_ADR2, U1_trg_par_oe, U1_mstr_par_oe_lc1);


--U1_par64_or is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|par64_or
--operation mode is normal

U1_par64_or = AMPP_FUNCTION(pci_rstn, GLOBAL(pci_clk), Y2_parc[10]);


--X1_par_error64 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pk:parity_Chk|par_error64
--operation mode is normal

X1_par_error64 = AMPP_FUNCTION(U1_par_oeR, U1_par64_or, X1_xxh[11]);


--X1L3 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pk:parity_Chk|_~74
--operation mode is normal

X1L3 = AMPP_FUNCTION(X1_par_error64, X1_perr_or_not_lc2, X1_perr_or_not_lc3);


--W1_MS_TAR is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MS_TAR
--operation mode is normal

W1_MS_TAR = AMPP_FUNCTION(W1_$00202, W1L02, W1_$00203, pci_rstn, GLOBAL(pci_clk));


--W1_wr_rdn is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|wr_rdn
--operation mode is normal

W1_wr_rdn = AMPP_FUNCTION(W1_wr_rdn_set, W1_wr_rdn, W1_MS_TAR, pci_rstn, GLOBAL(pci_clk));


--Z1L57 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|_~1514
--operation mode is normal

Z1L57 = AMPP_FUNCTION(U1_cben_ir_address[0], U1_cben_ir_address[1], Z1_adr_phase_lc1, Z1_LW_IDLE_NOT);


--DB1_decR[1] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|pcimt64_cd:cfg_adr_dec|decR[1]
--operation mode is normal

DB1_decR[1] = AMPP_FUNCTION(Z1_cfg_adr_dec_ena, DB1_dec_up[0], U1_ad_ir_address[2], U1_ad_ir_address[3], pci_rstn, GLOBAL(pci_clk));


--U1_low_cben_IR_data[0] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_cben_IR_data[0]
--operation mode is normal

U1_low_cben_IR_data[0] = AMPP_FUNCTION(U1_cben_IR_ce_data, pci_cben_0, pci_rstn, GLOBAL(pci_clk));


--BB1L59 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|stat_cmd_ena[0]~49
--operation mode is normal

BB1L59 = AMPP_FUNCTION(Z1_cfg_dat_vld, DB1_decR[1], U1_low_cben_IR_data[0]);


--U1_low_cben_IR_data[1] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_cben_IR_data[1]
--operation mode is normal

U1_low_cben_IR_data[1] = AMPP_FUNCTION(U1_cben_IR_ce_data, pci_cben_1, pci_rstn, GLOBAL(pci_clk));


--BB1L69 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|stat_cmd_ena[1]~50
--operation mode is normal

BB1L69 = AMPP_FUNCTION(Z1_cfg_dat_vld, DB1_decR[1], U1_low_cben_IR_data[1]);


--X1_xxlad[10] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pk:parity_Chk|xxlad[10]
--operation mode is normal

X1_xxlad[10] = AMPP_FUNCTION(X1_xxlad[7], X1_xxlad[6], X1_xxlad[5], X1_xxlad[4]);


--X1_xxlad[9] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pk:parity_Chk|xxlad[9]
--operation mode is normal

X1_xxlad[9] = AMPP_FUNCTION(X1_xxlad[3], X1_xxlad[2], X1_xxlad[1], X1_xxlad[0]);


--X1_xxlad[8] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pk:parity_Chk|xxlad[8]
--operation mode is normal

X1_xxlad[8] = AMPP_FUNCTION(U1_cben_ir_address[0], U1_cben_ir_address[3], U1_cben_ir_address[2], U1_cben_ir_address[1]);


--Z1L26 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|_~149
--operation mode is normal

Z1L26 = AMPP_FUNCTION(Z1L623, A1L234, A1L734, Z1L523);


--Z1L36 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|_~157
--operation mode is normal

Z1L36 = AMPP_FUNCTION(A1L734, Z1_trdy_OR_NOT, Z1L263);


--U1_high_ad_IR_data[7] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_IR_data[7]
--operation mode is normal

U1_high_ad_IR_data[7] = AMPP_FUNCTION(U1_ad_IR_ce_data, W1_ad_oer, U1_high_ad_or[39], Z1_adoe, pci_rstn, GLOBAL(pci_clk));


--U1L922 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|l_dato[39]~51
--operation mode is normal

U1L922 = AMPP_FUNCTION(U1_high_ad_IR_data[7], U1_low_ad_IR_data[7], U1_local_dat_sel);


--U1_high_ad_IR_data[6] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_IR_data[6]
--operation mode is normal

U1_high_ad_IR_data[6] = AMPP_FUNCTION(U1_ad_IR_ce_data, W1_ad_oer, U1_high_ad_or[38], Z1_adoe, pci_rstn, GLOBAL(pci_clk));


--U1L822 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|l_dato[38]~52
--operation mode is normal

U1L822 = AMPP_FUNCTION(U1_high_ad_IR_data[6], U1_low_ad_IR_data[6], U1_local_dat_sel);


--U1_high_ad_IR_data[5] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_IR_data[5]
--operation mode is normal

U1_high_ad_IR_data[5] = AMPP_FUNCTION(U1_ad_IR_ce_data, W1_ad_oer, U1_high_ad_or[37], Z1_adoe, pci_rstn, GLOBAL(pci_clk));


--U1L722 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|l_dato[37]~53
--operation mode is normal

U1L722 = AMPP_FUNCTION(U1_high_ad_IR_data[5], U1_low_ad_IR_data[5], U1_local_dat_sel);


--U1_high_ad_IR_data[4] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_IR_data[4]
--operation mode is normal

U1_high_ad_IR_data[4] = AMPP_FUNCTION(U1_ad_IR_ce_data, W1_ad_oer, U1_high_ad_or[36], Z1_adoe, pci_rstn, GLOBAL(pci_clk));


--U1L622 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|l_dato[36]~54
--operation mode is normal

U1L622 = AMPP_FUNCTION(U1_high_ad_IR_data[4], U1_low_ad_IR_data[4], U1_local_dat_sel);


--U1_high_ad_IR_data[3] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_IR_data[3]
--operation mode is normal

U1_high_ad_IR_data[3] = AMPP_FUNCTION(U1_ad_IR_ce_data, W1_ad_oer, U1_high_ad_or[35], Z1_adoe, pci_rstn, GLOBAL(pci_clk));


--U1L522 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|l_dato[35]~55
--operation mode is normal

U1L522 = AMPP_FUNCTION(U1_high_ad_IR_data[3], U1_low_ad_IR_data[3], U1_local_dat_sel);


--U1_high_ad_IR_data[2] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_IR_data[2]
--operation mode is normal

U1_high_ad_IR_data[2] = AMPP_FUNCTION(U1_ad_IR_ce_data, W1_ad_oer, U1_high_ad_or[34], Z1_adoe, pci_rstn, GLOBAL(pci_clk));


--U1L422 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|l_dato[34]~56
--operation mode is normal

U1L422 = AMPP_FUNCTION(U1_high_ad_IR_data[2], U1_low_ad_IR_data[2], U1_local_dat_sel);


--U1_high_ad_IR_data[1] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_IR_data[1]
--operation mode is normal

U1_high_ad_IR_data[1] = AMPP_FUNCTION(U1_ad_IR_ce_data, W1_ad_oer, U1_high_ad_or[33], Z1_adoe, pci_rstn, GLOBAL(pci_clk));


--U1L322 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|l_dato[33]~57
--operation mode is normal

U1L322 = AMPP_FUNCTION(U1_high_ad_IR_data[1], U1_low_ad_IR_data[1], U1_local_dat_sel);


--U1_high_ad_IR_data[0] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_IR_data[0]
--operation mode is normal

U1_high_ad_IR_data[0] = AMPP_FUNCTION(U1_ad_IR_ce_data, W1_ad_oer, U1_high_ad_or[32], Z1_adoe, pci_rstn, GLOBAL(pci_clk));


--U1L222 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|l_dato[32]~58
--operation mode is normal

U1L222 = AMPP_FUNCTION(U1_high_ad_IR_data[0], U1_low_ad_IR_data[0], U1_local_dat_sel);


--ix2066_lc is ix2066_lc
--operation mode is normal

ix2066_lc = dpm_ni2f_reg_sm_0 & (dpm_ni2f_reg_sm_5 # dpm_ni2f_reg_sm_3 # dpm_ni2f_reg_sm_2);


--U1_ad_IR_ce_address is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|ad_IR_ce_address
--operation mode is normal

U1_ad_IR_ce_address = AMPP_FUNCTION(W1_MS_ADR, U1_trg_ad_IR_ce_A, W1_MS_ADR2);


--ix2056 is ix2056
--operation mode is normal

ix2056 = dpm_ni2f_reg_end_marker32 # dpm_ni2f_reg_timeout # dpm_ni2f_reg_rdreq_fifo # !dpm_ni2f_reg_sm_1;


--A1L871 is ix2001_lc~0
--operation mode is normal

A1L871 = (!dpm_ni2f_reg_sm_2 & (dpm_ni2f_reg_sm_0 # !dpm_ni2f_reg_rdempty_s)) & CASCADE(ix2056);


--N3_add_sub_cella[9] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|add_sub_tjb:add_sub16|add_sub_cella[9]
--operation mode is arithmetic

N3_add_sub_cella[9] = E5_q[9] $ Q7_dffe51a[9] $ N3L02;

--N3L22 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|add_sub_tjb:add_sub16|add_sub_cella[9]~COUT
--operation mode is arithmetic

N3L22 = CARRY(E5_q[9] & Q7_dffe51a[9] & N3L02 # !E5_q[9] & (Q7_dffe51a[9] # N3L02));


--N3_add_sub_cella[8] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|add_sub_tjb:add_sub16|add_sub_cella[8]
--operation mode is arithmetic

N3_add_sub_cella[8] = E5_q[8] $ Q7_dffe51a[8] $ N3L81;

--N3L02 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|add_sub_tjb:add_sub16|add_sub_cella[8]~COUT
--operation mode is arithmetic

N3L02 = CARRY(E5_q[8] & Q7_dffe51a[8] & N3L81 # !E5_q[8] & (Q7_dffe51a[8] # N3L81));


--N3_add_sub_cella[7] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|add_sub_tjb:add_sub16|add_sub_cella[7]
--operation mode is arithmetic

N3_add_sub_cella[7] = E5_q[7] $ Q7_dffe51a[7] $ N3L61;

--N3L81 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|add_sub_tjb:add_sub16|add_sub_cella[7]~COUT
--operation mode is arithmetic

N3L81 = CARRY(E5_q[7] & Q7_dffe51a[7] & N3L61 # !E5_q[7] & (Q7_dffe51a[7] # N3L61));


--N3_add_sub_cella[6] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|add_sub_tjb:add_sub16|add_sub_cella[6]
--operation mode is arithmetic

N3_add_sub_cella[6] = E5_q[6] $ Q7_dffe51a[6] $ N3L41;

--N3L61 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|add_sub_tjb:add_sub16|add_sub_cella[6]~COUT
--operation mode is arithmetic

N3L61 = CARRY(E5_q[6] & Q7_dffe51a[6] & N3L41 # !E5_q[6] & (Q7_dffe51a[6] # N3L41));


--N3_add_sub_cella[5] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|add_sub_tjb:add_sub16|add_sub_cella[5]
--operation mode is arithmetic

N3_add_sub_cella[5] = E5_q[5] $ Q7_dffe51a[5] $ N3L21;

--N3L41 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|add_sub_tjb:add_sub16|add_sub_cella[5]~COUT
--operation mode is arithmetic

N3L41 = CARRY(E5_q[5] & Q7_dffe51a[5] & N3L21 # !E5_q[5] & (Q7_dffe51a[5] # N3L21));


--N3_add_sub_cella[4] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|add_sub_tjb:add_sub16|add_sub_cella[4]
--operation mode is arithmetic

N3_add_sub_cella[4] = E5_q[4] $ Q7_dffe51a[4] $ N3L01;

--N3L21 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|add_sub_tjb:add_sub16|add_sub_cella[4]~COUT
--operation mode is arithmetic

N3L21 = CARRY(E5_q[4] & Q7_dffe51a[4] & N3L01 # !E5_q[4] & (Q7_dffe51a[4] # N3L01));


--N3_add_sub_cella[3] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|add_sub_tjb:add_sub16|add_sub_cella[3]
--operation mode is arithmetic

N3_add_sub_cella[3] = E5_q[3] $ Q7_dffe51a[3] $ N3L8;

--N3L01 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|add_sub_tjb:add_sub16|add_sub_cella[3]~COUT
--operation mode is arithmetic

N3L01 = CARRY(E5_q[3] & Q7_dffe51a[3] & N3L8 # !E5_q[3] & (Q7_dffe51a[3] # N3L8));


--N3_add_sub_cella[1] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|add_sub_tjb:add_sub16|add_sub_cella[1]
--operation mode is arithmetic

N3_add_sub_cella[1] = E5_q[1] $ Q7_dffe51a[1] $ N3L4;

--N3L6 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|add_sub_tjb:add_sub16|add_sub_cella[1]~COUT
--operation mode is arithmetic

N3L6 = CARRY(E5_q[1] & Q7_dffe51a[1] & N3L4 # !E5_q[1] & (Q7_dffe51a[1] # N3L4));


--N3_add_sub_cella[2] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|add_sub_tjb:add_sub16|add_sub_cella[2]
--operation mode is arithmetic

N3_add_sub_cella[2] = E5_q[2] $ Q7_dffe51a[2] $ N3L6;

--N3L8 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|add_sub_tjb:add_sub16|add_sub_cella[2]~COUT
--operation mode is arithmetic

N3L8 = CARRY(E5_q[2] & Q7_dffe51a[2] & N3L6 # !E5_q[2] & (Q7_dffe51a[2] # N3L6));


--N3_add_sub_cella[0] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|add_sub_tjb:add_sub16|add_sub_cella[0]
--operation mode is arithmetic

N3_add_sub_cella[0] = E5_q[0] $ Q7_dffe51a[0];

--N3L4 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|add_sub_tjb:add_sub16|add_sub_cella[0]~COUT
--operation mode is arithmetic

N3L4 = CARRY(Q7_dffe51a[0] # !E5_q[0]);


--dpm_ni2f_reg_sm_8 is dpm_ni2f_reg_sm_8
--operation mode is normal

dpm_ni2f_reg_sm_8_lut_out = dpm_ni2f_reg_sm_7;
dpm_ni2f_reg_sm_8 = DFFEA(dpm_ni2f_reg_sm_8_lut_out, CLK50M, !ix2000_lc, , , , );


--ix2064 is ix2064
--operation mode is normal

ix2064 = U1_cben_ir_address[3] & U1_cben_ir_address[2] # !U1_cben_ir_address[3] & U1_cben_ir_address[1];


--dpm_ni2f_reg_sm_6 is dpm_ni2f_reg_sm_6
--operation mode is normal

dpm_ni2f_reg_sm_6_lut_out = dpm_ni2f_reg_sm_5;
dpm_ni2f_reg_sm_6 = DFFEA(dpm_ni2f_reg_sm_6_lut_out, CLK50M, !ix2000_lc, , , , );


--U1_high_data_out_HR[8] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_data_out_HR[8]
--operation mode is normal

U1_high_data_out_HR[8] = AMPP_FUNCTION(U1_high_data_out_HR_ena, U1_trg_ad_sel, U1_mstr_ad_sel, A1L361, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_out_lc[8] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_out_lc[8]
--operation mode is normal

U1_high_ad_out_lc[8] = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_high_data_out_HR[8], U1_trg_ad_sel, U1_mstr_ad_sel);


--U1_mstr_trg_hi_ad is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|mstr_trg_hi_ad
--operation mode is normal

U1_mstr_trg_hi_ad = AMPP_FUNCTION(U1_trg_ad_sel, U1_mstr_ad_sel, U1_mstr_trg_hr_dat_sel);


--W1_tgt_64_response_set is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|tgt_64_response_set
--operation mode is normal

W1_tgt_64_response_set = AMPP_FUNCTION(W1_MS_IDLE_not, W1_MS_REQ);


--W1_MR_END is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MR_END
--operation mode is normal

W1_MR_END = AMPP_FUNCTION(W1_MR_END_d_lc1, W1_no_op_reg[6], A1L744, pci_rstn, GLOBAL(pci_clk), W1_$00269);


--W1_tgt_64_response_reset is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|tgt_64_response_reset
--operation mode is normal

W1_tgt_64_response_reset = AMPP_FUNCTION(W1_MS_REQ, W1_tgt_64_response_reset_lc1, W1_MR_END);


--W1L652 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|lm_hdata_ack~0
--operation mode is normal

W1L652 = AMPP_FUNCTION(W1_lm_hdata_ack_lc[8], Z1_targ_oeR_reg, W1_lm_hdata_ack_lc[6], Z1_ack64_OR_not);


--Z1_lt_hdata_ack_r_d[4] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_hdata_ack_r_d[4]
--operation mode is normal

Z1_lt_hdata_ack_r_d[4] = AMPP_FUNCTION(Z1_lt_hdata_ack_r_d4_lc, W1_mstr_actv_lc);


--Z1_mem_cyc is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|mem_cyc
--operation mode is normal

Z1_mem_cyc = AMPP_FUNCTION(Z1_mem_cyc, Z1_adr_phase_lc1, Z1_mem_cyc_s_lc, Z1_TS_IDLE_NOT, pci_rstn, GLOBAL(pci_clk));


--Z1_lt_hdata_ack_r_d[1] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_hdata_ack_r_d[1]
--operation mode is normal

Z1_lt_hdata_ack_r_d[1] = AMPP_FUNCTION(Z1_lt_ldata_ack_r_d[1], Z1_mem_cyc);


--W1_MR_LLWAIT_r1 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MR_LLWAIT_r1
--operation mode is normal

W1_MR_LLWAIT_r1 = AMPP_FUNCTION(W1_MR_LLWAIT_r1_lc2, A1L744, pci_rstn, GLOBAL(pci_clk), W1_$00262);


--W1_MR_LLWAIT_r2 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MR_LLWAIT_r2
--operation mode is normal

W1_MR_LLWAIT_r2 = AMPP_FUNCTION(W1_devsel_toR, pci_rstn, GLOBAL(pci_clk), W1_$00263);


--W1_MR_LLWAIT_r1_lc2 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MR_LLWAIT_r1_lc2
--operation mode is normal

W1_MR_LLWAIT_r1_lc2 = AMPP_FUNCTION(W1_MR_LLWAIT_r1, W1_MR_LLWAIT_r2);


--W1_MR_LLXFR_r1 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MR_LLXFR_r1
--operation mode is normal

W1_MR_LLXFR_r1 = AMPP_FUNCTION(W1L04, W1_MR_LLXFR_r1_d_lc1, A1L744, pci_rstn, GLOBAL(pci_clk));


--W1_MR_LLXFR_r2 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MR_LLXFR_r2
--operation mode is normal

W1_MR_LLXFR_r2 = AMPP_FUNCTION(pci_rstn, GLOBAL(pci_clk), W1_$00266);


--W1_MR_LLXFR is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MR_LLXFR
--operation mode is normal

W1_MR_LLXFR = AMPP_FUNCTION(W1_MR_LLXFR_r1, W1_MR_LLXFR_r2);


--W1_MR_LWAIT is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MR_LWAIT
--operation mode is normal

W1_MR_LWAIT = AMPP_FUNCTION(W1_MR_LWAIT_lc2, A1L744, pci_rstn, GLOBAL(pci_clk), W1_$00259);


--U1_mstr_ad_IR_ce_D is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|mstr_ad_IR_ce_D
--operation mode is normal

U1_mstr_ad_IR_ce_D = AMPP_FUNCTION(W1_MS_IDLE_not, W1_MR_LLWAIT_r1_lc2, W1_MR_LLXFR, W1_MR_LWAIT);


--Z1_cfg_cyc is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|cfg_cyc
--operation mode is normal

Z1_cfg_cyc = AMPP_FUNCTION(Z1L011, Z1_cfg_cyc, Z1_TS_IDLE_NOT, Z1_adr_phase_lc1, pci_rstn, GLOBAL(pci_clk));


--U1_trg_ad_IR_ce_D is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|trg_ad_IR_ce_D
--operation mode is normal

U1_trg_ad_IR_ce_D = AMPP_FUNCTION(Z1_ad_ir_ce_D_lc1, Z1_TS_TURN_AR, Z1_cfg_cyc, W1_mstr_actv_lc);


--Z1_TS_ADR_CLMD is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|TS_ADR_CLMD
--operation mode is normal

Z1_TS_ADR_CLMD = AMPP_FUNCTION(Z1L763, Z1_TS_ADR_VLD, dpm_dec_reg_LT_RDY_n_pci, X1_serr_or, pci_rstn, GLOBAL(pci_clk));


--Z1L27 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|_~255
--operation mode is normal

Z1L27 = AMPP_FUNCTION(Z1_TS_ADR_VLD, Z1_TS_ADR_CLMD);


--Z1_retry is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|retry
--operation mode is normal

Z1_retry = AMPP_FUNCTION(Z1_retry_set, Z1_retry, Z1_retry_rst_lc2, pci_rstn, GLOBAL(pci_clk));


--Z1_lt_ldata_ack_r_prn3 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_ldata_ack_r_prn3
--operation mode is normal

Z1_lt_ldata_ack_r_prn3 = AMPP_FUNCTION(Z1_lt_ldata_ack_r_prn1, Z1L27, Z1_mem_cyc, Z1_retry);


--Z1_lt_ldata_ack_r_d[3] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_ldata_ack_r_d[3]
--operation mode is normal

Z1_lt_ldata_ack_r_d[3] = AMPP_FUNCTION(Z1_TS_IDLE_NOT, Z1_lt_ldata_ack_r_d[2], Z1_TS_ADR_VLD, AB5_REG);


--AB4_REG is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_sr:trans64_sr_edge|REG
--operation mode is normal

AB4_REG = AMPP_FUNCTION(AB4_REG, Z1L77, Z1_trans64_sr_edge_rst, Z1_trans64_reg_R, pci_rstn, GLOBAL(pci_clk));


--Z1_lt_ldata_ack_r_d[4] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_ldata_ack_r_d[4]
--operation mode is normal

Z1_lt_ldata_ack_r_d[4] = AMPP_FUNCTION(AB4_REG, Z1_lt_ldata_ack_r_ena_lc2, Z1_lt_ldata_ack_r_d[1], Z1_lt_ldata_ack_r_d[2]);


--Z1_lt_ldata_ack_r_ena is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_ldata_ack_r_ena
--operation mode is normal

Z1_lt_ldata_ack_r_ena = AMPP_FUNCTION(Z1_lt_ldata_ack_r_prn3, Z1_lt_ldata_ack_r_ena_lc2, Z1_lw_lr_done, Z1_lt_ldata_ack_r_ena_lc1);


--W1_park is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|park
--operation mode is normal

W1_park = AMPP_FUNCTION(A1L234, BB1_cmd_reg[2], pci_gntn, pci_rstn, GLOBAL(pci_clk), W1_$00077);


--W1_MS_ENA_d_lc is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MS_ENA_d_lc
--operation mode is normal

W1_MS_ENA_d_lc = AMPP_FUNCTION(W1_MS_REQ, W1_park);


--W1_lm_ldata_ack_ena3 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|lm_ldata_ack_ena3
--operation mode is normal

W1_lm_ldata_ack_ena3 = AMPP_FUNCTION(W1_MS_ENA, W1_lm_ldata_ack_ena2, W1_$00119);


--Z1_LR_IDLE_lc1 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|LR_IDLE_lc1
--operation mode is normal

Z1_LR_IDLE_lc1 = AMPP_FUNCTION(Z1L241, AB5_REG);


--Z1_LW_IDLE_lc1 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|LW_IDLE_lc1
--operation mode is normal

Z1_LW_IDLE_lc1 = AMPP_FUNCTION(Z1L482, AB5_REG, Z1_cfg_cyc);


--U1_cben_IR_ce_address is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|cben_IR_ce_address
--operation mode is normal

U1_cben_IR_ce_address = AMPP_FUNCTION(W1_MS_ADR, W1_MS_ADR2, U1_trg_cben_IR_ce_A);


--Z1_lt_rdynR is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_rdynR
--operation mode is normal

Z1_lt_rdynR = AMPP_FUNCTION(dpm_dec_reg_LT_RDY_n_pci, pci_rstn, GLOBAL(pci_clk));


--Z1L41 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|$00161~0
--operation mode is normal

Z1L41 = AMPP_FUNCTION(A1L734, Z1_lt_rdynR);


--Z1_no_op_reg[2] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|no_op_reg[2]
--operation mode is normal

Z1_no_op_reg[2] = AMPP_FUNCTION(pci_rstn, GLOBAL(pci_clk));


--Z1L31 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|$00159~0
--operation mode is normal

Z1L31 = AMPP_FUNCTION(Z1_no_op_reg[2], A1L734);


--Z1_LW_WAIT is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|LW_WAIT
--operation mode is normal

Z1_LW_WAIT = AMPP_FUNCTION(Z1_LW_WAIT, dpm_dec_reg_LT_RDY_n_pci, pci_rstn, GLOBAL(pci_clk), Z1_$00211);


--Z1_lt_ack_R_r1_lc[7] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_ack_R_r1_lc[7]
--operation mode is normal

Z1_lt_ack_R_r1_lc[7] = AMPP_FUNCTION(Z1_lt_ack_R_r1_lc[6], Z1_LW_WAIT, Z1_lt_ack_R_r1_lc[4], Z1_rd_backoff);


--Z1_lt_rdynR_R is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_rdynR_R
--operation mode is normal

Z1_lt_rdynR_R = AMPP_FUNCTION(Z1_lt_rdynR, pci_rstn, GLOBAL(pci_clk));


--Z1_lt_ack_R_r1_lc[8] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_ack_R_r1_lc[8]
--operation mode is normal

Z1_lt_ack_R_r1_lc[8] = AMPP_FUNCTION(Z1_lt_rdynR, Z1_lt_ldata_ack_r, Z1_lt_rdynR_R, Z1_direct_xfr);


--Z1_LR_LXFR is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|LR_LXFR
--operation mode is normal

Z1_LR_LXFR = AMPP_FUNCTION(Z1_LR_LXFR, Z1_LR_LXFR_lc[5], Z1L941, pci_rstn, GLOBAL(pci_clk), Z1_$00225);


--Z1_lt_ack_R_r1_lc[9] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_ack_R_r1_lc[9]
--operation mode is normal

Z1_lt_ack_R_r1_lc[9] = AMPP_FUNCTION(Z1_LR_LXFR, Z1_rd_backoff);


--Z1_TS_IDLE_d_lc is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|TS_IDLE_d_lc
--operation mode is normal

Z1_TS_IDLE_d_lc = AMPP_FUNCTION(Z1_TS_TURN_AR, X1_serr_or, Z1_TS_ADR_VLD);


--Z1_TS_IDLE_d_lc1 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|TS_IDLE_d_lc1
--operation mode is normal

Z1_TS_IDLE_d_lc1 = AMPP_FUNCTION(Z1_TS_IDLE_NOT, Z1L311);


--BB1_bar_hit[0] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|bar_hit[0]
--operation mode is normal

BB1_bar_hit[0] = AMPP_FUNCTION(Z1_adr_phase_lc1, BB1_cyc_vld[0], GB41_aeb_out);


--Z1_bar_hit_rst is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|bar_hit_rst
--operation mode is normal

Z1_bar_hit_rst = AMPP_FUNCTION(X1_serr_or, Z1_TS_TURN_AR, Z1_TS_IDLE_NOT, Z1_adr_phase_lc1);


--dpm_ni2f_reg_end_marker1 is dpm_ni2f_reg_end_marker1
--operation mode is normal

dpm_ni2f_reg_end_marker1_lut_out = dpm_ni2f_reg_clk_sram_i & A1L94;
dpm_ni2f_reg_end_marker1 = DFFEA(dpm_ni2f_reg_end_marker1_lut_out, CLK50M, , , ix2009_lc, , );


--dpm_ni2f_reg_end_marker2 is dpm_ni2f_reg_end_marker2
--operation mode is normal

dpm_ni2f_reg_end_marker2_lut_out = dpm_ni2f_reg_clk_sram_i & dpm_ni2f_reg_end_marker1;
dpm_ni2f_reg_end_marker2 = DFFEA(dpm_ni2f_reg_end_marker2_lut_out, CLK50M, , , ix2009_lc, , );


--ix2065_lc is ix2065_lc
--operation mode is normal

ix2065_lc = dpm_ni2f_reg_end_marker1 & dpm_ni2f_reg_end_marker2;


--ix2009_lc is ix2009_lc
--operation mode is normal

ix2009_lc = dpm_ni2f_reg_sreset120 # dpm_ni2f_reg_clk_sram_i;


--ix2006_lc is ix2006_lc
--operation mode is normal

ix2006_lc = dpm_ni2f_reg_sm_2 # E8_q[10];


--ix2052 is ix2052
--operation mode is normal

ix2052 = !Z1L512 & !Z1L412 & U1_cben_ir_address[1] & U1_cben_ir_address[0];


--U1_mstr_trg_low_ad_out_sel is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|mstr_trg_low_ad_out_sel
--operation mode is normal

U1_mstr_trg_low_ad_out_sel = AMPP_FUNCTION(U1_trg_ad_sel, U1_mstr_ad_sel, U1_hi_low_sel, U1_mstr_hi_low_sel);


--Z1_WAIT_wait32 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|WAIT_wait32
--operation mode is normal

Z1_WAIT_wait32 = AMPP_FUNCTION(Z1_no_op_reg[11], A1L234, pci_rstn, GLOBAL(pci_clk), Z1L8);


--W1_WAIT_WAIT32 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|WAIT_WAIT32
--operation mode is normal

W1_WAIT_WAIT32 = AMPP_FUNCTION(W1_no_op_reg[3], pci_rstn, GLOBAL(pci_clk), W1L12);


--U1_mstr_trg_hr_dat_sel is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|mstr_trg_hr_dat_sel
--operation mode is normal

U1_mstr_trg_hr_dat_sel = AMPP_FUNCTION(W1_dac_cyc_strobe, Z1_WAIT_wait32, W1_WAIT_WAIT32, W1_MW_LAST);


--dpm_ni2f_reg_sram_qL_0 is dpm_ni2f_reg_sram_qL_0
--operation mode is normal

dpm_ni2f_reg_sram_qL_0_lut_out = SRAM_IO_0;
dpm_ni2f_reg_sram_qL_0 = DFFEA(dpm_ni2f_reg_sram_qL_0_lut_out, CLK50M, , , dpm_ni2f_reg_sm_8, , );


--A1L171 is ix1996_lc~0
--operation mode is normal

A1L171 = (Z1L922 # ix2071_lc # dpm_dec_reg_rdata_LED_0 & ix2078_lc) & CASCADE(A1L223);


--U1_low_data_out_HR[0] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_data_out_HR[0]
--operation mode is normal

U1_low_data_out_HR[0] = AMPP_FUNCTION(U1_low_data_out_hr_ena_d, U1_mstr_ad_sel, U1_low_data_out_HR_lc, A1L171, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_or[32] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_or[32]
--operation mode is normal

U1_high_ad_or[32] = AMPP_FUNCTION(V1_ad_ce[32], U1_mstr_trg_hi_ad, A1L171, U1_high_ad_out_lc[0], pci_rstn, GLOBAL(pci_clk));


--U1L793 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_not_cc[0]~576
--operation mode is normal

U1L793 = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_low_data_out_HR[0], U1_high_ad_or[32], U1_mstr_trg_low_ad_out_sel);


--U1L563 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_NOT[0]~544
--operation mode is normal

U1L563 = AMPP_FUNCTION(U1_trg_cfg_cyc_out, U1_trg_low_ad_out_sel, U1_trg_cfg_ad_out[0], U1L793);


--V1_ad_ce[40] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[40]
--operation mode is normal

V1_ad_ce[40] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--Z1_low_dword_discard is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|low_dword_discard
--operation mode is normal

Z1_low_dword_discard = AMPP_FUNCTION(Z1_LR_LXFR, Z1_lt_ldata_ack_r, Z1_$00100, pci_rstn, GLOBAL(pci_clk));


--W1_ad_oer_lc2d is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|ad_oer_lc2d
--operation mode is normal

W1_ad_oer_lc2d = AMPP_FUNCTION(W1_dac_cyc_strobe, W1_ad_oer_lc2c, W1_ad_oer_lc2b);


--W1_idle_reg is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|idle_reg
--operation mode is normal

W1_idle_reg = AMPP_FUNCTION(A1L234, pci_rstn, GLOBAL(pci_clk), W1_$00078);


--W1_ad_oer_lc2a is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|ad_oer_lc2a
--operation mode is normal

W1_ad_oer_lc2a = AMPP_FUNCTION(W1_idle_reg, W1_MS_REQ, W1_MS_IDLE_not);


--W1_mstr_abrt is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|mstr_abrt
--operation mode is normal

W1_mstr_abrt = AMPP_FUNCTION(W1_devsel_toR, pci_rstn, GLOBAL(pci_clk));


--W1_ad_oer_lc3 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|ad_oer_lc3
--operation mode is normal

W1_ad_oer_lc3 = AMPP_FUNCTION(W1_MS_DXFR, W1_wr_rdn, W1_mstr_abrt);


--dpm_ni2f_reg_sram_qL_1 is dpm_ni2f_reg_sram_qL_1
--operation mode is normal

dpm_ni2f_reg_sram_qL_1_lut_out = SRAM_IO_1;
dpm_ni2f_reg_sram_qL_1 = DFFEA(dpm_ni2f_reg_sram_qL_1_lut_out, CLK50M, , , dpm_ni2f_reg_sm_8, , );


--A1L071 is ix1995_lc~0
--operation mode is normal

A1L071 = (Z1L922 # ix2072_lc # dpm_dec_reg_rdata_LED_1 & ix2078_lc) & CASCADE(A1L123);


--U1_low_data_out_HR[1] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_data_out_HR[1]
--operation mode is normal

U1_low_data_out_HR[1] = AMPP_FUNCTION(U1_low_data_out_hr_ena_d, U1_mstr_ad_sel, U1_low_data_out_HR_lc, A1L071, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_or[33] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_or[33]
--operation mode is normal

U1_high_ad_or[33] = AMPP_FUNCTION(V1_ad_ce[33], U1_mstr_trg_hi_ad, A1L071, U1_high_ad_out_lc[1], pci_rstn, GLOBAL(pci_clk));


--U1L893 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_not_cc[1]~577
--operation mode is normal

U1L893 = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_low_data_out_HR[1], U1_high_ad_or[33], U1_mstr_trg_low_ad_out_sel);


--U1L663 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_NOT[1]~545
--operation mode is normal

U1L663 = AMPP_FUNCTION(U1_trg_cfg_cyc_out, U1_trg_low_ad_out_sel, U1_trg_cfg_ad_out[1], U1L893);


--dpm_ni2f_reg_sram_qL_2 is dpm_ni2f_reg_sram_qL_2
--operation mode is normal

dpm_ni2f_reg_sram_qL_2_lut_out = SRAM_IO_2;
dpm_ni2f_reg_sram_qL_2 = DFFEA(dpm_ni2f_reg_sram_qL_2_lut_out, CLK50M, , , dpm_ni2f_reg_sm_8, , );


--A1L961 is ix1994_lc~0
--operation mode is normal

A1L961 = (Z1L922 # ix2073_lc # dpm_dec_reg_rdata_LED_2 & ix2078_lc) & CASCADE(A1L023);


--U1_low_data_out_HR[2] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_data_out_HR[2]
--operation mode is normal

U1_low_data_out_HR[2] = AMPP_FUNCTION(U1_low_data_out_hr_ena_d, U1_mstr_ad_sel, U1_low_data_out_HR_lc, A1L961, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_or[34] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_or[34]
--operation mode is normal

U1_high_ad_or[34] = AMPP_FUNCTION(V1_ad_ce[34], U1_mstr_trg_hi_ad, A1L961, U1_high_ad_out_lc[2], pci_rstn, GLOBAL(pci_clk));


--U1L993 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_not_cc[2]~578
--operation mode is normal

U1L993 = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_low_data_out_HR[2], U1_high_ad_or[34], U1_mstr_trg_low_ad_out_sel);


--U1L763 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_NOT[2]~546
--operation mode is normal

U1L763 = AMPP_FUNCTION(U1_trg_cfg_cyc_out, U1_trg_low_ad_out_sel, U1_trg_cfg_ad_out[2], U1L993);


--dpm_ni2f_reg_sram_qL_3 is dpm_ni2f_reg_sram_qL_3
--operation mode is normal

dpm_ni2f_reg_sram_qL_3_lut_out = SRAM_IO_3;
dpm_ni2f_reg_sram_qL_3 = DFFEA(dpm_ni2f_reg_sram_qL_3_lut_out, CLK50M, , , dpm_ni2f_reg_sm_8, , );


--A1L861 is ix1993_lc~0
--operation mode is normal

A1L861 = (Z1L922 # ix2074_lc # dpm_dec_reg_rdata_LED_3 & ix2078_lc) & CASCADE(A1L913);


--U1_low_data_out_HR[3] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_data_out_HR[3]
--operation mode is normal

U1_low_data_out_HR[3] = AMPP_FUNCTION(U1_low_data_out_hr_ena_d, U1_mstr_ad_sel, U1_low_data_out_HR_lc, A1L861, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_or[35] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_or[35]
--operation mode is normal

U1_high_ad_or[35] = AMPP_FUNCTION(V1_ad_ce[35], U1_mstr_trg_hi_ad, A1L861, U1_high_ad_out_lc[3], pci_rstn, GLOBAL(pci_clk));


--U1L004 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_not_cc[3]~579
--operation mode is normal

U1L004 = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_low_data_out_HR[3], U1_high_ad_or[35], U1_mstr_trg_low_ad_out_sel);


--U1L863 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_NOT[3]~547
--operation mode is normal

U1L863 = AMPP_FUNCTION(U1_trg_cfg_cyc_out, U1_trg_low_ad_out_sel, U1_trg_cfg_ad_out[3], U1L004);


--dpm_ni2f_reg_sram_qL_4 is dpm_ni2f_reg_sram_qL_4
--operation mode is normal

dpm_ni2f_reg_sram_qL_4_lut_out = SRAM_IO_4;
dpm_ni2f_reg_sram_qL_4 = DFFEA(dpm_ni2f_reg_sram_qL_4_lut_out, CLK50M, , , dpm_ni2f_reg_sm_8, , );


--A1L761 is ix1992_lc~0
--operation mode is normal

A1L761 = (Z1L922 # ix2075_lc # dpm_dec_reg_rdata_LED_4 & ix2078_lc) & CASCADE(A1L813);


--U1_low_data_out_HR[4] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_data_out_HR[4]
--operation mode is normal

U1_low_data_out_HR[4] = AMPP_FUNCTION(U1_low_data_out_hr_ena_d, U1_mstr_ad_sel, U1_low_data_out_HR_lc, A1L761, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_or[36] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_or[36]
--operation mode is normal

U1_high_ad_or[36] = AMPP_FUNCTION(V1_ad_ce[36], U1_mstr_trg_hi_ad, A1L761, U1_high_ad_out_lc[4], pci_rstn, GLOBAL(pci_clk));


--U1L104 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_not_cc[4]~580
--operation mode is normal

U1L104 = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_low_data_out_HR[4], U1_high_ad_or[36], U1_mstr_trg_low_ad_out_sel);


--U1L963 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_NOT[4]~548
--operation mode is normal

U1L963 = AMPP_FUNCTION(U1_trg_cfg_cyc_out, U1_trg_low_ad_out_sel, U1_trg_cfg_ad_out[4], U1L104);


--dpm_ni2f_reg_sram_qL_5 is dpm_ni2f_reg_sram_qL_5
--operation mode is normal

dpm_ni2f_reg_sram_qL_5_lut_out = SRAM_IO_5;
dpm_ni2f_reg_sram_qL_5 = DFFEA(dpm_ni2f_reg_sram_qL_5_lut_out, CLK50M, , , dpm_ni2f_reg_sm_8, , );


--A1L661 is ix1991_lc~0
--operation mode is normal

A1L661 = (Z1L922 # ix2076_lc # dpm_dec_reg_rdata_LED_5 & ix2078_lc) & CASCADE(A1L713);


--U1_low_data_out_HR[5] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_data_out_HR[5]
--operation mode is normal

U1_low_data_out_HR[5] = AMPP_FUNCTION(U1_low_data_out_hr_ena_d, U1_mstr_ad_sel, U1_low_data_out_HR_lc, A1L661, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_or[37] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_or[37]
--operation mode is normal

U1_high_ad_or[37] = AMPP_FUNCTION(V1_ad_ce[37], U1_mstr_trg_hi_ad, A1L661, U1_high_ad_out_lc[5], pci_rstn, GLOBAL(pci_clk));


--U1L204 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_not_cc[5]~581
--operation mode is normal

U1L204 = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_low_data_out_HR[5], U1_high_ad_or[37], U1_mstr_trg_low_ad_out_sel);


--U1L073 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_NOT[5]~549
--operation mode is normal

U1L073 = AMPP_FUNCTION(U1_trg_cfg_cyc_out, U1_trg_low_ad_out_sel, U1_trg_cfg_ad_out[5], U1L204);


--dpm_ni2f_reg_sram_qL_6 is dpm_ni2f_reg_sram_qL_6
--operation mode is normal

dpm_ni2f_reg_sram_qL_6_lut_out = SRAM_IO_6;
dpm_ni2f_reg_sram_qL_6 = DFFEA(dpm_ni2f_reg_sram_qL_6_lut_out, CLK50M, , , dpm_ni2f_reg_sm_8, , );


--A1L561 is ix1990_lc~0
--operation mode is normal

A1L561 = (Z1L922 # ix2077_lc # dpm_dec_reg_rdata_LED_6 & ix2078_lc) & CASCADE(A1L613);


--U1_low_data_out_HR[6] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_data_out_HR[6]
--operation mode is normal

U1_low_data_out_HR[6] = AMPP_FUNCTION(U1_low_data_out_hr_ena_d, U1_mstr_ad_sel, U1_low_data_out_HR_lc, A1L561, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_or[38] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_or[38]
--operation mode is normal

U1_high_ad_or[38] = AMPP_FUNCTION(V1_ad_ce[38], U1_mstr_trg_hi_ad, A1L561, U1_high_ad_out_lc[6], pci_rstn, GLOBAL(pci_clk));


--U1L304 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_not_cc[6]~582
--operation mode is normal

U1L304 = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_low_data_out_HR[6], U1_high_ad_or[38], U1_mstr_trg_low_ad_out_sel);


--U1L173 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_NOT[6]~550
--operation mode is normal

U1L173 = AMPP_FUNCTION(U1_trg_cfg_cyc_out, U1_trg_low_ad_out_sel, U1_trg_cfg_ad_out[6], U1L304);


--dpm_ni2f_reg_sram_qL_7 is dpm_ni2f_reg_sram_qL_7
--operation mode is normal

dpm_ni2f_reg_sram_qL_7_lut_out = SRAM_IO_7;
dpm_ni2f_reg_sram_qL_7 = DFFEA(dpm_ni2f_reg_sram_qL_7_lut_out, CLK50M, , , dpm_ni2f_reg_sm_8, , );


--A1L461 is ix1989_lc~0
--operation mode is normal

A1L461 = (Z1L922 # ix2079_lc # dpm_dec_reg_rdata_LED_7 & ix2078_lc) & CASCADE(A1L513);


--U1_low_data_out_HR[7] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_data_out_HR[7]
--operation mode is normal

U1_low_data_out_HR[7] = AMPP_FUNCTION(U1_low_data_out_hr_ena_d, U1_mstr_ad_sel, U1_low_data_out_HR_lc, A1L461, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_or[39] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_or[39]
--operation mode is normal

U1_high_ad_or[39] = AMPP_FUNCTION(V1_ad_ce[39], U1_mstr_trg_hi_ad, A1L461, U1_high_ad_out_lc[7], pci_rstn, GLOBAL(pci_clk));


--U1L404 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_not_cc[7]~583
--operation mode is normal

U1L404 = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_low_data_out_HR[7], U1_high_ad_or[39], U1_mstr_trg_low_ad_out_sel);


--U1L273 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_NOT[7]~551
--operation mode is normal

U1L273 = AMPP_FUNCTION(U1_trg_cfg_cyc_out, U1_trg_low_ad_out_sel, U1_trg_cfg_ad_out[7], U1L404);


--dpm_ni2f_reg_sram_qL_8 is dpm_ni2f_reg_sram_qL_8
--operation mode is normal

dpm_ni2f_reg_sram_qL_8_lut_out = SRAM_IO_8;
dpm_ni2f_reg_sram_qL_8 = DFFEA(dpm_ni2f_reg_sram_qL_8_lut_out, CLK50M, , , dpm_ni2f_reg_sm_8, , );


--U1_low_data_out_HR[8] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_data_out_HR[8]
--operation mode is normal

U1_low_data_out_HR[8] = AMPP_FUNCTION(U1_low_data_out_hr_ena_d, U1_mstr_ad_sel, U1_low_data_out_HR_lc, A1L361, pci_rstn, GLOBAL(pci_clk));


--U1L504 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_not_cc[8]~584
--operation mode is normal

U1L504 = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_low_data_out_HR[8], U1_high_ad_or[40], U1_mstr_trg_low_ad_out_sel);


--U1L373 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_NOT[8]~552
--operation mode is normal

U1L373 = AMPP_FUNCTION(U1_trg_cfg_cyc_out, U1_trg_low_ad_out_sel, U1_trg_cfg_ad_out[8], U1L504);


--dpm_ni2f_reg_sram_qL_9 is dpm_ni2f_reg_sram_qL_9
--operation mode is normal

dpm_ni2f_reg_sram_qL_9_lut_out = SRAM_IO_9;
dpm_ni2f_reg_sram_qL_9 = DFFEA(dpm_ni2f_reg_sram_qL_9_lut_out, CLK50M, , , dpm_ni2f_reg_sm_8, , );


--U1_low_data_out_HR[9] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_data_out_HR[9]
--operation mode is normal

U1_low_data_out_HR[9] = AMPP_FUNCTION(U1_low_data_out_hr_ena_d, U1_mstr_ad_sel, U1_low_data_out_HR_lc, A1L261, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_or[41] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_or[41]
--operation mode is normal

U1_high_ad_or[41] = AMPP_FUNCTION(V1_ad_ce[41], U1_mstr_trg_hi_ad, A1L261, U1_high_ad_out_lc[9], pci_rstn, GLOBAL(pci_clk));


--U1L604 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_not_cc[9]~585
--operation mode is normal

U1L604 = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_low_data_out_HR[9], U1_high_ad_or[41], U1_mstr_trg_low_ad_out_sel);


--U1L473 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_NOT[9]~553
--operation mode is normal

U1L473 = AMPP_FUNCTION(U1_trg_cfg_cyc_out, U1_trg_low_ad_out_sel, U1_trg_cfg_ad_out[9], U1L604);


--ix2037 is ix2037
--operation mode is normal

ix2037 = Z1L922 # !E7_q[10] # !Z1L412 # !Z1L512;


--dpm_ni2f_reg_sram_qL_10 is dpm_ni2f_reg_sram_qL_10
--operation mode is normal

dpm_ni2f_reg_sram_qL_10_lut_out = SRAM_IO_10;
dpm_ni2f_reg_sram_qL_10 = DFFEA(dpm_ni2f_reg_sram_qL_10_lut_out, CLK50M, , , dpm_ni2f_reg_sm_8, , );


--U1_low_data_out_HR[10] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_data_out_HR[10]
--operation mode is normal

U1_low_data_out_HR[10] = AMPP_FUNCTION(U1_low_data_out_hr_ena_d, U1_low_data_out_HR_lc, U1_mstr_ad_sel, A1L161, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_or[42] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_or[42]
--operation mode is normal

U1_high_ad_or[42] = AMPP_FUNCTION(V1_ad_ce[42], U1_mstr_trg_hi_ad, U1_high_ad_out_lc[10], A1L161, pci_rstn, GLOBAL(pci_clk));


--U1L704 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_not_cc[10]~586
--operation mode is normal

U1L704 = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_low_data_out_HR[10], U1_high_ad_or[42], U1_mstr_trg_low_ad_out_sel);


--U1L573 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_NOT[10]~554
--operation mode is normal

U1L573 = AMPP_FUNCTION(U1_trg_cfg_cyc_out, U1_trg_low_ad_out_sel, U1_trg_cfg_ad_out[10], U1L704);


--ix2036 is ix2036
--operation mode is normal

ix2036 = Z1L922 # !E7_q[11] # !Z1L412 # !Z1L512;


--dpm_ni2f_reg_sram_qL_11 is dpm_ni2f_reg_sram_qL_11
--operation mode is normal

dpm_ni2f_reg_sram_qL_11_lut_out = SRAM_IO_11;
dpm_ni2f_reg_sram_qL_11 = DFFEA(dpm_ni2f_reg_sram_qL_11_lut_out, CLK50M, , , dpm_ni2f_reg_sm_8, , );


--U1_low_data_out_HR[11] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_data_out_HR[11]
--operation mode is normal

U1_low_data_out_HR[11] = AMPP_FUNCTION(U1_low_data_out_hr_ena_d, U1_low_data_out_HR_lc, U1_mstr_ad_sel, A1L061, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_or[43] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_or[43]
--operation mode is normal

U1_high_ad_or[43] = AMPP_FUNCTION(V1_ad_ce[43], U1_mstr_trg_hi_ad, U1_high_ad_out_lc[11], A1L061, pci_rstn, GLOBAL(pci_clk));


--U1L804 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_not_cc[11]~587
--operation mode is normal

U1L804 = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_low_data_out_HR[11], U1_high_ad_or[43], U1_mstr_trg_low_ad_out_sel);


--U1L673 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_NOT[11]~555
--operation mode is normal

U1L673 = AMPP_FUNCTION(U1_trg_cfg_cyc_out, U1_trg_low_ad_out_sel, U1_trg_cfg_ad_out[11], U1L804);


--ix2035 is ix2035
--operation mode is normal

ix2035 = Z1L922 # !E7_q[12] # !Z1L412 # !Z1L512;


--dpm_ni2f_reg_sram_qL_12 is dpm_ni2f_reg_sram_qL_12
--operation mode is normal

dpm_ni2f_reg_sram_qL_12_lut_out = SRAM_IO_12;
dpm_ni2f_reg_sram_qL_12 = DFFEA(dpm_ni2f_reg_sram_qL_12_lut_out, CLK50M, , , dpm_ni2f_reg_sm_8, , );


--U1_low_data_out_HR[12] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_data_out_HR[12]
--operation mode is normal

U1_low_data_out_HR[12] = AMPP_FUNCTION(U1_low_data_out_hr_ena_d, U1_low_data_out_HR_lc, U1_mstr_ad_sel, A1L951, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_or[44] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_or[44]
--operation mode is normal

U1_high_ad_or[44] = AMPP_FUNCTION(V1_ad_ce[44], U1_mstr_trg_hi_ad, U1_high_ad_out_lc[12], A1L951, pci_rstn, GLOBAL(pci_clk));


--U1L904 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_not_cc[12]~588
--operation mode is normal

U1L904 = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_low_data_out_HR[12], U1_high_ad_or[44], U1_mstr_trg_low_ad_out_sel);


--U1L773 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_NOT[12]~556
--operation mode is normal

U1L773 = AMPP_FUNCTION(U1_trg_cfg_cyc_out, U1_trg_low_ad_out_sel, U1_trg_cfg_ad_out[12], U1L904);


--ix2034 is ix2034
--operation mode is normal

ix2034 = Z1L922 # !E7_q[13] # !Z1L412 # !Z1L512;


--dpm_ni2f_reg_sram_qL_13 is dpm_ni2f_reg_sram_qL_13
--operation mode is normal

dpm_ni2f_reg_sram_qL_13_lut_out = SRAM_IO_13;
dpm_ni2f_reg_sram_qL_13 = DFFEA(dpm_ni2f_reg_sram_qL_13_lut_out, CLK50M, , , dpm_ni2f_reg_sm_8, , );


--U1_low_data_out_HR[13] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_data_out_HR[13]
--operation mode is normal

U1_low_data_out_HR[13] = AMPP_FUNCTION(U1_low_data_out_hr_ena_d, U1_low_data_out_HR_lc, U1_mstr_ad_sel, A1L851, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_or[45] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_or[45]
--operation mode is normal

U1_high_ad_or[45] = AMPP_FUNCTION(V1_ad_ce[45], U1_mstr_trg_hi_ad, U1_high_ad_out_lc[13], A1L851, pci_rstn, GLOBAL(pci_clk));


--U1L014 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_not_cc[13]~589
--operation mode is normal

U1L014 = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_low_data_out_HR[13], U1_high_ad_or[45], U1_mstr_trg_low_ad_out_sel);


--U1L873 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_NOT[13]~557
--operation mode is normal

U1L873 = AMPP_FUNCTION(U1_trg_cfg_cyc_out, U1_trg_low_ad_out_sel, U1_trg_cfg_ad_out[13], U1L014);


--ix2033 is ix2033
--operation mode is normal

ix2033 = Z1L922 # !E7_q[14] # !Z1L412 # !Z1L512;


--dpm_ni2f_reg_sram_qL_14 is dpm_ni2f_reg_sram_qL_14
--operation mode is normal

dpm_ni2f_reg_sram_qL_14_lut_out = SRAM_IO_14;
dpm_ni2f_reg_sram_qL_14 = DFFEA(dpm_ni2f_reg_sram_qL_14_lut_out, CLK50M, , , dpm_ni2f_reg_sm_8, , );


--U1_low_data_out_HR[14] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_data_out_HR[14]
--operation mode is normal

U1_low_data_out_HR[14] = AMPP_FUNCTION(U1_low_data_out_hr_ena_d, U1_low_data_out_HR_lc, U1_mstr_ad_sel, A1L751, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_or[46] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_or[46]
--operation mode is normal

U1_high_ad_or[46] = AMPP_FUNCTION(V1_ad_ce[46], U1_mstr_trg_hi_ad, U1_high_ad_out_lc[14], A1L751, pci_rstn, GLOBAL(pci_clk));


--U1L114 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_not_cc[14]~590
--operation mode is normal

U1L114 = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_low_data_out_HR[14], U1_high_ad_or[46], U1_mstr_trg_low_ad_out_sel);


--U1L973 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_NOT[14]~558
--operation mode is normal

U1L973 = AMPP_FUNCTION(U1_trg_cfg_cyc_out, U1_trg_low_ad_out_sel, U1_trg_cfg_ad_out[14], U1L114);


--ix2032 is ix2032
--operation mode is normal

ix2032 = Z1L922 # !E7_q[15] # !Z1L412 # !Z1L512;


--dpm_ni2f_reg_sram_qL_15 is dpm_ni2f_reg_sram_qL_15
--operation mode is normal

dpm_ni2f_reg_sram_qL_15_lut_out = SRAM_IO_15;
dpm_ni2f_reg_sram_qL_15 = DFFEA(dpm_ni2f_reg_sram_qL_15_lut_out, CLK50M, , , dpm_ni2f_reg_sm_8, , );


--U1_low_data_out_HR[15] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_data_out_HR[15]
--operation mode is normal

U1_low_data_out_HR[15] = AMPP_FUNCTION(U1_low_data_out_hr_ena_d, U1_low_data_out_HR_lc, U1_mstr_ad_sel, A1L651, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_or[47] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_or[47]
--operation mode is normal

U1_high_ad_or[47] = AMPP_FUNCTION(V1_ad_ce[47], U1_mstr_trg_hi_ad, U1_high_ad_out_lc[15], A1L651, pci_rstn, GLOBAL(pci_clk));


--U1L214 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_not_cc[15]~591
--operation mode is normal

U1L214 = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_low_data_out_HR[15], U1_high_ad_or[47], U1_mstr_trg_low_ad_out_sel);


--U1L083 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_NOT[15]~559
--operation mode is normal

U1L083 = AMPP_FUNCTION(U1_trg_cfg_cyc_out, U1_trg_low_ad_out_sel, U1_trg_cfg_ad_out[15], U1L214);


--ix2031 is ix2031
--operation mode is normal

ix2031 = Z1L922 # !E7_q[16] # !Z1L412 # !Z1L512;


--dpm_ni2f_reg_sram_qH_0 is dpm_ni2f_reg_sram_qH_0
--operation mode is normal

dpm_ni2f_reg_sram_qH_0_lut_out = SRAM_IO_0;
dpm_ni2f_reg_sram_qH_0 = DFFEA(dpm_ni2f_reg_sram_qH_0_lut_out, CLK50M, , , dpm_ni2f_reg_sm_10, , );


--U1_low_data_out_HR[16] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_data_out_HR[16]
--operation mode is normal

U1_low_data_out_HR[16] = AMPP_FUNCTION(U1_low_data_out_hr_ena_d, U1_low_data_out_HR_lc, U1_mstr_ad_sel, A1L551, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_or[48] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_or[48]
--operation mode is normal

U1_high_ad_or[48] = AMPP_FUNCTION(V1_ad_ce[48], U1_mstr_trg_hi_ad, U1_high_ad_out_lc[16], A1L551, pci_rstn, GLOBAL(pci_clk));


--U1L314 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_not_cc[16]~592
--operation mode is normal

U1L314 = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_low_data_out_HR[16], U1_high_ad_or[48], U1_mstr_trg_low_ad_out_sel);


--U1L183 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_NOT[16]~560
--operation mode is normal

U1L183 = AMPP_FUNCTION(U1_trg_cfg_cyc_out, U1_trg_low_ad_out_sel, U1_trg_cfg_ad_out[16], U1L314);


--ix2030 is ix2030
--operation mode is normal

ix2030 = Z1L922 # !E7_q[17] # !Z1L412 # !Z1L512;


--dpm_ni2f_reg_sram_qH_1 is dpm_ni2f_reg_sram_qH_1
--operation mode is normal

dpm_ni2f_reg_sram_qH_1_lut_out = SRAM_IO_1;
dpm_ni2f_reg_sram_qH_1 = DFFEA(dpm_ni2f_reg_sram_qH_1_lut_out, CLK50M, , , dpm_ni2f_reg_sm_10, , );


--U1_low_data_out_HR[17] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_data_out_HR[17]
--operation mode is normal

U1_low_data_out_HR[17] = AMPP_FUNCTION(U1_low_data_out_hr_ena_d, U1_low_data_out_HR_lc, U1_mstr_ad_sel, A1L451, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_or[49] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_or[49]
--operation mode is normal

U1_high_ad_or[49] = AMPP_FUNCTION(V1_ad_ce[49], U1_mstr_trg_hi_ad, U1_high_ad_out_lc[17], A1L451, pci_rstn, GLOBAL(pci_clk));


--U1L414 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_not_cc[17]~593
--operation mode is normal

U1L414 = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_low_data_out_HR[17], U1_high_ad_or[49], U1_mstr_trg_low_ad_out_sel);


--U1L283 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_NOT[17]~561
--operation mode is normal

U1L283 = AMPP_FUNCTION(U1_trg_cfg_cyc_out, U1_trg_low_ad_out_sel, U1_trg_cfg_ad_out[17], U1L414);


--ix2029 is ix2029
--operation mode is normal

ix2029 = Z1L922 # !E6_q[0] # !Z1L412 # !Z1L512;


--dpm_ni2f_reg_sram_qH_2 is dpm_ni2f_reg_sram_qH_2
--operation mode is normal

dpm_ni2f_reg_sram_qH_2_lut_out = SRAM_IO_2;
dpm_ni2f_reg_sram_qH_2 = DFFEA(dpm_ni2f_reg_sram_qH_2_lut_out, CLK50M, , , dpm_ni2f_reg_sm_10, , );


--U1_low_data_out_HR[18] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_data_out_HR[18]
--operation mode is normal

U1_low_data_out_HR[18] = AMPP_FUNCTION(U1_low_data_out_hr_ena_d, U1_low_data_out_HR_lc, U1_mstr_ad_sel, A1L351, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_or[50] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_or[50]
--operation mode is normal

U1_high_ad_or[50] = AMPP_FUNCTION(V1_ad_ce[50], U1_mstr_trg_hi_ad, U1_high_ad_out_lc[18], A1L351, pci_rstn, GLOBAL(pci_clk));


--U1L514 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_not_cc[18]~594
--operation mode is normal

U1L514 = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_low_data_out_HR[18], U1_high_ad_or[50], U1_mstr_trg_low_ad_out_sel);


--U1L383 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_NOT[18]~562
--operation mode is normal

U1L383 = AMPP_FUNCTION(U1_trg_cfg_cyc_out, U1_trg_low_ad_out_sel, U1_trg_cfg_ad_out[18], U1L514);


--ix2028 is ix2028
--operation mode is normal

ix2028 = Z1L922 # !E6_q[1] # !Z1L412 # !Z1L512;


--dpm_ni2f_reg_sram_qH_3 is dpm_ni2f_reg_sram_qH_3
--operation mode is normal

dpm_ni2f_reg_sram_qH_3_lut_out = SRAM_IO_3;
dpm_ni2f_reg_sram_qH_3 = DFFEA(dpm_ni2f_reg_sram_qH_3_lut_out, CLK50M, , , dpm_ni2f_reg_sm_10, , );


--U1_low_data_out_HR[19] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_data_out_HR[19]
--operation mode is normal

U1_low_data_out_HR[19] = AMPP_FUNCTION(U1_low_data_out_hr_ena_d, U1_low_data_out_HR_lc, U1_mstr_ad_sel, A1L251, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_or[51] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_or[51]
--operation mode is normal

U1_high_ad_or[51] = AMPP_FUNCTION(V1_ad_ce[51], U1_mstr_trg_hi_ad, U1_high_ad_out_lc[19], A1L251, pci_rstn, GLOBAL(pci_clk));


--U1L614 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_not_cc[19]~595
--operation mode is normal

U1L614 = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_low_data_out_HR[19], U1_high_ad_or[51], U1_mstr_trg_low_ad_out_sel);


--U1L483 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_NOT[19]~563
--operation mode is normal

U1L483 = AMPP_FUNCTION(U1_trg_cfg_cyc_out, U1_trg_low_ad_out_sel, U1_trg_cfg_ad_out[19], U1L614);


--ix2027 is ix2027
--operation mode is normal

ix2027 = Z1L922 # !E6_q[2] # !Z1L412 # !Z1L512;


--dpm_ni2f_reg_sram_qH_4 is dpm_ni2f_reg_sram_qH_4
--operation mode is normal

dpm_ni2f_reg_sram_qH_4_lut_out = SRAM_IO_4;
dpm_ni2f_reg_sram_qH_4 = DFFEA(dpm_ni2f_reg_sram_qH_4_lut_out, CLK50M, , , dpm_ni2f_reg_sm_10, , );


--U1_low_data_out_HR[20] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_data_out_HR[20]
--operation mode is normal

U1_low_data_out_HR[20] = AMPP_FUNCTION(U1_low_data_out_hr_ena_d, U1_low_data_out_HR_lc, U1_mstr_ad_sel, A1L151, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_or[52] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_or[52]
--operation mode is normal

U1_high_ad_or[52] = AMPP_FUNCTION(V1_ad_ce[52], U1_mstr_trg_hi_ad, U1_high_ad_out_lc[20], A1L151, pci_rstn, GLOBAL(pci_clk));


--U1L714 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_not_cc[20]~596
--operation mode is normal

U1L714 = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_low_data_out_HR[20], U1_high_ad_or[52], U1_mstr_trg_low_ad_out_sel);


--U1L583 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_NOT[20]~564
--operation mode is normal

U1L583 = AMPP_FUNCTION(U1_trg_cfg_cyc_out, U1_trg_low_ad_out_sel, U1_trg_cfg_ad_out[20], U1L714);


--ix2026 is ix2026
--operation mode is normal

ix2026 = Z1L922 # !E6_q[3] # !Z1L412 # !Z1L512;


--dpm_ni2f_reg_sram_qH_5 is dpm_ni2f_reg_sram_qH_5
--operation mode is normal

dpm_ni2f_reg_sram_qH_5_lut_out = SRAM_IO_5;
dpm_ni2f_reg_sram_qH_5 = DFFEA(dpm_ni2f_reg_sram_qH_5_lut_out, CLK50M, , , dpm_ni2f_reg_sm_10, , );


--U1_low_data_out_HR[21] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_data_out_HR[21]
--operation mode is normal

U1_low_data_out_HR[21] = AMPP_FUNCTION(U1_low_data_out_hr_ena_d, U1_low_data_out_HR_lc, U1_mstr_ad_sel, A1L051, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_or[53] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_or[53]
--operation mode is normal

U1_high_ad_or[53] = AMPP_FUNCTION(V1_ad_ce[53], U1_mstr_trg_hi_ad, U1_high_ad_out_lc[21], A1L051, pci_rstn, GLOBAL(pci_clk));


--U1L814 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_not_cc[21]~597
--operation mode is normal

U1L814 = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_low_data_out_HR[21], U1_high_ad_or[53], U1_mstr_trg_low_ad_out_sel);


--U1L683 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_NOT[21]~565
--operation mode is normal

U1L683 = AMPP_FUNCTION(U1_trg_cfg_cyc_out, U1_trg_low_ad_out_sel, U1_trg_cfg_ad_out[21], U1L814);


--ix2025 is ix2025
--operation mode is normal

ix2025 = Z1L922 # !E6_q[4] # !Z1L412 # !Z1L512;


--dpm_ni2f_reg_sram_qH_6 is dpm_ni2f_reg_sram_qH_6
--operation mode is normal

dpm_ni2f_reg_sram_qH_6_lut_out = SRAM_IO_6;
dpm_ni2f_reg_sram_qH_6 = DFFEA(dpm_ni2f_reg_sram_qH_6_lut_out, CLK50M, , , dpm_ni2f_reg_sm_10, , );


--U1_low_data_out_HR[22] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_data_out_HR[22]
--operation mode is normal

U1_low_data_out_HR[22] = AMPP_FUNCTION(U1_low_data_out_hr_ena_d, U1_low_data_out_HR_lc, U1_mstr_ad_sel, A1L941, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_or[54] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_or[54]
--operation mode is normal

U1_high_ad_or[54] = AMPP_FUNCTION(V1_ad_ce[54], U1_mstr_trg_hi_ad, U1_high_ad_out_lc[22], A1L941, pci_rstn, GLOBAL(pci_clk));


--U1L914 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_not_cc[22]~598
--operation mode is normal

U1L914 = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_low_data_out_HR[22], U1_high_ad_or[54], U1_mstr_trg_low_ad_out_sel);


--U1L783 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_NOT[22]~566
--operation mode is normal

U1L783 = AMPP_FUNCTION(U1_trg_cfg_cyc_out, U1_trg_low_ad_out_sel, U1_trg_cfg_ad_out[22], U1L914);


--ix2024 is ix2024
--operation mode is normal

ix2024 = Z1L922 # !E6_q[5] # !Z1L412 # !Z1L512;


--dpm_ni2f_reg_sram_qH_7 is dpm_ni2f_reg_sram_qH_7
--operation mode is normal

dpm_ni2f_reg_sram_qH_7_lut_out = SRAM_IO_7;
dpm_ni2f_reg_sram_qH_7 = DFFEA(dpm_ni2f_reg_sram_qH_7_lut_out, CLK50M, , , dpm_ni2f_reg_sm_10, , );


--U1_low_data_out_HR[23] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_data_out_HR[23]
--operation mode is normal

U1_low_data_out_HR[23] = AMPP_FUNCTION(U1_low_data_out_hr_ena_d, U1_low_data_out_HR_lc, U1_mstr_ad_sel, A1L841, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_or[55] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_or[55]
--operation mode is normal

U1_high_ad_or[55] = AMPP_FUNCTION(V1_ad_ce[55], U1_mstr_trg_hi_ad, U1_high_ad_out_lc[23], A1L841, pci_rstn, GLOBAL(pci_clk));


--U1L024 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_not_cc[23]~599
--operation mode is normal

U1L024 = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_low_data_out_HR[23], U1_high_ad_or[55], U1_mstr_trg_low_ad_out_sel);


--U1L883 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_NOT[23]~567
--operation mode is normal

U1L883 = AMPP_FUNCTION(U1_trg_cfg_cyc_out, U1_trg_low_ad_out_sel, U1_trg_cfg_ad_out[23], U1L024);


--dpm_ni2f_reg_sram_qH_8 is dpm_ni2f_reg_sram_qH_8
--operation mode is normal

dpm_ni2f_reg_sram_qH_8_lut_out = SRAM_IO_8;
dpm_ni2f_reg_sram_qH_8 = DFFEA(dpm_ni2f_reg_sram_qH_8_lut_out, CLK50M, , , dpm_ni2f_reg_sm_10, , );


--U1_low_data_out_HR[24] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_data_out_HR[24]
--operation mode is normal

U1_low_data_out_HR[24] = AMPP_FUNCTION(U1_low_data_out_hr_ena_d, U1_low_data_out_HR_lc, U1_mstr_ad_sel, A1L741, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_or[56] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_or[56]
--operation mode is normal

U1_high_ad_or[56] = AMPP_FUNCTION(V1_ad_ce[56], U1_mstr_trg_hi_ad, U1_high_ad_out_lc[24], A1L741, pci_rstn, GLOBAL(pci_clk));


--U1L124 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_not_cc[24]~600
--operation mode is normal

U1L124 = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_low_data_out_HR[24], U1_high_ad_or[56], U1_mstr_trg_low_ad_out_sel);


--U1L983 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_NOT[24]~568
--operation mode is normal

U1L983 = AMPP_FUNCTION(U1_trg_cfg_cyc_out, U1_trg_low_ad_out_sel, U1_trg_cfg_ad_out[24], U1L124);


--dpm_ni2f_reg_sram_qH_9 is dpm_ni2f_reg_sram_qH_9
--operation mode is normal

dpm_ni2f_reg_sram_qH_9_lut_out = SRAM_IO_9;
dpm_ni2f_reg_sram_qH_9 = DFFEA(dpm_ni2f_reg_sram_qH_9_lut_out, CLK50M, , , dpm_ni2f_reg_sm_10, , );


--A1L641 is ix1971_lc~0
--operation mode is normal

A1L641 = (Z1L922 # !ix2085_lc # !ix2082_lc # !ix2021_lc) & CASCADE(A1L303);


--U1_low_data_out_HR[25] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_data_out_HR[25]
--operation mode is normal

U1_low_data_out_HR[25] = AMPP_FUNCTION(U1_low_data_out_hr_ena_d, U1_low_data_out_HR_lc, U1_mstr_ad_sel, A1L641, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_or[57] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_or[57]
--operation mode is normal

U1_high_ad_or[57] = AMPP_FUNCTION(V1_ad_ce[57], U1_mstr_trg_hi_ad, U1_high_ad_out_lc[25], A1L641, pci_rstn, GLOBAL(pci_clk));


--U1L224 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_not_cc[25]~601
--operation mode is normal

U1L224 = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_low_data_out_HR[25], U1_high_ad_or[57], U1_mstr_trg_low_ad_out_sel);


--U1L093 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_NOT[25]~569
--operation mode is normal

U1L093 = AMPP_FUNCTION(U1_trg_cfg_cyc_out, U1_trg_low_ad_out_sel, U1_trg_cfg_ad_out[25], U1L224);


--dpm_ni2f_reg_sram_qH_10 is dpm_ni2f_reg_sram_qH_10
--operation mode is normal

dpm_ni2f_reg_sram_qH_10_lut_out = SRAM_IO_10;
dpm_ni2f_reg_sram_qH_10 = DFFEA(dpm_ni2f_reg_sram_qH_10_lut_out, CLK50M, , , dpm_ni2f_reg_sm_10, , );


--A1L541 is ix1970_lc~0
--operation mode is normal

A1L541 = (Z1L922 # A1L502 # !Z1L412 # !Z1L512) & CASCADE(A1L603);


--U1_low_data_out_HR[26] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_data_out_HR[26]
--operation mode is normal

U1_low_data_out_HR[26] = AMPP_FUNCTION(U1_low_data_out_hr_ena_d, U1_low_data_out_HR_lc, U1_mstr_ad_sel, A1L541, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_or[58] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_or[58]
--operation mode is normal

U1_high_ad_or[58] = AMPP_FUNCTION(V1_ad_ce[58], U1_mstr_trg_hi_ad, U1_high_ad_out_lc[26], A1L541, pci_rstn, GLOBAL(pci_clk));


--U1L324 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_not_cc[26]~602
--operation mode is normal

U1L324 = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_low_data_out_HR[26], U1_high_ad_or[58], U1_mstr_trg_low_ad_out_sel);


--U1L193 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_NOT[26]~570
--operation mode is normal

U1L193 = AMPP_FUNCTION(U1_trg_cfg_cyc_out, U1_trg_low_ad_out_sel, U1_trg_cfg_ad_out[26], U1L324);


--dpm_ni2f_reg_sram_qH_11 is dpm_ni2f_reg_sram_qH_11
--operation mode is normal

dpm_ni2f_reg_sram_qH_11_lut_out = SRAM_IO_11;
dpm_ni2f_reg_sram_qH_11 = DFFEA(dpm_ni2f_reg_sram_qH_11_lut_out, CLK50M, , , dpm_ni2f_reg_sm_10, , );


--A1L441 is ix1969_lc~0
--operation mode is normal

A1L441 = (Z1L922 # A1L102 # !Z1L412 # !Z1L512) & CASCADE(A1L013);


--U1_low_data_out_HR[27] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_data_out_HR[27]
--operation mode is normal

U1_low_data_out_HR[27] = AMPP_FUNCTION(U1_low_data_out_hr_ena_d, U1_low_data_out_HR_lc, U1_mstr_ad_sel, A1L441, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_or[59] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_or[59]
--operation mode is normal

U1_high_ad_or[59] = AMPP_FUNCTION(V1_ad_ce[59], U1_mstr_trg_hi_ad, U1_high_ad_out_lc[27], A1L441, pci_rstn, GLOBAL(pci_clk));


--U1L424 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_not_cc[27]~603
--operation mode is normal

U1L424 = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_low_data_out_HR[27], U1_high_ad_or[59], U1_mstr_trg_low_ad_out_sel);


--U1L293 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_NOT[27]~571
--operation mode is normal

U1L293 = AMPP_FUNCTION(U1_trg_cfg_cyc_out, U1_trg_low_ad_out_sel, U1_trg_cfg_ad_out[27], U1L424);


--U1_low_data_out_HR[28] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_data_out_HR[28]
--operation mode is normal

U1_low_data_out_HR[28] = AMPP_FUNCTION(U1_low_data_out_hr_ena_d, U1_mstr_ad_sel, U1_low_data_out_HR_lc, ix2011_lc, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_or[60] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_or[60]
--operation mode is normal

U1_high_ad_or[60] = AMPP_FUNCTION(V1_ad_ce[60], U1_mstr_trg_hi_ad, ix2011_lc, U1_high_ad_out_lc[28], pci_rstn, GLOBAL(pci_clk));


--U1L524 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_not_cc[28]~604
--operation mode is normal

U1L524 = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_low_data_out_HR[28], U1_high_ad_or[60], U1_mstr_trg_low_ad_out_sel);


--U1L393 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_NOT[28]~572
--operation mode is normal

U1L393 = AMPP_FUNCTION(U1_trg_cfg_cyc_out, U1_trg_low_ad_out_sel, U1_trg_cfg_ad_out[28], U1L524);


--U1_low_data_out_HR[29] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_data_out_HR[29]
--operation mode is normal

U1_low_data_out_HR[29] = AMPP_FUNCTION(U1_low_data_out_hr_ena_d, U1_mstr_ad_sel, U1_low_data_out_HR_lc, ix2010_lc, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_or[61] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_or[61]
--operation mode is normal

U1_high_ad_or[61] = AMPP_FUNCTION(V1_ad_ce[61], U1_mstr_trg_hi_ad, ix2010_lc, U1_high_ad_out_lc[29], pci_rstn, GLOBAL(pci_clk));


--U1L624 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_not_cc[29]~605
--operation mode is normal

U1L624 = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_low_data_out_HR[29], U1_high_ad_or[61], U1_mstr_trg_low_ad_out_sel);


--U1L493 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_NOT[29]~573
--operation mode is normal

U1L493 = AMPP_FUNCTION(U1_trg_cfg_cyc_out, U1_trg_low_ad_out_sel, U1_trg_cfg_ad_out[29], U1L624);


--ix2014 is ix2014
--operation mode is normal

ix2014 = Z1L922 # !dpm_ni2f_reg_timeout # !Z1L412 # !Z1L512;


--dpm_ni2f_reg_sram_qH_14 is dpm_ni2f_reg_sram_qH_14
--operation mode is normal

dpm_ni2f_reg_sram_qH_14_lut_out = SRAM_IO_14;
dpm_ni2f_reg_sram_qH_14 = DFFEA(dpm_ni2f_reg_sram_qH_14_lut_out, CLK50M, , , dpm_ni2f_reg_sm_10, , );


--U1_low_data_out_HR[30] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_data_out_HR[30]
--operation mode is normal

U1_low_data_out_HR[30] = AMPP_FUNCTION(U1_low_data_out_hr_ena_d, U1_low_data_out_HR_lc, U1_mstr_ad_sel, A1L341, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_or[62] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_or[62]
--operation mode is normal

U1_high_ad_or[62] = AMPP_FUNCTION(V1_ad_ce[62], U1_mstr_trg_hi_ad, U1_high_ad_out_lc[30], A1L341, pci_rstn, GLOBAL(pci_clk));


--U1L724 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_not_cc[30]~606
--operation mode is normal

U1L724 = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_low_data_out_HR[30], U1_high_ad_or[62], U1_mstr_trg_low_ad_out_sel);


--U1L593 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_NOT[30]~574
--operation mode is normal

U1L593 = AMPP_FUNCTION(U1_trg_cfg_cyc_out, U1_trg_low_ad_out_sel, U1_trg_cfg_ad_out[30], U1L724);


--ix2013 is ix2013
--operation mode is normal

ix2013 = Z1L922 # !dpm_ni2f_reg_end_marker32 # !Z1L412 # !Z1L512;


--dpm_ni2f_reg_sram_qH_15 is dpm_ni2f_reg_sram_qH_15
--operation mode is normal

dpm_ni2f_reg_sram_qH_15_lut_out = SRAM_IO_15;
dpm_ni2f_reg_sram_qH_15 = DFFEA(dpm_ni2f_reg_sram_qH_15_lut_out, CLK50M, , , dpm_ni2f_reg_sm_10, , );


--U1_low_data_out_HR[31] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_data_out_HR[31]
--operation mode is normal

U1_low_data_out_HR[31] = AMPP_FUNCTION(U1_low_data_out_hr_ena_d, U1_low_data_out_HR_lc, U1_mstr_ad_sel, A1L241, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_or[63] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_or[63]
--operation mode is normal

U1_high_ad_or[63] = AMPP_FUNCTION(V1_ad_ce[63], U1_mstr_trg_hi_ad, U1_high_ad_out_lc[31], A1L241, pci_rstn, GLOBAL(pci_clk));


--U1L824 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_not_cc[31]~607
--operation mode is normal

U1L824 = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_low_data_out_HR[31], U1_high_ad_or[63], U1_mstr_trg_low_ad_out_sel);


--U1L693 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_out_lc1_NOT[31]~575
--operation mode is normal

U1L693 = AMPP_FUNCTION(U1_trg_cfg_cyc_out, U1_trg_low_ad_out_sel, U1_trg_cfg_ad_out[31], U1L824);


--W1_adr_phase_end_lc1 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|adr_phase_end_lc1
--operation mode is normal

W1_adr_phase_end_lc1 = AMPP_FUNCTION(W1_MS_ADR, W1_dac_cyc_reg);


--W1_lm_adr_ack_R is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|lm_adr_ack_R
--operation mode is normal

W1_lm_adr_ack_R = AMPP_FUNCTION(W1_lm_adr_ack_R_lc1, W1_lm_adr_ack_R, W1_lm_adr_ack_R_lc2, pci_gntn, pci_rstn, GLOBAL(pci_clk));


--W1_cbe_oer_r1_lc3 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|cbe_oer_r1_lc3
--operation mode is normal

W1_cbe_oer_r1_lc3 = AMPP_FUNCTION(W1_MS_ADR, W1_MS_ADR2, W1_cbe_oer_r1_lc2);


--W1_cbe_oer_r3_d is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|cbe_oer_r3_d
--operation mode is normal

W1_cbe_oer_r3_d = AMPP_FUNCTION(W1_MS_DXFR, W1_mstr_abrt);


--Z1_TS_DXFR is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|TS_DXFR
--operation mode is normal

Z1_TS_DXFR = AMPP_FUNCTION(Z1L083, Z1L773, Z1_TS_DXFR_d_lc[2], A1L234, pci_rstn, GLOBAL(pci_clk));


--Z1_devsel_OR_lc[1] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|devsel_OR_lc[1]
--operation mode is normal

Z1_devsel_OR_lc[1] = AMPP_FUNCTION(Z1_TS_DISC, Z1_TS_DXFR);


--Z1_targ_oeR_reg_lc[3] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|targ_oeR_reg_lc[3]
--operation mode is normal

Z1_targ_oeR_reg_lc[3] = AMPP_FUNCTION(Z1_TS_IDLE_NOT, Z1_TS_TURN_AR);


--Z1_frame_IR is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|frame_IR
--operation mode is normal

Z1_frame_IR = AMPP_FUNCTION(A1L234, pci_rstn, GLOBAL(pci_clk));


--Z1_frame_I1R is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|frame_I1R
--operation mode is normal

Z1_frame_I1R = AMPP_FUNCTION(Z1_frame_IR, pci_rstn, GLOBAL(pci_clk));


--Z1_adr_phase_lc1 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|adr_phase_lc1
--operation mode is normal

Z1_adr_phase_lc1 = AMPP_FUNCTION(Z1_frame_IR, Z1_frame_I1R);


--U1_ad_ir_address[1] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|ad_ir_address[1]
--operation mode is normal

U1_ad_ir_address[1] = AMPP_FUNCTION(U1_ad_IR_ce_address, pci_ad_1, pci_rstn, GLOBAL(pci_clk));


--U1_ad_ir_address[0] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|ad_ir_address[0]
--operation mode is normal

U1_ad_ir_address[0] = AMPP_FUNCTION(U1_ad_IR_ce_address, pci_ad_0, pci_rstn, GLOBAL(pci_clk));


--Z1_targ_oeR_reg_lc[2] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|targ_oeR_reg_lc[2]
--operation mode is normal

Z1_targ_oeR_reg_lc[2] = AMPP_FUNCTION(Z1_TS_IDLE_NOT, U1_ad_ir_address[1], U1_ad_ir_address[0]);


--Z1_idsel_IR is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|idsel_IR
--operation mode is normal

Z1_idsel_IR = AMPP_FUNCTION(pci_idsel, pci_rstn, GLOBAL(pci_clk));


--Z1_targ_oeR_reg_lc[1] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|targ_oeR_reg_lc[1]
--operation mode is normal

Z1_targ_oeR_reg_lc[1] = AMPP_FUNCTION(U1_cben_ir_address[3], U1_cben_ir_address[1], Z1_idsel_IR, U1_cben_ir_address[2]);


--W1L37 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|_~203
--operation mode is normal

W1L37 = AMPP_FUNCTION(A1L944, W1_irdy_or_lc[7]);


--W1L13 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00176~10
--operation mode is normal

W1L13 = AMPP_FUNCTION(A1L944, W1_irdy_or_lc[8], W1_irdy_or_lc[6], A1L744, W1L37);


--W1_MW_HOLD is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MW_HOLD
--operation mode is normal

W1_MW_HOLD = AMPP_FUNCTION(W1_MW_HOLD_lc[1], A1L744, W1_MW_HOLD_lc[2], pci_rstn, GLOBAL(pci_clk), W1L74);


--W1_lm_rdynR is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|lm_rdynR
--operation mode is normal

W1_lm_rdynR = AMPP_FUNCTION(pci_rstn, GLOBAL(pci_clk));


--W1_irdy_or_lc[5] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|irdy_or_lc[5]
--operation mode is normal

W1_irdy_or_lc[5] = AMPP_FUNCTION(W1_MW_HOLD, W1_MW_LXFR, W1_lm_rdynR, W1_direct_xfr);


--W1L02 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00107~2
--operation mode is arithmetic

W1L02 = AMPP_FUNCTION(A1L744, A1L944);

--W1_$00107 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00107
--operation mode is arithmetic

W1_$00107 = AMPP_FUNCTION(A1L744, A1L944);


--U1_trg_par_oe is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|trg_par_oe
--operation mode is normal

U1_trg_par_oe = AMPP_FUNCTION(AB5_REG, Z1_TS_TURN_AR, Z1_TS_IDLE_NOT);


--U1_mstr_par_oe_lc1 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|mstr_par_oe_lc1
--operation mode is normal

U1_mstr_par_oe_lc1 = AMPP_FUNCTION(W1_MS_PARK, W1_MS_ADR2, W1_wr_rdn, W1_MS_DXFR);


--X1_xxh[11] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pk:parity_Chk|xxh[11]
--operation mode is normal

X1_xxh[11] = AMPP_FUNCTION(X1_xxh[10], X1_xxh[9], X1_xxh[8]);


--W1_perr_vldR is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|perr_vldR
--operation mode is normal

W1_perr_vldR = AMPP_FUNCTION(W1_MS_DXFR, W1_irdy_or_not, pci_rstn, GLOBAL(pci_clk), W1_$00088);


--X1_perr_or_not_lc2 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pk:parity_Chk|perr_or_not_lc2
--operation mode is normal

X1_perr_or_not_lc2 = AMPP_FUNCTION(W1_tgt_64_response_reg, BB1_cmd_reg[6], W1_perr_vldR);


--AB3_REG is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_sr:trans64_reg|REG
--operation mode is normal

AB3_REG = AMPP_FUNCTION(Z1_trans64_reg_set, AB3_REG, Z1_trans64_reg_rst_lc1, Z1_trans64_reg_rst_lc2, pci_rstn, GLOBAL(pci_clk));


--Z1_perr_vldR is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|perr_vldR
--operation mode is normal

Z1_perr_vldR = AMPP_FUNCTION(AB5_REG, Z1_trdy_OR_NOT, pci_rstn, GLOBAL(pci_clk), Z1L51);


--X1_perr_or_not_lc3 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pk:parity_Chk|perr_or_not_lc3
--operation mode is normal

X1_perr_or_not_lc3 = AMPP_FUNCTION(BB1_cmd_reg[6], AB3_REG, Z1_perr_vldR);


--X1_perr_or_not_lc1 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pk:parity_Chk|perr_or_not_lc1
--operation mode is normal

X1_perr_or_not_lc1 = AMPP_FUNCTION(BB1_cmd_reg[6], W1_perr_vldR, Z1_perr_vldR);


--X1_xxl[11] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pk:parity_Chk|xxl[11]
--operation mode is normal

X1_xxl[11] = AMPP_FUNCTION(X1_xxl[10], X1_xxl[9], X1_xxl[8]);


--W1_MS_REQ_d_lc[1] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MS_REQ_d_lc[1]
--operation mode is normal

W1_MS_REQ_d_lc[1] = AMPP_FUNCTION(W1_MS_REQ, W1_l_req_vld, W1_park, W1_MS_IDLE_not);


--W1_MS_IDLE_lc1 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MS_IDLE_lc1
--operation mode is normal

W1_MS_IDLE_lc1 = AMPP_FUNCTION(W1_MS_PARK, W1_MS_IDLE_not);


--Z1_TS_DXFR_R is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|TS_DXFR_R
--operation mode is normal

Z1_TS_DXFR_R = AMPP_FUNCTION(Z1_TS_DXFR, pci_rstn, GLOBAL(pci_clk));


--Z1_cfg_dat_vld is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|cfg_dat_vld
--operation mode is normal

Z1_cfg_dat_vld = AMPP_FUNCTION(AB5_REG, Z1_cfg_cyc, Z1_TS_DXFR_R, Z1_TS_DXFR);


--U1_ad_ir_address[31] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|ad_ir_address[31]
--operation mode is normal

U1_ad_ir_address[31] = AMPP_FUNCTION(U1_ad_IR_ce_address, pci_ad_31, pci_rstn, GLOBAL(pci_clk));


--U1_ad_ir_address[30] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|ad_ir_address[30]
--operation mode is normal

U1_ad_ir_address[30] = AMPP_FUNCTION(U1_ad_IR_ce_address, pci_ad_30, pci_rstn, GLOBAL(pci_clk));


--U1_ad_ir_address[29] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|ad_ir_address[29]
--operation mode is normal

U1_ad_ir_address[29] = AMPP_FUNCTION(U1_ad_IR_ce_address, pci_ad_29, pci_rstn, GLOBAL(pci_clk));


--U1_ad_ir_address[28] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|ad_ir_address[28]
--operation mode is normal

U1_ad_ir_address[28] = AMPP_FUNCTION(U1_ad_IR_ce_address, pci_ad_28, pci_rstn, GLOBAL(pci_clk));


--X1_xxlad[7] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pk:parity_Chk|xxlad[7]
--operation mode is normal

X1_xxlad[7] = AMPP_FUNCTION(U1_ad_ir_address[31], U1_ad_ir_address[30], U1_ad_ir_address[29], U1_ad_ir_address[28]);


--U1_ad_ir_address[27] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|ad_ir_address[27]
--operation mode is normal

U1_ad_ir_address[27] = AMPP_FUNCTION(U1_ad_IR_ce_address, pci_ad_27, pci_rstn, GLOBAL(pci_clk));


--U1_ad_ir_address[26] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|ad_ir_address[26]
--operation mode is normal

U1_ad_ir_address[26] = AMPP_FUNCTION(U1_ad_IR_ce_address, pci_ad_26, pci_rstn, GLOBAL(pci_clk));


--U1_ad_ir_address[25] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|ad_ir_address[25]
--operation mode is normal

U1_ad_ir_address[25] = AMPP_FUNCTION(U1_ad_IR_ce_address, pci_ad_25, pci_rstn, GLOBAL(pci_clk));


--U1_ad_ir_address[24] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|ad_ir_address[24]
--operation mode is normal

U1_ad_ir_address[24] = AMPP_FUNCTION(U1_ad_IR_ce_address, pci_ad_24, pci_rstn, GLOBAL(pci_clk));


--X1_xxlad[6] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pk:parity_Chk|xxlad[6]
--operation mode is normal

X1_xxlad[6] = AMPP_FUNCTION(U1_ad_ir_address[27], U1_ad_ir_address[26], U1_ad_ir_address[25], U1_ad_ir_address[24]);


--U1_ad_ir_address[23] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|ad_ir_address[23]
--operation mode is normal

U1_ad_ir_address[23] = AMPP_FUNCTION(U1_ad_IR_ce_address, pci_ad_23, pci_rstn, GLOBAL(pci_clk));


--U1_ad_ir_address[22] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|ad_ir_address[22]
--operation mode is normal

U1_ad_ir_address[22] = AMPP_FUNCTION(U1_ad_IR_ce_address, pci_ad_22, pci_rstn, GLOBAL(pci_clk));


--U1_ad_ir_address[21] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|ad_ir_address[21]
--operation mode is normal

U1_ad_ir_address[21] = AMPP_FUNCTION(U1_ad_IR_ce_address, pci_ad_21, pci_rstn, GLOBAL(pci_clk));


--U1_ad_ir_address[20] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|ad_ir_address[20]
--operation mode is normal

U1_ad_ir_address[20] = AMPP_FUNCTION(U1_ad_IR_ce_address, pci_ad_20, pci_rstn, GLOBAL(pci_clk));


--X1_xxlad[5] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pk:parity_Chk|xxlad[5]
--operation mode is normal

X1_xxlad[5] = AMPP_FUNCTION(U1_ad_ir_address[23], U1_ad_ir_address[22], U1_ad_ir_address[21], U1_ad_ir_address[20]);


--X1_xxlad[4] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pk:parity_Chk|xxlad[4]
--operation mode is normal

X1_xxlad[4] = AMPP_FUNCTION(U1_ad_ir_address[16], U1_ad_ir_address[17], U1_ad_ir_address[18], U1_ad_ir_address[19]);


--X1_xxlad[3] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pk:parity_Chk|xxlad[3]
--operation mode is normal

X1_xxlad[3] = AMPP_FUNCTION(U1_ad_ir_address[12], U1_ad_ir_address[13], U1_ad_ir_address[14], U1_ad_ir_address[15]);


--X1_xxlad[2] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pk:parity_Chk|xxlad[2]
--operation mode is normal

X1_xxlad[2] = AMPP_FUNCTION(U1_ad_ir_address[8], U1_ad_ir_address[9], U1_ad_ir_address[10], U1_ad_ir_address[11]);


--X1_xxlad[1] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pk:parity_Chk|xxlad[1]
--operation mode is normal

X1_xxlad[1] = AMPP_FUNCTION(U1_ad_ir_address[4], U1_ad_ir_address[5], U1_ad_ir_address[6], U1_ad_ir_address[7]);


--X1_xxlad[0] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pk:parity_Chk|xxlad[0]
--operation mode is normal

X1_xxlad[0] = AMPP_FUNCTION(U1_ad_ir_address[2], U1_ad_ir_address[3], U1_ad_ir_address[1], U1_ad_ir_address[0]);


--Z1_stop_or_lc[5] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|stop_or_lc[5]
--operation mode is normal

Z1_stop_or_lc[5] = AMPP_FUNCTION(Z1_cfg_cyc, Z1_TS_DXFR, Z1_targ_burst_lc, Z1_stop_OR_NOT);


--U1_trg_ad_IR_ce_A is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|trg_ad_IR_ce_A
--operation mode is normal

U1_trg_ad_IR_ce_A = AMPP_FUNCTION(Z1_ad_ir_ce_A_lc1, Z1_ad_ir_ce_A_lc2);


--Q7_dffe51a[10] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|dffpipe_ab3:dffpipe14|dffe51a[10]
--operation mode is normal

Q7_dffe51a[10]_lut_out = S3_dffe50a[10];
Q7_dffe51a[10] = DFFEA(Q7_dffe51a[10]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );


--N3L1 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|add_sub_tjb:add_sub16|_~51
--operation mode is normal

N3L1 = Q7_dffe51a[10] $ E5_q[10] $ N3L22;


--H2L3 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_fefifo_v1d:a_fefifo5|_~175
--operation mode is normal

H2L3 = !Q11_dffe51a[7] & !Q11_dffe51a[6] & !Q11_dffe51a[5] & !Q11_dffe51a[4];


--H2L4 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_fefifo_v1d:a_fefifo5|_~177
--operation mode is normal

H2L4 = (dpm_ni2f_reg_rdreq_fifo & !Q11_dffe51a[10] & !Q11_dffe51a[9] & !Q11_dffe51a[8]) & CASCADE(H2L3);


--U1_trg_ad_sel is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|trg_ad_sel
--operation mode is normal

U1_trg_ad_sel = AMPP_FUNCTION(Z1_TS_IDLE_NOT, AB5_REG);


--W1_DXFR_write is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|DXFR_write
--operation mode is normal

W1_DXFR_write = AMPP_FUNCTION(W1_DXFR_write_lc3, W1_DXFR_write_lc4, pci_rstn, GLOBAL(pci_clk), W1_$00107);


--U1_mstr_ad_sel is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|mstr_ad_sel
--operation mode is normal

U1_mstr_ad_sel = AMPP_FUNCTION(W1_MS_ENA, W1_MS_ADR, W1_MS_ADR2, W1_DXFR_write);


--W1_tgt_64_response_reset_lc1 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|tgt_64_response_reset_lc1
--operation mode is normal

W1_tgt_64_response_reset_lc1 = AMPP_FUNCTION(W1_MS_TAR, W1_MW_END, W1_MW_IDLE_not, W1_MR_IDLE_not);


--W1_no_op_reg[6] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|no_op_reg[6]
--operation mode is normal

W1_no_op_reg[6] = AMPP_FUNCTION(pci_rstn, GLOBAL(pci_clk));


--W1_lm_hdata_ack_lc[8] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|lm_hdata_ack_lc[8]
--operation mode is normal

W1_lm_hdata_ack_lc[8] = AMPP_FUNCTION(W1_lm_hdata_ack_lc[5], W1_lm_hdata_ack_lc[7]);


--W1_lm_hdata_ack_lc[6] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|lm_hdata_ack_lc[6]
--operation mode is normal

W1_lm_hdata_ack_lc[6] = AMPP_FUNCTION(W1_MR_IDLE_not, W1_MR_END, W1_MR_LLXFR, W1_wr_rdn);

--W1L252 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|lm_hdata_ack_lc[6]~103
--operation mode is normal

W1L252 = AMPP_FUNCTION(W1_MR_IDLE_not, W1_MR_END, W1_MR_LLXFR, W1_wr_rdn);


--W1_lm_hdata_ack_ena2 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|lm_hdata_ack_ena2
--operation mode is normal

W1_lm_hdata_ack_ena2 = AMPP_FUNCTION(W1_lm_hdata_ack_ena1, W1_lm_ldata_ack_ena1, W1_$00119);


--Z1_lt_hdata_ack_r_d4_lc is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_hdata_ack_r_d4_lc
--operation mode is normal

Z1_lt_hdata_ack_r_d4_lc = AMPP_FUNCTION(Z1_lt_hdata_ack_r_ena_lc1, Z1_lt_hdata_ack_r_d[3], Z1_TS_IDLE_NOT, Z1_lt_hdata_ack_r_d[2]);


--Z1_lt_hdata_ack_r_ena is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_hdata_ack_r_ena
--operation mode is normal

Z1_lt_hdata_ack_r_ena = AMPP_FUNCTION(Z1_lw_lr_done, Z1_lt_ldata_ack_r_ena_lc1, AB3_REG, Z1_lt_hdata_ack_r_ena_lc1);


--W1_devsel_toR is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|devsel_toR
--operation mode is normal

W1_devsel_toR = AMPP_FUNCTION(A1L034, W1_MS_DXFR, W1_devsel_toR_lc1, pci_rstn, GLOBAL(pci_clk));


--W1L04 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00208~3
--operation mode is arithmetic

W1L04 = AMPP_FUNCTION(A1L944, W1_no_op_reg[1]);

--W1_$00208 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00208
--operation mode is arithmetic

W1_$00208 = AMPP_FUNCTION(A1L944, W1_no_op_reg[1]);


--Z1_ad_ir_ce_D_lc1 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|ad_ir_ce_D_lc1
--operation mode is normal

Z1_ad_ir_ce_D_lc1 = AMPP_FUNCTION(Z1L27, Z1_TS_DISC, Z1_TS_DXFR, Z1_LW_WAIT);


--Z1_cfg_adr_dec_ena_lc2 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|cfg_adr_dec_ena_lc2
--operation mode is normal

Z1_cfg_adr_dec_ena_lc2 = AMPP_FUNCTION(U1_cben_ir_address[3], U1_cben_ir_address[1], U1_cben_ir_address[2]);


--Z1L901 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|cfg_cyc~80
--operation mode is normal

Z1L901 = AMPP_FUNCTION(Z1_idsel_IR, Z1_cfg_cyc, U1_ad_ir_address[1], U1_ad_ir_address[0]);


--Z1L011 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|cfg_cyc~81
--operation mode is normal

Z1L011 = AMPP_FUNCTION(Z1_adr_phase_lc1, Z1_cfg_adr_dec_ena_lc2, Z1L901);


--Z1L763 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|TS_ADR_CLMD_d~25
--operation mode is normal

Z1L763 = AMPP_FUNCTION(Z1_TS_ADR_CLMD, W1_mstr_actv_lc, Z1_cfg_cyc, Z1_retry);


--dpm_dec_reg_LT_RDY_n_pci is dpm_dec_reg_LT_RDY_n_pci
--operation mode is normal

dpm_dec_reg_LT_RDY_n_pci_lut_out = dpm_dec_reg_tmp3;
dpm_dec_reg_LT_RDY_n_pci = DFFEA(dpm_dec_reg_LT_RDY_n_pci_lut_out, GLOBAL(pci_clk), pci_rstn, , , , );


--Z1_lt_ldata_ack_r_d[2] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_ldata_ack_r_d[2]
--operation mode is normal

Z1_lt_ldata_ack_r_d[2] = AMPP_FUNCTION(Z1_LR_DONE, Z1_LR_IDLE_NOT);


--Z1L77 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|_~1525
--operation mode is normal

Z1L77 = AMPP_FUNCTION(Z1_TS_IDLE_NOT, AB3_REG, W1_mstr_actv_lc, Z1_lw_lr_done);


--Z1_trans64_reg_R is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|trans64_reg_R
--operation mode is normal

Z1_trans64_reg_R = AMPP_FUNCTION(AB3_REG, pci_rstn, GLOBAL(pci_clk));


--Z1_io_cyc is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|io_cyc
--operation mode is normal

Z1_io_cyc = AMPP_FUNCTION(Z1_io_cyc, Z1_adr_phase_lc1, Z1_io_cyc_s_lc, Z1_TS_IDLE_NOT, pci_rstn, GLOBAL(pci_clk));


--Z1L87 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|_~1526
--operation mode is normal

Z1L87 = AMPP_FUNCTION(dpm_dec_reg_LT_RDY_n_pci, Z1_LW_WAIT, Z1_TS_DXFR);


--Z1_LW_DONE_lc[2] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|LW_DONE_lc[2]
--operation mode is normal

Z1_LW_DONE_lc[2] = AMPP_FUNCTION(Z1L87, Z1_LW_LXFR, Z1_TS_TURN_AR);


--Z1_lw_lr_done is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lw_lr_done
--operation mode is normal

Z1_lw_lr_done = AMPP_FUNCTION(Z1_LW_DONE, Z1_LR_DONE);


--Z1_lt_ldata_ack_r_ena_lc1 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_ldata_ack_r_ena_lc1
--operation mode is normal

Z1_lt_ldata_ack_r_ena_lc1 = AMPP_FUNCTION(Z1_LW_IDLE_NOT, Z1_TS_IDLE_NOT, Z1_$00100);


--W1L32 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00125~0
--operation mode is normal

W1L32 = AMPP_FUNCTION(W1_lm_ldata_ack, W1_tgt_64_response_reg);


--W1L18 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|_~276
--operation mode is normal

W1L18 = AMPP_FUNCTION(W1_MR_IDLE_not, W1_MR_END, W1_MR_LLXFR_r1, W1_MR_LLXFR_r2);


--BB1_cmd_reg[2] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|cmd_reg[2]
--operation mode is normal

BB1_cmd_reg[2] = AMPP_FUNCTION(BB1L59, U1_low_ad_IR_data[2], pci_rstn, GLOBAL(pci_clk));


--W1_lm_ldata_ack_ena2 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|lm_ldata_ack_ena2
--operation mode is normal

W1_lm_ldata_ack_ena2 = AMPP_FUNCTION(W1_MR_END, W1_MW_END);


--W1_$00119 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00119
--operation mode is normal

W1_$00119 = AMPP_FUNCTION(W1_lm_ack_or, W1_lm_rdynR);


--Z1_LR_WAIT is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|LR_WAIT
--operation mode is normal

Z1_LR_WAIT = AMPP_FUNCTION(Z1_LR_WAIT, Z1_lt_rdynR, Z1_direct_xfr, Z1_LR_WAIT_lc[1], pci_rstn, GLOBAL(pci_clk), Z1L25);


--Z1L54 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|$00231~1
--operation mode is arithmetic

Z1L54 = AMPP_FUNCTION(Z1_LR_PXFR_32);

--Z1_$00231 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|$00231
--operation mode is arithmetic

Z1_$00231 = AMPP_FUNCTION(Z1_LR_PXFR_32);


--Z1_LR_WAIT_32 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|LR_WAIT_32
--operation mode is normal

Z1_LR_WAIT_32 = AMPP_FUNCTION(Z1_LR_WAIT_32, Z1_LR_WAIT_32_lc1, pci_rstn, GLOBAL(pci_clk), Z1L06);


--Z1_LR_DONE_lc[2] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|LR_DONE_lc[2]
--operation mode is normal

Z1_LR_DONE_lc[2] = AMPP_FUNCTION(Z1_LR_PXFR, Z1_LR_WAIT, Z1L54, Z1_LR_WAIT_32);


--Z1_LR_DONE_lc[1] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|LR_DONE_lc[1]
--operation mode is normal

Z1_LR_DONE_lc[1] = AMPP_FUNCTION(Z1_TS_DISC, Z1_LR_PXFR, Z1_LR_LXFR, Z1_LR_LXFR_lc[1]);


--W1_MW_END_r[2] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MW_END_r[2]
--operation mode is normal

W1_MW_END_r[2] = AMPP_FUNCTION(W1_devsel_toR, W1_MW_LXFR, W1_MW_IDLE_not, A1L744, pci_rstn, GLOBAL(pci_clk));


--W1_MW_END_r[1] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MW_END_r[1]
--operation mode is normal

W1_MW_END_r[1] = AMPP_FUNCTION(W1_MW_HOLD, W1_devsel_toR, W1_MW_END_lc1, pci_rstn, GLOBAL(pci_clk), W1_$00244);


--W1_MW_END is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MW_END
--operation mode is normal

W1_MW_END = AMPP_FUNCTION(W1_MW_END_r[2], W1_MW_END_r[1]);


--W1_MR_IDLE_lc1 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MR_IDLE_lc1
--operation mode is normal

W1_MR_IDLE_lc1 = AMPP_FUNCTION(W1_MS_ADR2, W1_MS_ADR, W1_dac_cyc_reg, W1_wr_rdn);

--W1L972 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MR_IDLE_lc1~24
--operation mode is normal

W1L972 = AMPP_FUNCTION(W1_MS_ADR2, W1_MS_ADR, W1_dac_cyc_reg, W1_wr_rdn);


--Z1_LR_PXFR_r1 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|LR_PXFR_r1
--operation mode is normal

Z1_LR_PXFR_r1 = AMPP_FUNCTION(Z1L561, pci_rstn, GLOBAL(pci_clk), Z1_$00236);


--Z1_LR_PXFR_r2 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|LR_PXFR_r2
--operation mode is normal

Z1_LR_PXFR_r2 = AMPP_FUNCTION(Z1_LR_WAIT, Z1L54, Z1_LR_PXFR_lc[3], Z1L15, pci_rstn, GLOBAL(pci_clk));


--Z1_LR_PXFR is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|LR_PXFR
--operation mode is normal

Z1_LR_PXFR = AMPP_FUNCTION(Z1_LR_PXFR_r1, Z1_LR_PXFR_r2);


--Z1_lt_ack_R_r3_lc3 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_ack_R_r3_lc3
--operation mode is normal

Z1_lt_ack_R_r3_lc3 = AMPP_FUNCTION(Z1_LR_WAIT, Z1L54, Z1_lt_ack_R_r3_lc1, Z1_lt_ack_R_r3_lc2);


--Z1_lt_ack_R_r1_lc[6] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_ack_R_r1_lc[6]
--operation mode is normal

Z1_lt_ack_R_r1_lc[6] = AMPP_FUNCTION(Z1_lt_ack_R_r1_lc[5], X1_serr_or, Z1_rd_backoff, Z1_retry);


--Z1_lt_ack_R_r1_lc[4] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_ack_R_r1_lc[4]
--operation mode is normal

Z1_lt_ack_R_r1_lc[4] = AMPP_FUNCTION(Z1_lt_ack_R_r1_lc[3], Z1_lt_ack_R_r1_lc[1], Z1_lt_ack_R_r1_lc[2]);


--Z1_int_ack_cyc is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|int_ack_cyc
--operation mode is normal

Z1_int_ack_cyc = AMPP_FUNCTION(Z1_adr_phase_lc1, Z1_int_ack_cyc, Z1_TS_IDLE_NOT, Z1L031, pci_rstn, GLOBAL(pci_clk));


--Z1_direct_xfr is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|direct_xfr
--operation mode is normal

Z1_direct_xfr = AMPP_FUNCTION(AB3_REG, Z1_io_cyc, Z1_int_ack_cyc);


--Z1_LW_LXFR_lc[1] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|LW_LXFR_lc[1]
--operation mode is normal

Z1_LW_LXFR_lc[1] = AMPP_FUNCTION(Z1L292, AB5_REG, Z1_cfg_cyc);


--Z1_LW_LXFR_lc[2] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|LW_LXFR_lc[2]
--operation mode is normal

Z1_LW_LXFR_lc[2] = AMPP_FUNCTION(Z1_LW_LXFR, Z1_TS_DXFR, dpm_dec_reg_LT_RDY_n_pci);


--Z1_TS_DISC_d_lc2 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|TS_DISC_d_lc2
--operation mode is normal

Z1_TS_DISC_d_lc2 = AMPP_FUNCTION(Z1_TS_DXFR, Z1_TS_DISC_d_lc3);


--BB1_cmd_reg[1] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|cmd_reg[1]
--operation mode is normal

BB1_cmd_reg[1] = AMPP_FUNCTION(BB1L59, U1_low_ad_IR_data[1], pci_rstn, GLOBAL(pci_clk));


--BB1_cyc_vld[0] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|cyc_vld[0]
--operation mode is normal

BB1_cyc_vld[0] = AMPP_FUNCTION(BB1_mem_cyc, BB1_cmd_reg[1]);


--GB41_aeb_out is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|lpm_compare:bar0_comp|comptree:comparator|comptree:sub_comptree|cmpchain:cmp_end|aeb_out
--operation mode is normal

GB41_aeb_out = AMPP_FUNCTION(GB31_aeb_out, GB9_aeb_out);


--E8L32 is lpm_counter:dpm_ni2f_tout_ix8|alt_counter_f10ke:wysi_counter|counter_cell[10]~0
--operation mode is normal

E8L32 = dpm_ni2f_reg_sm_1 # !ix2002_lc;


--U1_hi_low_sel is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|hi_low_sel
--operation mode is normal

U1_hi_low_sel = AMPP_FUNCTION(Z1L54, Z1_LR_LXFR, Z1_$00137);


--W1_WAIT_ndirect is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|WAIT_ndirect
--operation mode is normal

W1_WAIT_ndirect = AMPP_FUNCTION(A1L744, A1L944, W1_WAIT_ndirect_lc, W1_direct_xfr, pci_rstn, GLOBAL(pci_clk));


--U1_mstr_hi_low_sel is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|mstr_hi_low_sel
--operation mode is normal

U1_mstr_hi_low_sel = AMPP_FUNCTION(W1_dac_cyc_strobe, W1_MW_DXFR_32, W1_WAIT_ndirect);


--W1_no_op_reg[3] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|no_op_reg[3]
--operation mode is normal

W1_no_op_reg[3] = AMPP_FUNCTION(pci_rstn, GLOBAL(pci_clk));


--W1_MW_LAST_r[3] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MW_LAST_r[3]
--operation mode is normal

W1_MW_LAST_r[3] = AMPP_FUNCTION(A1L744, W1_MW_LAST, W1_devsel_toR, pci_rstn, GLOBAL(pci_clk), W1L64);


--W1_MW_LAST_r[2] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MW_LAST_r[2]
--operation mode is normal

W1_MW_LAST_r[2] = AMPP_FUNCTION(W1_MW_LAST_lc[3], W1_last_xfr, W1L093, pci_rstn, GLOBAL(pci_clk));


--W1_MW_LAST_r[1] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MW_LAST_r[1]
--operation mode is normal

W1_MW_LAST_r[1] = AMPP_FUNCTION(A1L744, W1_MW_LAST_lc[1], W1_last_xfr, W1_MW_LAST_lc[2], pci_rstn, GLOBAL(pci_clk), W1L54);


--W1_MW_LAST is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MW_LAST
--operation mode is normal

W1_MW_LAST = AMPP_FUNCTION(W1_MW_LAST_r[3], W1_MW_LAST_r[2], W1_MW_LAST_r[1]);


--dpm_dec_reg_rdata_CNF_0 is dpm_dec_reg_rdata_CNF_0
--operation mode is normal

dpm_dec_reg_rdata_CNF_0_lut_out = U1_low_ad_IR_data[0] & (U1L232 # U1L222) # !U1_low_ad_IR_data[0] & !U1L232 & U1L222;
dpm_dec_reg_rdata_CNF_0 = DFFEA(dpm_dec_reg_rdata_CNF_0_lut_out, GLOBAL(pci_clk), pci_rstn, , A1L371, , );


--ix2071_lc is ix2071_lc
--operation mode is normal

ix2071_lc = Z1L512 & (Z1L412 & E7_q[0] # !Z1L412 & dpm_dec_reg_rdata_CNF_0);


--U1_trg_low_ad_out_sel is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|trg_low_ad_out_sel
--operation mode is normal

U1_trg_low_ad_out_sel = AMPP_FUNCTION(U1_trg_ad_sel, U1_hi_low_sel);


--BB1L11Q is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|ad_dat_out[0]~reg
--operation mode is normal

BB1L11Q = AMPP_FUNCTION(DB1_decR[2], BB1L4, DB1_decR[1], BB1_cmd_reg[0], pci_rstn, GLOBAL(pci_clk));


--U1_ad_ce_nc is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|ad_ce_nc
--operation mode is normal

U1_ad_ce_nc = AMPP_FUNCTION(U1_mstr_ADOR_ena, U1_trg_ADOR_ena);


--Z1_TS_TURN_AR_d_lc1 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|TS_TURN_AR_d_lc1
--operation mode is normal

Z1_TS_TURN_AR_d_lc1 = AMPP_FUNCTION(Z1_TS_DXFR, Z1_trdy_OR_NOT);


--W1_ad_oer_lc2c is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|ad_oer_lc2c
--operation mode is normal

W1_ad_oer_lc2c = AMPP_FUNCTION(W1_wr_rdn, W1_MS_ADR, W1_MS_ADR2);


--W1_ad_oer_lc2b is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|ad_oer_lc2b
--operation mode is normal

W1_ad_oer_lc2b = AMPP_FUNCTION(W1_wr_rdn, W1_MS_DXFR, W1_irdy_or_not, W1_frame_or_not);


--dpm_dec_reg_rdata_CNF_1 is dpm_dec_reg_rdata_CNF_1
--operation mode is normal

dpm_dec_reg_rdata_CNF_1_lut_out = U1_low_ad_IR_data[1] & (U1L232 # U1L322) # !U1_low_ad_IR_data[1] & !U1L232 & U1L322;
dpm_dec_reg_rdata_CNF_1 = DFFEA(dpm_dec_reg_rdata_CNF_1_lut_out, GLOBAL(pci_clk), pci_rstn, , A1L371, , );


--ix2072_lc is ix2072_lc
--operation mode is normal

ix2072_lc = Z1L512 & (Z1L412 & E7_q[1] # !Z1L412 & dpm_dec_reg_rdata_CNF_1);


--BB1L21Q is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|ad_dat_out[1]~reg
--operation mode is normal

BB1L21Q = AMPP_FUNCTION(DB1_decR[0], BB1L3, DB1_decR[1], BB1_cmd_reg[1], pci_rstn, GLOBAL(pci_clk));


--dpm_dec_reg_rdata_CNF_2 is dpm_dec_reg_rdata_CNF_2
--operation mode is normal

dpm_dec_reg_rdata_CNF_2_lut_out = U1_low_ad_IR_data[2] & (U1L232 # U1L422) # !U1_low_ad_IR_data[2] & !U1L232 & U1L422;
dpm_dec_reg_rdata_CNF_2 = DFFEA(dpm_dec_reg_rdata_CNF_2_lut_out, GLOBAL(pci_clk), pci_rstn, , A1L371, , );


--ix2073_lc is ix2073_lc
--operation mode is normal

ix2073_lc = Z1L512 & (Z1L412 & E7_q[2] # !Z1L412 & dpm_dec_reg_rdata_CNF_2);


--BB1L31Q is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|ad_dat_out[2]~reg
--operation mode is normal

BB1L31Q = AMPP_FUNCTION(DB1_decR[1], DB1_decR[3], BB1_cache_line[2], BB1_cmd_reg[2], pci_rstn, GLOBAL(pci_clk));


--dpm_dec_reg_rdata_CNF_3 is dpm_dec_reg_rdata_CNF_3
--operation mode is normal

dpm_dec_reg_rdata_CNF_3_lut_out = U1_low_ad_IR_data[3] & (U1L232 # U1L522) # !U1_low_ad_IR_data[3] & !U1L232 & U1L522;
dpm_dec_reg_rdata_CNF_3 = DFFEA(dpm_dec_reg_rdata_CNF_3_lut_out, GLOBAL(pci_clk), pci_rstn, , A1L371, , );


--ix2074_lc is ix2074_lc
--operation mode is normal

ix2074_lc = Z1L512 & (Z1L412 & E7_q[3] # !Z1L412 & dpm_dec_reg_rdata_CNF_3);


--BB1L41Q is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|ad_dat_out[3]~reg
--operation mode is normal

BB1L41Q = AMPP_FUNCTION(DB1_decR[3], BB1_cache_line[3], pci_rstn, GLOBAL(pci_clk));


--dpm_dec_reg_rdata_CNF_4 is dpm_dec_reg_rdata_CNF_4
--operation mode is normal

dpm_dec_reg_rdata_CNF_4_lut_out = U1_low_ad_IR_data[4] & (U1L232 # U1L622) # !U1_low_ad_IR_data[4] & !U1L232 & U1L622;
dpm_dec_reg_rdata_CNF_4 = DFFEA(dpm_dec_reg_rdata_CNF_4_lut_out, GLOBAL(pci_clk), pci_rstn, , A1L371, , );


--ix2075_lc is ix2075_lc
--operation mode is normal

ix2075_lc = Z1L512 & (Z1L412 & E7_q[4] # !Z1L412 & dpm_dec_reg_rdata_CNF_4);


--BB1L51Q is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|ad_dat_out[4]~reg
--operation mode is normal

BB1L51Q = AMPP_FUNCTION(DB1_decR[0], BB1L2, DB1_decR[1], BB1_cmd_reg[4], pci_rstn, GLOBAL(pci_clk));


--dpm_dec_reg_rdata_CNF_5 is dpm_dec_reg_rdata_CNF_5
--operation mode is normal

dpm_dec_reg_rdata_CNF_5_lut_out = U1_low_ad_IR_data[5] & (U1L232 # U1L722) # !U1_low_ad_IR_data[5] & !U1L232 & U1L722;
dpm_dec_reg_rdata_CNF_5 = DFFEA(dpm_dec_reg_rdata_CNF_5_lut_out, GLOBAL(pci_clk), pci_rstn, , A1L371, , );


--ix2076_lc is ix2076_lc
--operation mode is normal

ix2076_lc = Z1L512 & (Z1L412 & E7_q[5] # !Z1L412 & dpm_dec_reg_rdata_CNF_5);


--BB1L61Q is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|ad_dat_out[5]~reg
--operation mode is normal

BB1L61Q = AMPP_FUNCTION(DB1_decR[0], DB1_decR[3], BB1_cache_line[5], pci_rstn, GLOBAL(pci_clk));


--dpm_dec_reg_rdata_CNF_6 is dpm_dec_reg_rdata_CNF_6
--operation mode is normal

dpm_dec_reg_rdata_CNF_6_lut_out = U1_low_ad_IR_data[6] & (U1L232 # U1L822) # !U1_low_ad_IR_data[6] & !U1L232 & U1L822;
dpm_dec_reg_rdata_CNF_6 = DFFEA(dpm_dec_reg_rdata_CNF_6_lut_out, GLOBAL(pci_clk), pci_rstn, , A1L371, , );


--ix2077_lc is ix2077_lc
--operation mode is normal

ix2077_lc = Z1L512 & (Z1L412 & E7_q[6] # !Z1L412 & dpm_dec_reg_rdata_CNF_6);


--BB1L71Q is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|ad_dat_out[6]~reg
--operation mode is normal

BB1L71Q = AMPP_FUNCTION(DB1_decR[0], BB1L1, BB1_cmd_reg[6], DB1_decR[1], pci_rstn, GLOBAL(pci_clk));


--dpm_dec_reg_rdata_CNF_7 is dpm_dec_reg_rdata_CNF_7
--operation mode is normal

dpm_dec_reg_rdata_CNF_7_lut_out = U1_low_ad_IR_data[7] & (U1L232 # U1L922) # !U1_low_ad_IR_data[7] & !U1L232 & U1L922;
dpm_dec_reg_rdata_CNF_7 = DFFEA(dpm_dec_reg_rdata_CNF_7_lut_out, GLOBAL(pci_clk), pci_rstn, , A1L371, , );


--ix2079_lc is ix2079_lc
--operation mode is normal

ix2079_lc = Z1L512 & (Z1L412 & E7_q[7] # !Z1L412 & dpm_dec_reg_rdata_CNF_7);


--BB1L81Q is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|ad_dat_out[7]~reg
--operation mode is normal

BB1L81Q = AMPP_FUNCTION(DB1_decR[3], BB1_cache_line[7], pci_rstn, GLOBAL(pci_clk));


--BB1L91Q is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|ad_dat_out[8]~reg
--operation mode is normal

BB1L91Q = AMPP_FUNCTION(DB1_decR[0], BB1_cmd_reg[8], DB1_decR[1], pci_rstn, GLOBAL(pci_clk));


--dpm_dec_reg_rdata_LED_9 is dpm_dec_reg_rdata_LED_9
--operation mode is normal

dpm_dec_reg_rdata_LED_9_lut_out = U1_low_ad_IR_data[9] & (U1L232 # U1L132) # !U1_low_ad_IR_data[9] & !U1L232 & U1L132;
dpm_dec_reg_rdata_LED_9 = DFFEA(dpm_dec_reg_rdata_LED_9_lut_out, GLOBAL(pci_clk), pci_rstn, , A1L271, , );


--BB1L02Q is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|ad_dat_out[11]~reg
--operation mode is normal

BB1L02Q = AMPP_FUNCTION(DB1_decR[3], BB1_lat_tmr_reg[0], pci_rstn, GLOBAL(pci_clk));


--BB1L12Q is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|ad_dat_out[12]~reg
--operation mode is normal

BB1L12Q = AMPP_FUNCTION(DB1_decR[0], DB1_decR[3], BB1_lat_tmr_reg[1], pci_rstn, GLOBAL(pci_clk));


--BB1L22Q is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|ad_dat_out[13]~reg
--operation mode is normal

BB1L22Q = AMPP_FUNCTION(DB1_decR[3], BB1_lat_tmr_reg[2], pci_rstn, GLOBAL(pci_clk));


--BB1L32Q is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|ad_dat_out[14]~reg
--operation mode is normal

BB1L32Q = AMPP_FUNCTION(DB1_decR[3], BB1_lat_tmr_reg[3], pci_rstn, GLOBAL(pci_clk));


--BB1L42Q is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|ad_dat_out[15]~reg
--operation mode is normal

BB1L42Q = AMPP_FUNCTION(DB1_decR[3], BB1_lat_tmr_reg[4], pci_rstn, GLOBAL(pci_clk));


--E6L31 is lpm_counter:dpm_ni2f_naddr_dup_2_ix8|alt_counter_f10ke:wysi_counter|counter_cell[5]~0
--operation mode is normal

E6L31 = dpm_ni2f_reg_sm_10 # !ix2007_lc;


--BB1L52Q is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|ad_dat_out[18]~reg
--operation mode is normal

BB1L52Q = AMPP_FUNCTION(DB1_decR[0], pci_rstn, GLOBAL(pci_clk));


--BB1L62Q is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|ad_dat_out[20]~reg
--operation mode is normal

BB1L62Q = AMPP_FUNCTION(BB1_bar0_reg[20], DB1_decR[4], pci_rstn, GLOBAL(pci_clk));


--BB1L72Q is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|ad_dat_out[21]~reg
--operation mode is normal

BB1L72Q = AMPP_FUNCTION(BB1_bar0_reg[21], DB1_decR[4], pci_rstn, GLOBAL(pci_clk));


--BB1L82Q is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|ad_dat_out[22]~reg
--operation mode is normal

BB1L82Q = AMPP_FUNCTION(BB1_bar0_reg[22], DB1_decR[4], pci_rstn, GLOBAL(pci_clk));


--BB1L92Q is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|ad_dat_out[23]~reg
--operation mode is normal

BB1L92Q = AMPP_FUNCTION(BB1_bar0_reg[23], DB1_decR[4], pci_rstn, GLOBAL(pci_clk));


--ix2022_lc is ix2022_lc
--operation mode is normal

ix2022_lc = Z1L512 & Z1L412 & !dpm_ni2f_reg_sm_10 & !dpm_ni2f_reg_sm_8;


--ix2023_lc is ix2023_lc
--operation mode is normal

ix2023_lc = !dpm_ni2f_reg_sm_6 & !dpm_ni2f_reg_sm_4 & !dpm_ni2f_reg_sm_2 & dpm_ni2f_reg_sm_0;


--BB1L03Q is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|ad_dat_out[24]~reg
--operation mode is normal

BB1L03Q = AMPP_FUNCTION(DB1_decR[2], BB1L9, DB1_decR[1], BB1_stat_reg[8], pci_rstn, GLOBAL(pci_clk));


--ix2021_lc is ix2021_lc
--operation mode is normal

ix2021_lc = !dpm_ni2f_reg_sm_5 & !dpm_ni2f_reg_sm_4 & !dpm_ni2f_reg_sm_1 & dpm_ni2f_reg_sm_0;


--ix2085_lc is ix2085_lc
--operation mode is normal

ix2085_lc = !dpm_ni2f_reg_sm_9 & !dpm_ni2f_reg_sm_8;


--BB1L13Q is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|ad_dat_out[25]~reg
--operation mode is normal

BB1L13Q = AMPP_FUNCTION(DB1_decR[2], BB1_bar0_reg[25], DB1_decR[4], pci_rstn, GLOBAL(pci_clk));


--BB1L23Q is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|ad_dat_out[26]~reg
--operation mode is normal

BB1L23Q = AMPP_FUNCTION(DB1_decR[1], DB1_decR[2], BB1_bar0_reg[26], DB1_decR[4], pci_rstn, GLOBAL(pci_clk));


--BB1L33Q is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|ad_dat_out[27]~reg
--operation mode is normal

BB1L33Q = AMPP_FUNCTION(DB1_decR[2], BB1_bar0_reg[27], DB1_decR[4], pci_rstn, GLOBAL(pci_clk));


--BB1L43Q is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|ad_dat_out[28]~reg
--operation mode is normal

BB1L43Q = AMPP_FUNCTION(DB1_decR[2], BB1L8, DB1_decR[1], AB7_REG, pci_rstn, GLOBAL(pci_clk));


--BB1L53Q is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|ad_dat_out[29]~reg
--operation mode is normal

BB1L53Q = AMPP_FUNCTION(DB1_decR[2], BB1L7, DB1_decR[1], AB8_REG, pci_rstn, GLOBAL(pci_clk));


--BB1L63Q is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|ad_dat_out[30]~reg
--operation mode is normal

BB1L63Q = AMPP_FUNCTION(DB1_decR[2], BB1L6, DB1_decR[1], AB9_REG, pci_rstn, GLOBAL(pci_clk));


--BB1L73Q is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|ad_dat_out[31]~reg
--operation mode is normal

BB1L73Q = AMPP_FUNCTION(DB1_decR[2], BB1L5, DB1_decR[1], AB01_REG, pci_rstn, GLOBAL(pci_clk));


--W1_cbe_oer_r1_lc2 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|cbe_oer_r1_lc2
--operation mode is normal

W1_cbe_oer_r1_lc2 = AMPP_FUNCTION(W1_MS_DXFR, W1_irdy_or_not, W1_frame_or_not);


--W1L67 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|_~227
--operation mode is normal

W1L67 = AMPP_FUNCTION(W1_MS_IDLE_not, W1_frame_or_not);


--W1L651 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|frame_or_lc1~9
--operation mode is normal

W1L651 = AMPP_FUNCTION(W1_frame_or_lc1a, W1_last_xfr, W1_frame_or_lc1b, W1_frame_or_lc1c, W1L67);


--W1_irdy_or_lc[7] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|irdy_or_lc[7]
--operation mode is normal

W1_irdy_or_lc[7] = AMPP_FUNCTION(W1_MR_PXFR, W1_MW_DXFR_32, W1_MW_DXFR);


--W1_irdy_or_lc[8] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|irdy_or_lc[8]
--operation mode is normal

W1_irdy_or_lc[8] = AMPP_FUNCTION(W1_MW_LAST, W1_MR_LPXFR);


--W1_irdy_or_lc[6] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|irdy_or_lc[6]
--operation mode is normal

W1_irdy_or_lc[6] = AMPP_FUNCTION(W1_MR_PXFR, W1_MW_LXFR, W1_lm_rdynR);


--W1_MW_LXFR_r[2] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MW_LXFR_r[2]
--operation mode is normal

W1_MW_LXFR_r[2] = AMPP_FUNCTION(W1_MW_LXFR_lc[3], pci_gntn, pci_rstn, GLOBAL(pci_clk));


--W1_MW_LXFR_r[1] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MW_LXFR_r[1]
--operation mode is normal

W1_MW_LXFR_r[1] = AMPP_FUNCTION(W1_MW_LXFR_lc[1], A1L744, W1_MW_LXFR_lc[2], pci_rstn, GLOBAL(pci_clk), W1_$00208);


--W1_MW_LXFR is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MW_LXFR
--operation mode is normal

W1_MW_LXFR = AMPP_FUNCTION(W1_MW_LXFR_r[2], W1_MW_LXFR_r[1]);


--W1_frame_or_lc1b is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|frame_or_lc1b
--operation mode is normal

W1_frame_or_lc1b = AMPP_FUNCTION(W1_MW_LXFR, W1_direct_xfr, W1_lm_rdynR);


--W1_ms_dxfr_lc1 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|ms_dxfr_lc1
--operation mode is normal

W1_ms_dxfr_lc1 = AMPP_FUNCTION(W1_ms_dxfr_lc1c, W1_ms_dxfr_lc1a, W1_ms_dxfr_lc1b);


--W1_ms_dxfr_lc2 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|ms_dxfr_lc2
--operation mode is normal

W1_ms_dxfr_lc2 = AMPP_FUNCTION(W1_MS_DXFR, W1_irdy_or_not, W1_frame_or_not, W1_mstr_abrt);


--X1_xxh[10] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pk:parity_Chk|xxh[10]
--operation mode is normal

X1_xxh[10] = AMPP_FUNCTION(X1_xxh[7], X1_xxh[6], X1_xxh[5], X1_xxh[4]);


--X1_xxh[9] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pk:parity_Chk|xxh[9]
--operation mode is normal

X1_xxh[9] = AMPP_FUNCTION(X1_xxh[3], X1_xxh[2], X1_xxh[1], X1_xxh[0]);


--U1_high_cben_IR_data[3] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_cben_IR_data[3]
--operation mode is normal

U1_high_cben_IR_data[3] = AMPP_FUNCTION(U1_cben_IR_ce_data, W1_cbe_oer_not, pci_rstn, GLOBAL(pci_clk));


--U1_high_cben_IR_data[2] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_cben_IR_data[2]
--operation mode is normal

U1_high_cben_IR_data[2] = AMPP_FUNCTION(U1_cben_IR_ce_data, W1_cbe_oer_not, pci_rstn, GLOBAL(pci_clk));


--U1_high_cben_IR_data[1] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_cben_IR_data[1]
--operation mode is normal

U1_high_cben_IR_data[1] = AMPP_FUNCTION(U1_cben_IR_ce_data, W1_cbe_oer_not, pci_rstn, GLOBAL(pci_clk));


--U1_high_cben_IR_data[0] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_cben_IR_data[0]
--operation mode is normal

U1_high_cben_IR_data[0] = AMPP_FUNCTION(U1_cben_IR_ce_data, W1_cbe_oer_not, pci_rstn, GLOBAL(pci_clk));


--X1_xxh[8] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pk:parity_Chk|xxh[8]
--operation mode is normal

X1_xxh[8] = AMPP_FUNCTION(U1_high_cben_IR_data[3], U1_high_cben_IR_data[2], U1_high_cben_IR_data[1], U1_high_cben_IR_data[0]);


--X1_xxl[10] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pk:parity_Chk|xxl[10]
--operation mode is normal

X1_xxl[10] = AMPP_FUNCTION(X1_xxl[7], X1_xxl[6], X1_xxl[5], X1_xxl[4]);


--X1_xxl[9] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pk:parity_Chk|xxl[9]
--operation mode is normal

X1_xxl[9] = AMPP_FUNCTION(X1_xxl[3], X1_xxl[2], X1_xxl[1], X1_xxl[0]);


--U1_low_cben_IR_data[3] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_cben_IR_data[3]
--operation mode is normal

U1_low_cben_IR_data[3] = AMPP_FUNCTION(U1_cben_IR_ce_data, pci_cben_3, pci_rstn, GLOBAL(pci_clk));


--U1_low_cben_IR_data[2] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_cben_IR_data[2]
--operation mode is normal

U1_low_cben_IR_data[2] = AMPP_FUNCTION(U1_cben_IR_ce_data, pci_cben_2, pci_rstn, GLOBAL(pci_clk));


--X1_xxl[8] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pk:parity_Chk|xxl[8]
--operation mode is normal

X1_xxl[8] = AMPP_FUNCTION(U1_low_cben_IR_data[0], U1_low_cben_IR_data[1], U1_low_cben_IR_data[3], U1_low_cben_IR_data[2]);


--W1_$00202 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00202
--operation mode is normal

W1_$00202 = AMPP_FUNCTION(W1_frame_or_not, W1_MS_DXFR, W1_mstr_abrt, W1_irdy_or_not);


--W1_$00203 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00203
--operation mode is normal

W1_$00203 = AMPP_FUNCTION(W1_frame_or_not, W1_MS_DXFR, W1_irdy_or_not);


--DB1_dec_up[0] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|pcimt64_cd:cfg_adr_dec|dec_up[0]
--operation mode is normal

DB1_dec_up[0] = AMPP_FUNCTION(U1_ad_ir_address[4], U1_ad_ir_address[5], U1_ad_ir_address[6], U1_ad_ir_address[7]);


--U1_cben_IR_ce_data is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|cben_IR_ce_data
--operation mode is normal

U1_cben_IR_ce_data = AMPP_FUNCTION(U1_mstr_cben_ir_ce_d, U1_trg_cben_IR_ce_D);


--Z1L123 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|stop_or_cc4~0
--operation mode is normal

Z1L123 = AMPP_FUNCTION(Z1_TS_DISC, Z1_LW_LXFR, Z1_$00184, AB5_REG);


--Z1L623 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|stop_or_lc[4]~43
--operation mode is normal

Z1L623 = AMPP_FUNCTION(Z1_TS_DISC, Z1_LR_PXFR, Z1L123);


--Z1L85 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|_~67
--operation mode is normal

Z1L85 = AMPP_FUNCTION(Z1L423, W1_mstr_actv_lc, Z1_TS_ADR_CLMD, Z1_cfg_cyc);


--AB1_REG is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_sr:burst_trans|REG
--operation mode is normal

AB1_REG = AMPP_FUNCTION(A1L234, AB1_REG, Z1_burst_trans_r, pci_rstn, GLOBAL(pci_clk), Z1_$00103);


--Z1_targ_burst_lc is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|targ_burst_lc
--operation mode is normal

Z1_targ_burst_lc = AMPP_FUNCTION(Z1_TS_IDLE_NOT, AB1_REG);


--Z1L263 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|trdy_OR_lc[5]~72
--operation mode is normal

Z1L263 = AMPP_FUNCTION(Z1L953, dpm_dec_reg_LT_RDY_n_pci, Z1_LW_WAIT, Z1_TS_DXFR, Z1L91);


--Z1_ad_ir_ce_A_lc1 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|ad_ir_ce_A_lc1
--operation mode is normal

Z1_ad_ir_ce_A_lc1 = AMPP_FUNCTION(Z1_cfg_cyc, Z1_TS_IDLE_NOT, Z1_adr_phase_lc1);


--Z1_ad_ir_ce_A_lc2 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|ad_ir_ce_A_lc2
--operation mode is normal

Z1_ad_ir_ce_A_lc2 = AMPP_FUNCTION(Z1_LW_LXFR, Z1_TS_TURN_AR, Z1_cfg_cyc, Z1_TS_IDLE_NOT);


--S3_dffe50a[10] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|alt_synch_pipe_cb3:alt_synch_pipe10|dffpipe_cb3:dffpipe47|dffe50a[10]
--operation mode is arithmetic

S3_dffe50a[10]_lut_out = S3_dffe49a[10];
S3_dffe50a[10] = DFFEA(S3_dffe50a[10]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );

--K3L12 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_gray2bin_7qa:a_gray2bin12|cs22a[10]~COUT
--operation mode is arithmetic

K3L12 = CARRY(S3_dffe50a[10]);


--Q7_dffe51a[9] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|dffpipe_ab3:dffpipe14|dffe51a[9]
--operation mode is normal

Q7_dffe51a[9]_lut_out = K3_cs22a[9];
Q7_dffe51a[9] = DFFEA(Q7_dffe51a[9]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );


--Q7_dffe51a[8] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|dffpipe_ab3:dffpipe14|dffe51a[8]
--operation mode is normal

Q7_dffe51a[8]_lut_out = K3_cs22a[8];
Q7_dffe51a[8] = DFFEA(Q7_dffe51a[8]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );


--Q7_dffe51a[7] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|dffpipe_ab3:dffpipe14|dffe51a[7]
--operation mode is normal

Q7_dffe51a[7]_lut_out = K3_cs22a[7];
Q7_dffe51a[7] = DFFEA(Q7_dffe51a[7]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );


--Q7_dffe51a[6] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|dffpipe_ab3:dffpipe14|dffe51a[6]
--operation mode is normal

Q7_dffe51a[6]_lut_out = K3_cs22a[6];
Q7_dffe51a[6] = DFFEA(Q7_dffe51a[6]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );


--Q7_dffe51a[5] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|dffpipe_ab3:dffpipe14|dffe51a[5]
--operation mode is normal

Q7_dffe51a[5]_lut_out = K3_cs22a[5];
Q7_dffe51a[5] = DFFEA(Q7_dffe51a[5]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );


--Q7_dffe51a[4] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|dffpipe_ab3:dffpipe14|dffe51a[4]
--operation mode is normal

Q7_dffe51a[4]_lut_out = K3_cs22a[4];
Q7_dffe51a[4] = DFFEA(Q7_dffe51a[4]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );


--Q7_dffe51a[3] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|dffpipe_ab3:dffpipe14|dffe51a[3]
--operation mode is normal

Q7_dffe51a[3]_lut_out = K3_cs22a[3];
Q7_dffe51a[3] = DFFEA(Q7_dffe51a[3]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );


--Q7_dffe51a[1] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|dffpipe_ab3:dffpipe14|dffe51a[1]
--operation mode is normal

Q7_dffe51a[1]_lut_out = K3_cs22a[1];
Q7_dffe51a[1] = DFFEA(Q7_dffe51a[1]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );


--Q7_dffe51a[2] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|dffpipe_ab3:dffpipe14|dffe51a[2]
--operation mode is normal

Q7_dffe51a[2]_lut_out = K3_cs22a[2];
Q7_dffe51a[2] = DFFEA(Q7_dffe51a[2]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );


--Q7_dffe51a[0] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|dffpipe_ab3:dffpipe14|dffe51a[0]
--operation mode is normal

Q7_dffe51a[0]_lut_out = K3L2;
Q7_dffe51a[0] = DFFEA(Q7_dffe51a[0]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );


--Z1L71 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|$00168~10
--operation mode is normal

Z1L71 = AMPP_FUNCTION(A1L734, Z1_devsel_OR_lc[3], Z1_trans64_R, Z1L81);


--Z1_trans64_R is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|trans64_R
--operation mode is normal

Z1_trans64_R = AMPP_FUNCTION(Z1_TS_IDLE_NOT, AB3_REG, Z1_cfg_cyc, Z1_io_cyc);


--W1_MR_END_d_lc2 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MR_END_d_lc2
--operation mode is normal

W1_MR_END_d_lc2 = AMPP_FUNCTION(W1_MR_LPXFR, W1_MR_PXFR);


--W1_MR_END_d_lc1 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MR_END_d_lc1
--operation mode is normal

W1_MR_END_d_lc1 = AMPP_FUNCTION(W1_MR_LLXFR_r1, W1_MR_LLXFR_r2, W1_devsel_toR, W1_MR_END_d_lc2);


--W1_lm_hdata_ack_lc[5] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|lm_hdata_ack_lc[5]
--operation mode is normal

W1_lm_hdata_ack_lc[5] = AMPP_FUNCTION(W1L742, W1L642, W1_lm_hdata_ack_lc[1], W1_lm_hdata_ack_lc[2]);


--W1_lm_hdata_ack_lc[7] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|lm_hdata_ack_lc[7]
--operation mode is normal

W1_lm_hdata_ack_lc[7] = AMPP_FUNCTION(W1_tgt_64_response_reg, W1_lm_hdata_ack_lc[6]);


--W1_lm_hdata_ack_ena1 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|lm_hdata_ack_ena1
--operation mode is normal

W1_lm_hdata_ack_ena1 = AMPP_FUNCTION(W1_MS_DXFR, W1_lm_ldata_ack_ena2, W1_MS_ENA, W1_MS_ADR);


--W1_disc0_det is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|disc0_det
--operation mode is normal

W1_disc0_det = AMPP_FUNCTION(W1_disc0_det_set, W1_MS_ENA, W1_MS_REQ, W1_disc0_det, pci_rstn, GLOBAL(pci_clk));


--W1_tabrt_set is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|tabrt_set
--operation mode is normal

W1_tabrt_set = AMPP_FUNCTION(A1L034, A1L944, W1_MS_DXFR, A1L744, pci_rstn, GLOBAL(pci_clk));


--W1_retry_det is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|retry_det
--operation mode is normal

W1_retry_det = AMPP_FUNCTION(W1_retry_det_set2, W1_MS_ENA, W1_MS_REQ, W1_retry_det, pci_rstn, GLOBAL(pci_clk));


--W1_lm_ldata_ack_ena1 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|lm_ldata_ack_ena1
--operation mode is normal

W1_lm_ldata_ack_ena1 = AMPP_FUNCTION(W1_mstr_abrt, W1_disc0_det, W1_tabrt_set, W1_retry_det);


--Z1_lt_hdata_ack_r_ena_lc1 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_hdata_ack_r_ena_lc1
--operation mode is normal

Z1_lt_hdata_ack_r_ena_lc1 = AMPP_FUNCTION(Z1_lt_hdata_ack_r_prn[2], Z1_lt_hdata_ack_r_prn[3], AB5_REG);


--Z1_lt_hdata_ack_r_d[3] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_hdata_ack_r_d[3]
--operation mode is normal

Z1_lt_hdata_ack_r_d[3] = AMPP_FUNCTION(AB4_REG, Z1_mem_cyc, Z1_TS_ADR_VLD, AB5_REG);


--Z1_lt_hdata_ack_r_d[2] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_hdata_ack_r_d[2]
--operation mode is normal

Z1_lt_hdata_ack_r_d[2] = AMPP_FUNCTION(Z1_mem_cyc, Z1_lt_ldata_ack_r_d[2]);


--Z1_mem_cyc_s_lc is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|mem_cyc_s_lc
--operation mode is normal

Z1_mem_cyc_s_lc = AMPP_FUNCTION(U1_cben_ir_address[2], U1_cben_ir_address[1], U1_cben_ir_address[3], U1_cben_ir_address[0]);


--dpm_dec_reg_tmp3 is dpm_dec_reg_tmp3
--operation mode is normal

dpm_dec_reg_tmp3_lut_out = dpm_dec_reg_tmp2;
dpm_dec_reg_tmp3 = DFFEA(dpm_dec_reg_tmp3_lut_out, GLOBAL(pci_clk), pci_rstn, , , , );


--Z1_lreg_busy is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lreg_busy
--operation mode is normal

Z1_lreg_busy = AMPP_FUNCTION(Z1_LW_DONE, Z1_TS_IDLE_NOT, Z1_lreg_busy, Z1_LW_IDLE_NOT, pci_rstn, GLOBAL(pci_clk));


--Z1_retry_set is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|retry_set
--operation mode is normal

Z1_retry_set = AMPP_FUNCTION(Z1_lreg_busy, Z1_retry_set_lc);


--Z1L413 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|retry_rst_lc2~38
--operation mode is normal

Z1L413 = AMPP_FUNCTION(AB5_REG, Z1_TS_ADR_CLMD, Z1_retry_rst_lc1, Z1_cfg_cyc);


--Z1_retry_rst_lc2 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|retry_rst_lc2
--operation mode is normal

Z1_retry_rst_lc2 = AMPP_FUNCTION(Z1L413, Z1_retry_rst_lc1, Z1_TS_IDLE_NOT, Z1_adr_phase_lc1);


--Z1_trans64_sr_edge_rst is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|trans64_sr_edge_rst
--operation mode is normal

Z1_trans64_sr_edge_rst = AMPP_FUNCTION(Z1_lw_lr_done, Z1_LR_IDLE_NOT, Z1_LW_IDLE_NOT, Z1_TS_IDLE_NOT);


--Z1L112 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_ack_R~19
--operation mode is normal

Z1L112 = AMPP_FUNCTION(Z1_lt_ack_R_r1, Z1_lt_ack_R_r2);


--Z1_$00100 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|$00100
--operation mode is normal

Z1_$00100 = AMPP_FUNCTION(Z1_lt_rdynR, Z1_lt_ack_R_r4, Z1_lt_ack_R_r3, Z1L112);


--W1_lm_ack_or_r[4] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|lm_ack_or_r[4]
--operation mode is normal

W1_lm_ack_or_r[4] = AMPP_FUNCTION(W1_lm_ack_or_lc[8], W1_MS_ENA, W1_lm_ack_or_lc[9], pci_gntn, pci_rstn, GLOBAL(pci_clk));


--W1_lm_ack_or_r[3] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|lm_ack_or_r[3]
--operation mode is normal

W1_lm_ack_or_r[3] = AMPP_FUNCTION(A1L744, W1_lm_ack_or_lc[10], W1_lm_ack_or_lc[4], A1L034, pci_rstn, GLOBAL(pci_clk));


--W1_lm_ack_or_r[2] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|lm_ack_or_r[2]
--operation mode is normal

W1_lm_ack_or_r[2] = AMPP_FUNCTION(A1L744, W1_lm_ack_or_lc[2], W1_last_xfr, W1L212, pci_rstn, GLOBAL(pci_clk), W1L33);


--W1_lm_ack_or_r[1] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|lm_ack_or_r[1]
--operation mode is normal

W1_lm_ack_or_r[1] = AMPP_FUNCTION(A1L744, W1_MW_DXFR_32, W1_last_xfr, pci_rstn, GLOBAL(pci_clk), W1L23);


--W1_lm_ack_or is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|lm_ack_or
--operation mode is normal

W1_lm_ack_or = AMPP_FUNCTION(W1_lm_ack_or_r[4], W1_lm_ack_or_r[3], W1_lm_ack_or_r[2], W1_lm_ack_or_r[1]);


--Z1_LR_LXFR_lc[1] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|LR_LXFR_lc[1]
--operation mode is normal

Z1_LR_LXFR_lc[1] = AMPP_FUNCTION(Z1_lt_ldata_ack_r, Z1_lt_rdynR_R, Z1_direct_xfr);


--Z1L53 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|$00216~0
--operation mode is normal

Z1L53 = AMPP_FUNCTION(Z1_TS_ADR_VLD, X1_serr_or, Z1_cfg_cyc);


--Z1L52 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|$00204~0
--operation mode is normal

Z1L52 = AMPP_FUNCTION(Z1_TS_ADR_CLMD, W1_mstr_actv_lc, Z1_retry);


--Z1L15 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|$00240~0
--operation mode is normal

Z1L15 = AMPP_FUNCTION(A1L234, A1L734);


--Z1_lt_ack_R_r3_lc1 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_ack_R_r3_lc1
--operation mode is normal

Z1_lt_ack_R_r3_lc1 = AMPP_FUNCTION(Z1_LR_PXFR, Z1_direct_xfr, Z1_lt_ldata_ack_r, Z1_lt_rdynR);


--Z1_lt_ack_R_r3_lc2 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_ack_R_r3_lc2
--operation mode is normal

Z1_lt_ack_R_r3_lc2 = AMPP_FUNCTION(Z1_LR_PXFR, Z1_TS_ADR_VLD, Z1_TS_ADR_CLMD, Z1_lt_rdynR);


--Z1_lt_ack_R_r1_lc[5] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_ack_R_r1_lc[5]
--operation mode is normal

Z1_lt_ack_R_r1_lc[5] = AMPP_FUNCTION(Z1_TS_ADR_VLD, Z1_LR_IDLE_NOT, AB5_REG, Z1_cfg_cyc);


--Z1_lt_ack_R_r1_lc[3] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_ack_R_r1_lc[3]
--operation mode is normal

Z1_lt_ack_R_r1_lc[3] = AMPP_FUNCTION(Z1_LR_LXFR, Z1_lt_ldata_ack_r, Z1_TS_ADR_VLD, Z1_TS_ADR_CLMD);


--Z1_lt_ack_R_r1_lc[1] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_ack_R_r1_lc[1]
--operation mode is normal

Z1_lt_ack_R_r1_lc[1] = AMPP_FUNCTION(Z1_lt_rdynR, Z1_lt_ldata_ack_r, Z1_direct_xfr, Z1_lt_rdynR_R);


--Z1_lt_ack_R_r1_lc[2] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_ack_R_r1_lc[2]
--operation mode is normal

Z1_lt_ack_R_r1_lc[2] = AMPP_FUNCTION(Z1_direct_xfr, Z1_lt_ldata_ack_r, Z1_lt_rdynR_R, Z1_lt_rdynR);


--Z1L031 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|int_ack_cyc~75
--operation mode is normal

Z1L031 = AMPP_FUNCTION(U1_cben_ir_address[0], U1_cben_ir_address[3], U1_cben_ir_address[2], U1_cben_ir_address[1]);


--Z1_LR_LXFR_lc[5] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|LR_LXFR_lc[5]
--operation mode is normal

Z1_LR_LXFR_lc[5] = AMPP_FUNCTION(Z1L351, AB5_REG);


--Z1_TS_DISC_d_lc3 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|TS_DISC_d_lc3
--operation mode is normal

Z1_TS_DISC_d_lc3 = AMPP_FUNCTION(Z1_cfg_cyc, Z1_targ_burst_lc);


--Z1L073 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|TS_DISC_d_lc1~7
--operation mode is normal

Z1L073 = AMPP_FUNCTION(Z1_cfg_cyc, Z1_targ_burst_lc, Z1_trdy_OR_NOT, Z1_TS_DXFR, Z1L42);


--Z1L1 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|$00081~0
--operation mode is normal

Z1L1 = AMPP_FUNCTION(Z1_idsel_IR, U1_cben_ir_address[3], U1_cben_ir_address[1], U1_cben_ir_address[2]);


--Z1L311 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|cfg_type0_cyc~21
--operation mode is normal

Z1L311 = AMPP_FUNCTION(Z1_adr_phase_lc1, U1_ad_ir_address[1], U1_ad_ir_address[0], Z1L1);


--GB31_aeb_out is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|lpm_compare:bar0_comp|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|cmpchain:cmp_end|aeb_out
--operation mode is normal

GB31_aeb_out = AMPP_FUNCTION(GB11_aeb_out, GB21_aeb_out);


--GB9_aeb_out is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|lpm_compare:bar0_comp|comptree:comparator|cmpchain:cmp[0]|comptree:comp|comptree:sub_comptree|cmpchain:cmp_end|aeb_out
--operation mode is normal

GB9_aeb_out = AMPP_FUNCTION(GB8_aeb_out, GB7_aeb_out, GB5_aeb_out, GB6_aeb_out);


--ix2002_lc is ix2002_lc
--operation mode is normal

ix2002_lc = dpm_ni2f_reg_sm_2 # dpm_ni2f_reg_sm_1;


--W1_MW_DXFR_32_r[3] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MW_DXFR_32_r[3]
--operation mode is normal

W1_MW_DXFR_32_r[3] = AMPP_FUNCTION(A1L744, W1_lm_rdynR, W1_MW_DXFR_32, pci_rstn, GLOBAL(pci_clk), W1L05);


--W1_MW_DXFR_32_r[2] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MW_DXFR_32_r[2]
--operation mode is normal

W1_MW_DXFR_32_r[2] = AMPP_FUNCTION(W1_MW_DXFR_32_lc[2], A1L744, W1_MW_DXFR_32_lc[3], pci_rstn, GLOBAL(pci_clk), W1L94);


--W1_MW_DXFR_32_r[1] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MW_DXFR_32_r[1]
--operation mode is normal

W1_MW_DXFR_32_r[1] = AMPP_FUNCTION(A1L744, W1_MW_DXFR_32_lc[1], W1_MW_WAIT_32, W1_latcntr_toR, pci_rstn, GLOBAL(pci_clk), W1L84);


--W1_MW_DXFR_32 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MW_DXFR_32
--operation mode is normal

W1_MW_DXFR_32 = AMPP_FUNCTION(W1_MW_DXFR_32_r[3], W1_MW_DXFR_32_r[2], W1_MW_DXFR_32_r[1]);


--Z1L8 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|$00136~0
--operation mode is normal

Z1L8 = AMPP_FUNCTION(A1L734, Z1_wait_wait32_lc[4]);


--Z1_no_op_reg[11] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|no_op_reg[11]
--operation mode is normal

Z1_no_op_reg[11] = AMPP_FUNCTION(pci_rstn, GLOBAL(pci_clk));


--W1L12 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00115~2
--operation mode is normal

W1L12 = AMPP_FUNCTION(A1L744, W1_WAIT_WAIT32_lc3, W1_MW_WAIT_32_d_lc_1d, A1L944);


--W1L093 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MW_LAST_r2_d~27
--operation mode is normal

W1L093 = AMPP_FUNCTION(W1_direct_xfr, Z1_targ_oeR_reg, Z1_ack64_OR_not);


--U1_low_data_out_HR_lc is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_data_out_HR_lc
--operation mode is normal

U1_low_data_out_HR_lc = AMPP_FUNCTION(U1_trg_ad_sel, W1_MS_ENA);


--U1_high_data_out_HR[0] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_data_out_HR[0]
--operation mode is normal

U1_high_data_out_HR[0] = AMPP_FUNCTION(U1_high_data_out_HR_ena, U1_trg_ad_sel, U1_mstr_ad_sel, A1L171, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_out_lc[0] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_out_lc[0]
--operation mode is normal

U1_high_ad_out_lc[0] = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_high_data_out_HR[0], U1_trg_ad_sel, U1_mstr_ad_sel);


--DB1_decR[2] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|pcimt64_cd:cfg_adr_dec|decR[2]
--operation mode is normal

DB1_decR[2] = AMPP_FUNCTION(Z1_cfg_adr_dec_ena, DB1_dec_up[0], U1_ad_ir_address[3], U1_ad_ir_address[2], pci_rstn, GLOBAL(pci_clk));


--BB1_cache_line[0] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|cache_line[0]
--operation mode is normal

BB1_cache_line[0] = AMPP_FUNCTION(BB1L28, U1_low_ad_IR_data[0], pci_rstn, GLOBAL(pci_clk));


--DB1_decR[3] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|pcimt64_cd:cfg_adr_dec|decR[3]
--operation mode is normal

DB1_decR[3] = AMPP_FUNCTION(Z1_cfg_adr_dec_ena, U1_ad_ir_address[3], DB1_dec_up[0], U1_ad_ir_address[2], pci_rstn, GLOBAL(pci_clk));


--BB1L4 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|_~36
--operation mode is normal

BB1L4 = AMPP_FUNCTION(BB1_cache_line[0], DB1_decR[3]);


--BB1_cmd_reg[0] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|cmd_reg[0]
--operation mode is normal

BB1_cmd_reg[0] = AMPP_FUNCTION(BB1L59, U1_low_ad_IR_data[0], pci_rstn, GLOBAL(pci_clk));


--U1_mstr_ADOR_ena is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|mstr_ADOR_ena
--operation mode is normal

U1_mstr_ADOR_ena = AMPP_FUNCTION(W1_ADOR_ena_lc, W1_mstr_actv_lc, W1_wr_rdn, W1_MW_LXFR);


--Z1_trg_OR_advance is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|trg_OR_advance
--operation mode is normal

Z1_trg_OR_advance = AMPP_FUNCTION(Z1_TS_ADR_CLMD, Z1_cfg_cyc, Z1_TS_ADR_VLD, AB5_REG, pci_rstn, GLOBAL(pci_clk));


--U1_trg_ADOR_ena is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|trg_ADOR_ena
--operation mode is normal

U1_trg_ADOR_ena = AMPP_FUNCTION(Z1_LR_LXFR, Z1_trg_OR_advance);


--U1_high_data_out_HR[1] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_data_out_HR[1]
--operation mode is normal

U1_high_data_out_HR[1] = AMPP_FUNCTION(U1_high_data_out_HR_ena, U1_trg_ad_sel, U1_mstr_ad_sel, A1L071, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_out_lc[1] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_out_lc[1]
--operation mode is normal

U1_high_ad_out_lc[1] = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_high_data_out_HR[1], U1_trg_ad_sel, U1_mstr_ad_sel);


--DB1_decR[0] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|pcimt64_cd:cfg_adr_dec|decR[0]
--operation mode is normal

DB1_decR[0] = AMPP_FUNCTION(Z1_cfg_adr_dec_ena, DB1_dec_up[0], U1_ad_ir_address[2], U1_ad_ir_address[3], pci_rstn, GLOBAL(pci_clk));


--BB1_cache_line[1] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|cache_line[1]
--operation mode is normal

BB1_cache_line[1] = AMPP_FUNCTION(BB1L28, U1_low_ad_IR_data[1], pci_rstn, GLOBAL(pci_clk));


--BB1L3 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|_~35
--operation mode is normal

BB1L3 = AMPP_FUNCTION(DB1_decR[3], BB1_cache_line[1]);


--U1_high_data_out_HR[2] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_data_out_HR[2]
--operation mode is normal

U1_high_data_out_HR[2] = AMPP_FUNCTION(U1_high_data_out_HR_ena, U1_trg_ad_sel, U1_mstr_ad_sel, A1L961, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_out_lc[2] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_out_lc[2]
--operation mode is normal

U1_high_ad_out_lc[2] = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_high_data_out_HR[2], U1_trg_ad_sel, U1_mstr_ad_sel);


--BB1_cache_line[2] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|cache_line[2]
--operation mode is normal

BB1_cache_line[2] = AMPP_FUNCTION(BB1L28, U1_low_ad_IR_data[2], pci_rstn, GLOBAL(pci_clk));


--U1_high_data_out_HR[3] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_data_out_HR[3]
--operation mode is normal

U1_high_data_out_HR[3] = AMPP_FUNCTION(U1_high_data_out_HR_ena, U1_trg_ad_sel, U1_mstr_ad_sel, A1L861, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_out_lc[3] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_out_lc[3]
--operation mode is normal

U1_high_ad_out_lc[3] = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_high_data_out_HR[3], U1_trg_ad_sel, U1_mstr_ad_sel);


--BB1_cache_line[3] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|cache_line[3]
--operation mode is normal

BB1_cache_line[3] = AMPP_FUNCTION(BB1L28, U1_low_ad_IR_data[3], pci_rstn, GLOBAL(pci_clk));


--U1_high_data_out_HR[4] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_data_out_HR[4]
--operation mode is normal

U1_high_data_out_HR[4] = AMPP_FUNCTION(U1_high_data_out_HR_ena, U1_trg_ad_sel, U1_mstr_ad_sel, A1L761, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_out_lc[4] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_out_lc[4]
--operation mode is normal

U1_high_ad_out_lc[4] = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_high_data_out_HR[4], U1_trg_ad_sel, U1_mstr_ad_sel);


--BB1_cache_line[4] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|cache_line[4]
--operation mode is normal

BB1_cache_line[4] = AMPP_FUNCTION(BB1L28, U1_low_ad_IR_data[4], pci_rstn, GLOBAL(pci_clk));


--BB1L2 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|_~32
--operation mode is normal

BB1L2 = AMPP_FUNCTION(DB1_decR[3], BB1_cache_line[4]);


--BB1_cmd_reg[4] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|cmd_reg[4]
--operation mode is normal

BB1_cmd_reg[4] = AMPP_FUNCTION(BB1L59, U1_low_ad_IR_data[4], pci_rstn, GLOBAL(pci_clk));


--U1_high_data_out_HR[5] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_data_out_HR[5]
--operation mode is normal

U1_high_data_out_HR[5] = AMPP_FUNCTION(U1_high_data_out_HR_ena, U1_trg_ad_sel, U1_mstr_ad_sel, A1L661, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_out_lc[5] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_out_lc[5]
--operation mode is normal

U1_high_ad_out_lc[5] = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_high_data_out_HR[5], U1_trg_ad_sel, U1_mstr_ad_sel);


--BB1_cache_line[5] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|cache_line[5]
--operation mode is normal

BB1_cache_line[5] = AMPP_FUNCTION(BB1L28, U1_low_ad_IR_data[5], pci_rstn, GLOBAL(pci_clk));


--U1_high_data_out_HR[6] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_data_out_HR[6]
--operation mode is normal

U1_high_data_out_HR[6] = AMPP_FUNCTION(U1_high_data_out_HR_ena, U1_trg_ad_sel, U1_mstr_ad_sel, A1L561, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_out_lc[6] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_out_lc[6]
--operation mode is normal

U1_high_ad_out_lc[6] = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_high_data_out_HR[6], U1_trg_ad_sel, U1_mstr_ad_sel);


--BB1_cache_line[6] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|cache_line[6]
--operation mode is normal

BB1_cache_line[6] = AMPP_FUNCTION(BB1L28, U1_low_ad_IR_data[6], pci_rstn, GLOBAL(pci_clk));


--BB1L1 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|_~30
--operation mode is normal

BB1L1 = AMPP_FUNCTION(DB1_decR[3], BB1_cache_line[6]);


--U1_high_data_out_HR[7] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_data_out_HR[7]
--operation mode is normal

U1_high_data_out_HR[7] = AMPP_FUNCTION(U1_high_data_out_HR_ena, U1_trg_ad_sel, U1_mstr_ad_sel, A1L461, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_out_lc[7] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_out_lc[7]
--operation mode is normal

U1_high_ad_out_lc[7] = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_high_data_out_HR[7], U1_trg_ad_sel, U1_mstr_ad_sel);


--BB1_cache_line[7] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|cache_line[7]
--operation mode is normal

BB1_cache_line[7] = AMPP_FUNCTION(BB1L28, U1_low_ad_IR_data[7], pci_rstn, GLOBAL(pci_clk));


--U1_low_ad_IR_data[9] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_IR_data[9]
--operation mode is normal

U1_low_ad_IR_data[9] = AMPP_FUNCTION(U1_ad_IR_ce_data, pci_ad_9, pci_rstn, GLOBAL(pci_clk));


--U1_high_data_out_HR[9] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_data_out_HR[9]
--operation mode is normal

U1_high_data_out_HR[9] = AMPP_FUNCTION(U1_high_data_out_HR_ena, U1_trg_ad_sel, U1_mstr_ad_sel, A1L261, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_out_lc[9] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_out_lc[9]
--operation mode is normal

U1_high_ad_out_lc[9] = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_high_data_out_HR[9], U1_trg_ad_sel, U1_mstr_ad_sel);


--U1_high_data_out_HR[10] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_data_out_HR[10]
--operation mode is normal

U1_high_data_out_HR[10] = AMPP_FUNCTION(U1_high_data_out_HR_ena, U1_mstr_ad_sel, U1_trg_ad_sel, A1L161, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_out_lc[10] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_out_lc[10]
--operation mode is normal

U1_high_ad_out_lc[10] = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_high_data_out_HR[10], U1_trg_ad_sel, U1_mstr_ad_sel);


--U1_high_data_out_HR[11] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_data_out_HR[11]
--operation mode is normal

U1_high_data_out_HR[11] = AMPP_FUNCTION(U1_high_data_out_HR_ena, U1_mstr_ad_sel, U1_trg_ad_sel, A1L061, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_out_lc[11] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_out_lc[11]
--operation mode is normal

U1_high_ad_out_lc[11] = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_high_data_out_HR[11], U1_trg_ad_sel, U1_mstr_ad_sel);


--BB1_lat_tmr_reg[0] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|lat_tmr_reg[0]
--operation mode is normal

BB1_lat_tmr_reg[0] = AMPP_FUNCTION(BB1L38, U1_low_ad_IR_data[11], pci_rstn, GLOBAL(pci_clk));


--U1_high_data_out_HR[12] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_data_out_HR[12]
--operation mode is normal

U1_high_data_out_HR[12] = AMPP_FUNCTION(U1_high_data_out_HR_ena, U1_mstr_ad_sel, U1_trg_ad_sel, A1L951, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_out_lc[12] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_out_lc[12]
--operation mode is normal

U1_high_ad_out_lc[12] = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_high_data_out_HR[12], U1_trg_ad_sel, U1_mstr_ad_sel);


--BB1_lat_tmr_reg[1] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|lat_tmr_reg[1]
--operation mode is normal

BB1_lat_tmr_reg[1] = AMPP_FUNCTION(BB1L38, U1_low_ad_IR_data[12], pci_rstn, GLOBAL(pci_clk));


--U1_high_data_out_HR[13] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_data_out_HR[13]
--operation mode is normal

U1_high_data_out_HR[13] = AMPP_FUNCTION(U1_high_data_out_HR_ena, U1_mstr_ad_sel, U1_trg_ad_sel, A1L851, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_out_lc[13] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_out_lc[13]
--operation mode is normal

U1_high_ad_out_lc[13] = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_high_data_out_HR[13], U1_trg_ad_sel, U1_mstr_ad_sel);


--BB1_lat_tmr_reg[2] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|lat_tmr_reg[2]
--operation mode is normal

BB1_lat_tmr_reg[2] = AMPP_FUNCTION(BB1L38, U1_low_ad_IR_data[13], pci_rstn, GLOBAL(pci_clk));


--U1_high_data_out_HR[14] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_data_out_HR[14]
--operation mode is normal

U1_high_data_out_HR[14] = AMPP_FUNCTION(U1_high_data_out_HR_ena, U1_mstr_ad_sel, U1_trg_ad_sel, A1L751, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_out_lc[14] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_out_lc[14]
--operation mode is normal

U1_high_ad_out_lc[14] = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_high_data_out_HR[14], U1_trg_ad_sel, U1_mstr_ad_sel);


--BB1_lat_tmr_reg[3] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|lat_tmr_reg[3]
--operation mode is normal

BB1_lat_tmr_reg[3] = AMPP_FUNCTION(BB1L38, U1_low_ad_IR_data[14], pci_rstn, GLOBAL(pci_clk));


--U1_high_data_out_HR[15] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_data_out_HR[15]
--operation mode is normal

U1_high_data_out_HR[15] = AMPP_FUNCTION(U1_high_data_out_HR_ena, U1_mstr_ad_sel, U1_trg_ad_sel, A1L651, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_out_lc[15] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_out_lc[15]
--operation mode is normal

U1_high_ad_out_lc[15] = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_high_data_out_HR[15], U1_trg_ad_sel, U1_mstr_ad_sel);


--BB1_lat_tmr_reg[4] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|lat_tmr_reg[4]
--operation mode is normal

BB1_lat_tmr_reg[4] = AMPP_FUNCTION(BB1L38, U1_low_ad_IR_data[15], pci_rstn, GLOBAL(pci_clk));


--U1_high_data_out_HR[16] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_data_out_HR[16]
--operation mode is normal

U1_high_data_out_HR[16] = AMPP_FUNCTION(U1_high_data_out_HR_ena, U1_mstr_ad_sel, U1_trg_ad_sel, A1L551, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_out_lc[16] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_out_lc[16]
--operation mode is normal

U1_high_ad_out_lc[16] = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_high_data_out_HR[16], U1_trg_ad_sel, U1_mstr_ad_sel);


--U1_high_data_out_HR[17] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_data_out_HR[17]
--operation mode is normal

U1_high_data_out_HR[17] = AMPP_FUNCTION(U1_high_data_out_HR_ena, U1_mstr_ad_sel, U1_trg_ad_sel, A1L451, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_out_lc[17] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_out_lc[17]
--operation mode is normal

U1_high_ad_out_lc[17] = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_high_data_out_HR[17], U1_trg_ad_sel, U1_mstr_ad_sel);


--ix2007_lc is ix2007_lc
--operation mode is normal

ix2007_lc = dpm_ni2f_reg_sm_10 # dpm_ni2f_reg_sreset120;


--U1_high_data_out_HR[18] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_data_out_HR[18]
--operation mode is normal

U1_high_data_out_HR[18] = AMPP_FUNCTION(U1_high_data_out_HR_ena, U1_mstr_ad_sel, U1_trg_ad_sel, A1L351, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_out_lc[18] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_out_lc[18]
--operation mode is normal

U1_high_ad_out_lc[18] = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_high_data_out_HR[18], U1_trg_ad_sel, U1_mstr_ad_sel);


--U1_high_data_out_HR[19] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_data_out_HR[19]
--operation mode is normal

U1_high_data_out_HR[19] = AMPP_FUNCTION(U1_high_data_out_HR_ena, U1_mstr_ad_sel, U1_trg_ad_sel, A1L251, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_out_lc[19] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_out_lc[19]
--operation mode is normal

U1_high_ad_out_lc[19] = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_high_data_out_HR[19], U1_trg_ad_sel, U1_mstr_ad_sel);


--U1_high_data_out_HR[20] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_data_out_HR[20]
--operation mode is normal

U1_high_data_out_HR[20] = AMPP_FUNCTION(U1_high_data_out_HR_ena, U1_mstr_ad_sel, U1_trg_ad_sel, A1L151, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_out_lc[20] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_out_lc[20]
--operation mode is normal

U1_high_ad_out_lc[20] = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_high_data_out_HR[20], U1_trg_ad_sel, U1_mstr_ad_sel);


--BB1_bar0_reg[20] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|bar0_reg[20]
--operation mode is normal

BB1_bar0_reg[20] = AMPP_FUNCTION(BB1L83, U1_low_ad_IR_data[20], pci_rstn, GLOBAL(pci_clk));


--DB1_decR[4] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|pcimt64_cd:cfg_adr_dec|decR[4]
--operation mode is normal

DB1_decR[4] = AMPP_FUNCTION(Z1_cfg_adr_dec_ena, DB1_dec_up[1], U1_ad_ir_address[2], U1_ad_ir_address[3], pci_rstn, GLOBAL(pci_clk));


--U1_high_data_out_HR[21] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_data_out_HR[21]
--operation mode is normal

U1_high_data_out_HR[21] = AMPP_FUNCTION(U1_high_data_out_HR_ena, U1_mstr_ad_sel, U1_trg_ad_sel, A1L051, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_out_lc[21] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_out_lc[21]
--operation mode is normal

U1_high_ad_out_lc[21] = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_high_data_out_HR[21], U1_trg_ad_sel, U1_mstr_ad_sel);


--BB1_bar0_reg[21] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|bar0_reg[21]
--operation mode is normal

BB1_bar0_reg[21] = AMPP_FUNCTION(BB1L83, U1_low_ad_IR_data[21], pci_rstn, GLOBAL(pci_clk));


--U1_high_data_out_HR[22] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_data_out_HR[22]
--operation mode is normal

U1_high_data_out_HR[22] = AMPP_FUNCTION(U1_high_data_out_HR_ena, U1_mstr_ad_sel, U1_trg_ad_sel, A1L941, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_out_lc[22] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_out_lc[22]
--operation mode is normal

U1_high_ad_out_lc[22] = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_high_data_out_HR[22], U1_trg_ad_sel, U1_mstr_ad_sel);


--BB1_bar0_reg[22] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|bar0_reg[22]
--operation mode is normal

BB1_bar0_reg[22] = AMPP_FUNCTION(BB1L83, U1_low_ad_IR_data[22], pci_rstn, GLOBAL(pci_clk));


--U1_high_data_out_HR[23] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_data_out_HR[23]
--operation mode is normal

U1_high_data_out_HR[23] = AMPP_FUNCTION(U1_high_data_out_HR_ena, U1_mstr_ad_sel, U1_trg_ad_sel, A1L841, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_out_lc[23] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_out_lc[23]
--operation mode is normal

U1_high_ad_out_lc[23] = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_high_data_out_HR[23], U1_trg_ad_sel, U1_mstr_ad_sel);


--BB1_bar0_reg[23] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|bar0_reg[23]
--operation mode is normal

BB1_bar0_reg[23] = AMPP_FUNCTION(BB1L83, U1_low_ad_IR_data[23], pci_rstn, GLOBAL(pci_clk));


--U1_high_data_out_HR[24] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_data_out_HR[24]
--operation mode is normal

U1_high_data_out_HR[24] = AMPP_FUNCTION(U1_high_data_out_HR_ena, U1_mstr_ad_sel, U1_trg_ad_sel, A1L741, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_out_lc[24] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_out_lc[24]
--operation mode is normal

U1_high_ad_out_lc[24] = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_high_data_out_HR[24], U1_trg_ad_sel, U1_mstr_ad_sel);


--BB1_bar0_reg[24] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|bar0_reg[24]
--operation mode is normal

BB1_bar0_reg[24] = AMPP_FUNCTION(BB1L93, U1_low_ad_IR_data[24], pci_rstn, GLOBAL(pci_clk));


--BB1L9 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|_~51
--operation mode is normal

BB1L9 = AMPP_FUNCTION(BB1_bar0_reg[24], DB1_decR[4]);


--BB1_stat_reg[8] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|stat_reg[8]
--operation mode is normal

BB1_stat_reg[8] = AMPP_FUNCTION(W1_perr_rep_setR, BB1_stat_reg[8], BB1_par_rep_rst, pci_rstn, GLOBAL(pci_clk));


--U1_high_data_out_HR[25] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_data_out_HR[25]
--operation mode is normal

U1_high_data_out_HR[25] = AMPP_FUNCTION(U1_high_data_out_HR_ena, U1_mstr_ad_sel, U1_trg_ad_sel, A1L641, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_out_lc[25] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_out_lc[25]
--operation mode is normal

U1_high_ad_out_lc[25] = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_high_data_out_HR[25], U1_trg_ad_sel, U1_mstr_ad_sel);


--BB1_bar0_reg[25] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|bar0_reg[25]
--operation mode is normal

BB1_bar0_reg[25] = AMPP_FUNCTION(BB1L93, U1_low_ad_IR_data[25], pci_rstn, GLOBAL(pci_clk));


--ix2084 is ix2084
--operation mode is normal

ix2084 = !dpm_ni2f_reg_sm_6 & !dpm_ni2f_reg_sm_5;


--A1L502 is ix2018_lc~0
--operation mode is normal

A1L502 = (!dpm_ni2f_reg_sm_7 & !dpm_ni2f_reg_sm_4 & (!ix2020_lc # !ix2019_lc)) & CASCADE(ix2084);


--U1_high_data_out_HR[26] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_data_out_HR[26]
--operation mode is normal

U1_high_data_out_HR[26] = AMPP_FUNCTION(U1_high_data_out_HR_ena, U1_mstr_ad_sel, U1_trg_ad_sel, A1L541, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_out_lc[26] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_out_lc[26]
--operation mode is normal

U1_high_ad_out_lc[26] = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_high_data_out_HR[26], U1_trg_ad_sel, U1_mstr_ad_sel);


--BB1_bar0_reg[26] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|bar0_reg[26]
--operation mode is normal

BB1_bar0_reg[26] = AMPP_FUNCTION(BB1L93, U1_low_ad_IR_data[26], pci_rstn, GLOBAL(pci_clk));


--ix2087 is ix2087
--operation mode is normal

ix2087 = !dpm_ni2f_reg_sm_10 & !dpm_ni2f_reg_sm_9;


--A1L102 is ix2015_lc~0
--operation mode is normal

A1L102 = (!dpm_ni2f_reg_sm_11 & !dpm_ni2f_reg_sm_8 & (!ix2017_lc # !ix2016_lc)) & CASCADE(ix2087);


--U1_high_data_out_HR[27] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_data_out_HR[27]
--operation mode is normal

U1_high_data_out_HR[27] = AMPP_FUNCTION(U1_high_data_out_HR_ena, U1_mstr_ad_sel, U1_trg_ad_sel, A1L441, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_out_lc[27] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_out_lc[27]
--operation mode is normal

U1_high_ad_out_lc[27] = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_high_data_out_HR[27], U1_trg_ad_sel, U1_mstr_ad_sel);


--BB1_bar0_reg[27] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|bar0_reg[27]
--operation mode is normal

BB1_bar0_reg[27] = AMPP_FUNCTION(BB1L93, U1_low_ad_IR_data[27], pci_rstn, GLOBAL(pci_clk));


--U1_high_data_out_HR[28] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_data_out_HR[28]
--operation mode is normal

U1_high_data_out_HR[28] = AMPP_FUNCTION(U1_high_data_out_HR_ena, U1_trg_ad_sel, U1_mstr_ad_sel, ix2011_lc, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_out_lc[28] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_out_lc[28]
--operation mode is normal

U1_high_ad_out_lc[28] = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_high_data_out_HR[28], U1_trg_ad_sel, U1_mstr_ad_sel);


--BB1_bar0_reg[28] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|bar0_reg[28]
--operation mode is normal

BB1_bar0_reg[28] = AMPP_FUNCTION(BB1L93, U1_low_ad_IR_data[28], pci_rstn, GLOBAL(pci_clk));


--BB1L8 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|_~47
--operation mode is normal

BB1L8 = AMPP_FUNCTION(BB1_bar0_reg[28], DB1_decR[4]);


--AB7_REG is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|pcimt64_sr:$00210|REG
--operation mode is normal

AB7_REG = AMPP_FUNCTION(W1_tabrt_set, AB7_REG, BB1_targ_abrt_rcvd_rst, pci_rstn, GLOBAL(pci_clk));


--U1_high_data_out_HR[29] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_data_out_HR[29]
--operation mode is normal

U1_high_data_out_HR[29] = AMPP_FUNCTION(U1_high_data_out_HR_ena, U1_trg_ad_sel, U1_mstr_ad_sel, ix2010_lc, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_out_lc[29] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_out_lc[29]
--operation mode is normal

U1_high_ad_out_lc[29] = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_high_data_out_HR[29], U1_trg_ad_sel, U1_mstr_ad_sel);


--BB1_bar0_reg[29] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|bar0_reg[29]
--operation mode is normal

BB1_bar0_reg[29] = AMPP_FUNCTION(BB1L93, U1_low_ad_IR_data[29], pci_rstn, GLOBAL(pci_clk));


--BB1L7 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|_~46
--operation mode is normal

BB1L7 = AMPP_FUNCTION(BB1_bar0_reg[29], DB1_decR[4]);


--AB8_REG is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|pcimt64_sr:$00212|REG
--operation mode is normal

AB8_REG = AMPP_FUNCTION(W1_$00070, AB8_REG, BB1_mstr_abrt_rst, pci_rstn, GLOBAL(pci_clk));


--U1_high_data_out_HR[30] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_data_out_HR[30]
--operation mode is normal

U1_high_data_out_HR[30] = AMPP_FUNCTION(U1_high_data_out_HR_ena, U1_mstr_ad_sel, U1_trg_ad_sel, A1L341, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_out_lc[30] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_out_lc[30]
--operation mode is normal

U1_high_ad_out_lc[30] = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_high_data_out_HR[30], U1_trg_ad_sel, U1_mstr_ad_sel);


--BB1_bar0_reg[30] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|bar0_reg[30]
--operation mode is normal

BB1_bar0_reg[30] = AMPP_FUNCTION(BB1L93, U1_low_ad_IR_data[30], pci_rstn, GLOBAL(pci_clk));


--BB1L6 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|_~45
--operation mode is normal

BB1L6 = AMPP_FUNCTION(BB1_bar0_reg[30], DB1_decR[4]);


--AB9_REG is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|pcimt64_sr:$00214|REG
--operation mode is normal

AB9_REG = AMPP_FUNCTION(X1_serr_or, AB9_REG, BB1_serr_rst, pci_rstn, GLOBAL(pci_clk));


--U1_high_data_out_HR[31] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_data_out_HR[31]
--operation mode is normal

U1_high_data_out_HR[31] = AMPP_FUNCTION(U1_high_data_out_HR_ena, U1_mstr_ad_sel, U1_trg_ad_sel, A1L241, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_out_lc[31] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_out_lc[31]
--operation mode is normal

U1_high_ad_out_lc[31] = AMPP_FUNCTION(U1_mstr_trg_hr_dat_sel, U1_high_data_out_HR[31], U1_trg_ad_sel, U1_mstr_ad_sel);


--BB1_bar0_reg[31] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|bar0_reg[31]
--operation mode is normal

BB1_bar0_reg[31] = AMPP_FUNCTION(BB1L93, U1_low_ad_IR_data[31], pci_rstn, GLOBAL(pci_clk));


--BB1L5 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|_~44
--operation mode is normal

BB1L5 = AMPP_FUNCTION(BB1_bar0_reg[31], DB1_decR[4]);


--AB01_REG is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|pcimt64_sr:$00216|REG
--operation mode is normal

AB01_REG = AMPP_FUNCTION(X1_perr_det_setR_r2, AB01L2, AB01_REG, BB1_perr_det_rst, pci_rstn, GLOBAL(pci_clk));


--W1_lm_adr_ack_R_lc1 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|lm_adr_ack_R_lc1
--operation mode is normal

W1_lm_adr_ack_R_lc1 = AMPP_FUNCTION(W1_MS_REQ, W1_park, W1_lm_adr_ack_R, W1_MS_ENA);


--Z1_TS_DXFR_d_lc[2] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|TS_DXFR_d_lc[2]
--operation mode is normal

Z1_TS_DXFR_d_lc[2] = AMPP_FUNCTION(Z1_TS_DXFR, Z1_TS_DISC_d_lc3);


--Z1L45 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|_~51
--operation mode is normal

Z1L45 = AMPP_FUNCTION(Z1_trdy_OR_NOT, Z1_stop_OR_NOT, Z1_TS_DISC);


--Z1L86 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|_~193
--operation mode is normal

Z1L86 = AMPP_FUNCTION(Z1_trdy_OR_NOT, Z1_TS_DXFR);


--W1_frame_or_lc1a is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|frame_or_lc1a
--operation mode is normal

W1_frame_or_lc1a = AMPP_FUNCTION(W1_MR_LLXFR_r1, W1_MR_LLXFR_r2, W1_MS_DXFR, W1_devsel_toR);


--W1_adr_phase is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|adr_phase
--operation mode is normal

W1_adr_phase = AMPP_FUNCTION(W1_MS_ADR, W1_dac_cyc_reg, W1_MS_ENA, pci_gntn, pci_rstn, GLOBAL(pci_clk));


--W1_frame_or_lc1c is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|frame_or_lc1c
--operation mode is normal

W1_frame_or_lc1c = AMPP_FUNCTION(W1_adr_phase, W1_MR_IDLE_not, W1_wr_rdn);


--W1_frame_or_lc3 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|frame_or_lc3
--operation mode is normal

W1_frame_or_lc3 = AMPP_FUNCTION(W1_frame_or_lc3a, W1_last_xfr, W1_frame_or_lc3b, W1_frame_or_lc3c);


--W1_frame_or_lc2 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|frame_or_lc2
--operation mode is normal

W1_frame_or_lc2 = AMPP_FUNCTION(W1_frame_or_lc2a, W1_frame_or_lc2b);


--W1_MR_PXFR_r1 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MR_PXFR_r1
--operation mode is normal

W1_MR_PXFR_r1 = AMPP_FUNCTION(A1L744, W1_MR_PXFR_lc2, W1_MR_PXFR_lc1, W1_last_xfr, pci_rstn, GLOBAL(pci_clk));


--W1_MR_PXFR_r2 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MR_PXFR_r2
--operation mode is normal

W1_MR_PXFR_r2 = AMPP_FUNCTION(W1L013, W1_MR_PXFR, W1_devsel_toR, pci_rstn, GLOBAL(pci_clk));


--W1_MR_PXFR is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MR_PXFR
--operation mode is normal

W1_MR_PXFR = AMPP_FUNCTION(W1_MR_PXFR_r1, W1_MR_PXFR_r2);


--W1_MW_DXFR_r4 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MW_DXFR_r4
--operation mode is normal

W1_MW_DXFR_r4 = AMPP_FUNCTION(A1L744, W1_lm_rdynR, W1_MW_DXFR, W1_last_xfr, pci_rstn, GLOBAL(pci_clk), W1L34);


--W1_MW_DXFR_r3 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MW_DXFR_r3
--operation mode is normal

W1_MW_DXFR_r3 = AMPP_FUNCTION(W1_MW_HOLD_lc[2], A1L744, Z1_targ_oeR_reg, Z1_ack64_OR_not, pci_rstn, GLOBAL(pci_clk));


--W1_MW_DXFR_r1 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MW_DXFR_r1
--operation mode is normal

W1_MW_DXFR_r1 = AMPP_FUNCTION(A1L744, W1_MW_DXFR_lc[1], W1_MW_DXFR_lc[2], W1_last_xfr, pci_rstn, GLOBAL(pci_clk), W1L14);


--W1_MW_DXFR_r2 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MW_DXFR_r2
--operation mode is normal

W1_MW_DXFR_r2 = AMPP_FUNCTION(W1L093, W1_last_xfr, W1_lm_rdynR, pci_rstn, GLOBAL(pci_clk), W1L24);


--W1_MW_DXFR is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MW_DXFR
--operation mode is normal

W1_MW_DXFR = AMPP_FUNCTION(W1_MW_DXFR_r4, W1_MW_DXFR_r3, W1_MW_DXFR_r1, W1_MW_DXFR_r2);

--W1L463 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MW_DXFR~40
--operation mode is normal

W1L463 = AMPP_FUNCTION(W1_MW_DXFR_r4, W1_MW_DXFR_r3, W1_MW_DXFR_r1, W1_MW_DXFR_r2);


--W1_MR_LPXFR_r1 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MR_LPXFR_r1
--operation mode is normal

W1_MR_LPXFR_r1 = AMPP_FUNCTION(W1L492, A1L744, W1_MR_LPXFR_lc2, pci_rstn, GLOBAL(pci_clk), W1_$00253);


--W1_no_op_reg[1] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|no_op_reg[1]
--operation mode is normal

W1_no_op_reg[1] = AMPP_FUNCTION(pci_rstn, GLOBAL(pci_clk));


--W1L74 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00230~0
--operation mode is normal

W1L74 = AMPP_FUNCTION(A1L034, W1_no_op_reg[1]);


--W1L97 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|_~249
--operation mode is normal

W1L97 = AMPP_FUNCTION(W1_MS_DXFR, W1_devsel_toR);


--W1L03 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00170~10
--operation mode is normal

W1L03 = AMPP_FUNCTION(W1_irdy_or_lc[3], W1_irdy_or_lc[1], W1_irdy_or_lc[2], W1L97);


--W1_ms_dxfr_lc1c is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|ms_dxfr_lc1c
--operation mode is normal

W1_ms_dxfr_lc1c = AMPP_FUNCTION(W1_MS_DXFR, W1_irdy_or_not, W1_frame_or_not, W1_mstr_abrt);


--W1_ms_dxfr_lc1a is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|ms_dxfr_lc1a
--operation mode is normal

W1_ms_dxfr_lc1a = AMPP_FUNCTION(W1_MS_ADR2, W1_MS_ADR, W1_dac_cyc_reg);


--W1_ms_dxfr_lc1b is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|ms_dxfr_lc1b
--operation mode is normal

W1_ms_dxfr_lc1b = AMPP_FUNCTION(W1_irdy_or_not, W1_MS_DXFR, W1_frame_or_not);


--U1_high_ad_IR_data[31] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_IR_data[31]
--operation mode is normal

U1_high_ad_IR_data[31] = AMPP_FUNCTION(U1_ad_IR_ce_data, W1_ad_oer, U1_high_ad_or[63], Z1_adoe, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_IR_data[30] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_IR_data[30]
--operation mode is normal

U1_high_ad_IR_data[30] = AMPP_FUNCTION(U1_ad_IR_ce_data, W1_ad_oer, U1_high_ad_or[62], Z1_adoe, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_IR_data[29] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_IR_data[29]
--operation mode is normal

U1_high_ad_IR_data[29] = AMPP_FUNCTION(U1_ad_IR_ce_data, W1_ad_oer, U1_high_ad_or[61], Z1_adoe, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_IR_data[28] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_IR_data[28]
--operation mode is normal

U1_high_ad_IR_data[28] = AMPP_FUNCTION(U1_ad_IR_ce_data, W1_ad_oer, U1_high_ad_or[60], Z1_adoe, pci_rstn, GLOBAL(pci_clk));


--X1_xxh[7] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pk:parity_Chk|xxh[7]
--operation mode is normal

X1_xxh[7] = AMPP_FUNCTION(U1_high_ad_IR_data[31], U1_high_ad_IR_data[30], U1_high_ad_IR_data[29], U1_high_ad_IR_data[28]);


--U1_high_ad_IR_data[27] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_IR_data[27]
--operation mode is normal

U1_high_ad_IR_data[27] = AMPP_FUNCTION(U1_ad_IR_ce_data, W1_ad_oer, U1_high_ad_or[59], Z1_adoe, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_IR_data[26] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_IR_data[26]
--operation mode is normal

U1_high_ad_IR_data[26] = AMPP_FUNCTION(U1_ad_IR_ce_data, W1_ad_oer, U1_high_ad_or[58], Z1_adoe, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_IR_data[25] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_IR_data[25]
--operation mode is normal

U1_high_ad_IR_data[25] = AMPP_FUNCTION(U1_ad_IR_ce_data, W1_ad_oer, U1_high_ad_or[57], Z1_adoe, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_IR_data[24] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_IR_data[24]
--operation mode is normal

U1_high_ad_IR_data[24] = AMPP_FUNCTION(U1_ad_IR_ce_data, W1_ad_oer, U1_high_ad_or[56], Z1_adoe, pci_rstn, GLOBAL(pci_clk));


--X1_xxh[6] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pk:parity_Chk|xxh[6]
--operation mode is normal

X1_xxh[6] = AMPP_FUNCTION(U1_high_ad_IR_data[27], U1_high_ad_IR_data[26], U1_high_ad_IR_data[25], U1_high_ad_IR_data[24]);


--U1_high_ad_IR_data[23] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_IR_data[23]
--operation mode is normal

U1_high_ad_IR_data[23] = AMPP_FUNCTION(U1_ad_IR_ce_data, W1_ad_oer, U1_high_ad_or[55], Z1_adoe, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_IR_data[22] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_IR_data[22]
--operation mode is normal

U1_high_ad_IR_data[22] = AMPP_FUNCTION(U1_ad_IR_ce_data, W1_ad_oer, U1_high_ad_or[54], Z1_adoe, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_IR_data[21] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_IR_data[21]
--operation mode is normal

U1_high_ad_IR_data[21] = AMPP_FUNCTION(U1_ad_IR_ce_data, W1_ad_oer, U1_high_ad_or[53], Z1_adoe, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_IR_data[20] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_IR_data[20]
--operation mode is normal

U1_high_ad_IR_data[20] = AMPP_FUNCTION(U1_ad_IR_ce_data, W1_ad_oer, U1_high_ad_or[52], Z1_adoe, pci_rstn, GLOBAL(pci_clk));


--X1_xxh[5] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pk:parity_Chk|xxh[5]
--operation mode is normal

X1_xxh[5] = AMPP_FUNCTION(U1_high_ad_IR_data[23], U1_high_ad_IR_data[22], U1_high_ad_IR_data[21], U1_high_ad_IR_data[20]);


--U1_high_ad_IR_data[19] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_IR_data[19]
--operation mode is normal

U1_high_ad_IR_data[19] = AMPP_FUNCTION(U1_ad_IR_ce_data, W1_ad_oer, U1_high_ad_or[51], Z1_adoe, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_IR_data[18] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_IR_data[18]
--operation mode is normal

U1_high_ad_IR_data[18] = AMPP_FUNCTION(U1_ad_IR_ce_data, W1_ad_oer, U1_high_ad_or[50], Z1_adoe, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_IR_data[17] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_IR_data[17]
--operation mode is normal

U1_high_ad_IR_data[17] = AMPP_FUNCTION(U1_ad_IR_ce_data, W1_ad_oer, U1_high_ad_or[49], Z1_adoe, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_IR_data[16] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_IR_data[16]
--operation mode is normal

U1_high_ad_IR_data[16] = AMPP_FUNCTION(U1_ad_IR_ce_data, W1_ad_oer, U1_high_ad_or[48], Z1_adoe, pci_rstn, GLOBAL(pci_clk));


--X1_xxh[4] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pk:parity_Chk|xxh[4]
--operation mode is normal

X1_xxh[4] = AMPP_FUNCTION(U1_high_ad_IR_data[19], U1_high_ad_IR_data[18], U1_high_ad_IR_data[17], U1_high_ad_IR_data[16]);


--U1_high_ad_IR_data[15] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_IR_data[15]
--operation mode is normal

U1_high_ad_IR_data[15] = AMPP_FUNCTION(U1_ad_IR_ce_data, W1_ad_oer, U1_high_ad_or[47], Z1_adoe, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_IR_data[14] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_IR_data[14]
--operation mode is normal

U1_high_ad_IR_data[14] = AMPP_FUNCTION(U1_ad_IR_ce_data, W1_ad_oer, U1_high_ad_or[46], Z1_adoe, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_IR_data[13] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_IR_data[13]
--operation mode is normal

U1_high_ad_IR_data[13] = AMPP_FUNCTION(U1_ad_IR_ce_data, W1_ad_oer, U1_high_ad_or[45], Z1_adoe, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_IR_data[12] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_IR_data[12]
--operation mode is normal

U1_high_ad_IR_data[12] = AMPP_FUNCTION(U1_ad_IR_ce_data, W1_ad_oer, U1_high_ad_or[44], Z1_adoe, pci_rstn, GLOBAL(pci_clk));


--X1_xxh[3] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pk:parity_Chk|xxh[3]
--operation mode is normal

X1_xxh[3] = AMPP_FUNCTION(U1_high_ad_IR_data[15], U1_high_ad_IR_data[14], U1_high_ad_IR_data[13], U1_high_ad_IR_data[12]);


--U1_high_ad_IR_data[9] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_IR_data[9]
--operation mode is normal

U1_high_ad_IR_data[9] = AMPP_FUNCTION(U1_ad_IR_ce_data, W1_ad_oer, U1_high_ad_or[41], Z1_adoe, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_IR_data[11] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_IR_data[11]
--operation mode is normal

U1_high_ad_IR_data[11] = AMPP_FUNCTION(U1_ad_IR_ce_data, W1_ad_oer, U1_high_ad_or[43], Z1_adoe, pci_rstn, GLOBAL(pci_clk));


--U1_high_ad_IR_data[10] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_ad_IR_data[10]
--operation mode is normal

U1_high_ad_IR_data[10] = AMPP_FUNCTION(U1_ad_IR_ce_data, W1_ad_oer, U1_high_ad_or[42], Z1_adoe, pci_rstn, GLOBAL(pci_clk));


--X1_xxh[2] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pk:parity_Chk|xxh[2]
--operation mode is normal

X1_xxh[2] = AMPP_FUNCTION(U1_high_ad_IR_data[8], U1_high_ad_IR_data[9], U1_high_ad_IR_data[11], U1_high_ad_IR_data[10]);


--X1_xxh[1] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pk:parity_Chk|xxh[1]
--operation mode is normal

X1_xxh[1] = AMPP_FUNCTION(U1_high_ad_IR_data[7], U1_high_ad_IR_data[6], U1_high_ad_IR_data[5], U1_high_ad_IR_data[4]);


--X1_xxh[0] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pk:parity_Chk|xxh[0]
--operation mode is normal

X1_xxh[0] = AMPP_FUNCTION(U1_high_ad_IR_data[3], U1_high_ad_IR_data[2], U1_high_ad_IR_data[1], U1_high_ad_IR_data[0]);


--Z1_req64_R is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|req64_R
--operation mode is normal

Z1_req64_R = AMPP_FUNCTION(W1_cbe_oer_not, W1_req64_or_not, pci_rstn, GLOBAL(pci_clk));


--Z1_trans64_reg_set is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|trans64_reg_set
--operation mode is normal

Z1_trans64_reg_set = AMPP_FUNCTION(Z1_adr_phase_lc1, Z1_req64_R);


--Z1_trans64_reg_rst_lc1 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|trans64_reg_rst_lc1
--operation mode is normal

Z1_trans64_reg_rst_lc1 = AMPP_FUNCTION(W1_tabrt_set, Z1_lw_lr_done, Z1_TS_DISC, Z1_TS_IDLE_NOT);


--Z1_trans64_reg_rst_lc2 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|trans64_reg_rst_lc2
--operation mode is normal

Z1_trans64_reg_rst_lc2 = AMPP_FUNCTION(X1_serr_or, W1_$00070, W1_mstr_actv_lc, W1_lm_ack_or);


--Z1_no_op_reg[12] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|no_op_reg[12]
--operation mode is normal

Z1_no_op_reg[12] = AMPP_FUNCTION(pci_rstn, GLOBAL(pci_clk));


--Z1L51 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|$00162~0
--operation mode is normal

Z1L51 = AMPP_FUNCTION(Z1_no_op_reg[12], Z1_TS_IDLE_NOT, A1L734);


--U1_low_ad_IR_data[28] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_IR_data[28]
--operation mode is normal

U1_low_ad_IR_data[28] = AMPP_FUNCTION(U1_ad_IR_ce_data, pci_ad_28, pci_rstn, GLOBAL(pci_clk));


--U1_low_ad_IR_data[29] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_IR_data[29]
--operation mode is normal

U1_low_ad_IR_data[29] = AMPP_FUNCTION(U1_ad_IR_ce_data, pci_ad_29, pci_rstn, GLOBAL(pci_clk));


--U1_low_ad_IR_data[30] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_IR_data[30]
--operation mode is normal

U1_low_ad_IR_data[30] = AMPP_FUNCTION(U1_ad_IR_ce_data, pci_ad_30, pci_rstn, GLOBAL(pci_clk));


--U1_low_ad_IR_data[31] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_IR_data[31]
--operation mode is normal

U1_low_ad_IR_data[31] = AMPP_FUNCTION(U1_ad_IR_ce_data, pci_ad_31, pci_rstn, GLOBAL(pci_clk));


--X1_xxl[7] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pk:parity_Chk|xxl[7]
--operation mode is normal

X1_xxl[7] = AMPP_FUNCTION(U1_low_ad_IR_data[28], U1_low_ad_IR_data[29], U1_low_ad_IR_data[30], U1_low_ad_IR_data[31]);


--U1_low_ad_IR_data[24] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_IR_data[24]
--operation mode is normal

U1_low_ad_IR_data[24] = AMPP_FUNCTION(U1_ad_IR_ce_data, pci_ad_24, pci_rstn, GLOBAL(pci_clk));


--U1_low_ad_IR_data[25] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_IR_data[25]
--operation mode is normal

U1_low_ad_IR_data[25] = AMPP_FUNCTION(U1_ad_IR_ce_data, pci_ad_25, pci_rstn, GLOBAL(pci_clk));


--U1_low_ad_IR_data[26] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_IR_data[26]
--operation mode is normal

U1_low_ad_IR_data[26] = AMPP_FUNCTION(U1_ad_IR_ce_data, pci_ad_26, pci_rstn, GLOBAL(pci_clk));


--U1_low_ad_IR_data[27] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_IR_data[27]
--operation mode is normal

U1_low_ad_IR_data[27] = AMPP_FUNCTION(U1_ad_IR_ce_data, pci_ad_27, pci_rstn, GLOBAL(pci_clk));


--X1_xxl[6] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pk:parity_Chk|xxl[6]
--operation mode is normal

X1_xxl[6] = AMPP_FUNCTION(U1_low_ad_IR_data[24], U1_low_ad_IR_data[25], U1_low_ad_IR_data[26], U1_low_ad_IR_data[27]);


--U1_low_ad_IR_data[20] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_IR_data[20]
--operation mode is normal

U1_low_ad_IR_data[20] = AMPP_FUNCTION(U1_ad_IR_ce_data, pci_ad_20, pci_rstn, GLOBAL(pci_clk));


--U1_low_ad_IR_data[21] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_IR_data[21]
--operation mode is normal

U1_low_ad_IR_data[21] = AMPP_FUNCTION(U1_ad_IR_ce_data, pci_ad_21, pci_rstn, GLOBAL(pci_clk));


--U1_low_ad_IR_data[22] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_IR_data[22]
--operation mode is normal

U1_low_ad_IR_data[22] = AMPP_FUNCTION(U1_ad_IR_ce_data, pci_ad_22, pci_rstn, GLOBAL(pci_clk));


--U1_low_ad_IR_data[23] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_IR_data[23]
--operation mode is normal

U1_low_ad_IR_data[23] = AMPP_FUNCTION(U1_ad_IR_ce_data, pci_ad_23, pci_rstn, GLOBAL(pci_clk));


--X1_xxl[5] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pk:parity_Chk|xxl[5]
--operation mode is normal

X1_xxl[5] = AMPP_FUNCTION(U1_low_ad_IR_data[20], U1_low_ad_IR_data[21], U1_low_ad_IR_data[22], U1_low_ad_IR_data[23]);


--U1_low_ad_IR_data[19] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_IR_data[19]
--operation mode is normal

U1_low_ad_IR_data[19] = AMPP_FUNCTION(U1_ad_IR_ce_data, pci_ad_19, pci_rstn, GLOBAL(pci_clk));


--U1_low_ad_IR_data[18] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_IR_data[18]
--operation mode is normal

U1_low_ad_IR_data[18] = AMPP_FUNCTION(U1_ad_IR_ce_data, pci_ad_18, pci_rstn, GLOBAL(pci_clk));


--U1_low_ad_IR_data[17] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_IR_data[17]
--operation mode is normal

U1_low_ad_IR_data[17] = AMPP_FUNCTION(U1_ad_IR_ce_data, pci_ad_17, pci_rstn, GLOBAL(pci_clk));


--U1_low_ad_IR_data[16] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_IR_data[16]
--operation mode is normal

U1_low_ad_IR_data[16] = AMPP_FUNCTION(U1_ad_IR_ce_data, pci_ad_16, pci_rstn, GLOBAL(pci_clk));


--X1_xxl[4] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pk:parity_Chk|xxl[4]
--operation mode is normal

X1_xxl[4] = AMPP_FUNCTION(U1_low_ad_IR_data[19], U1_low_ad_IR_data[18], U1_low_ad_IR_data[17], U1_low_ad_IR_data[16]);


--U1_low_ad_IR_data[12] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_IR_data[12]
--operation mode is normal

U1_low_ad_IR_data[12] = AMPP_FUNCTION(U1_ad_IR_ce_data, pci_ad_12, pci_rstn, GLOBAL(pci_clk));


--U1_low_ad_IR_data[13] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_IR_data[13]
--operation mode is normal

U1_low_ad_IR_data[13] = AMPP_FUNCTION(U1_ad_IR_ce_data, pci_ad_13, pci_rstn, GLOBAL(pci_clk));


--U1_low_ad_IR_data[14] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_IR_data[14]
--operation mode is normal

U1_low_ad_IR_data[14] = AMPP_FUNCTION(U1_ad_IR_ce_data, pci_ad_14, pci_rstn, GLOBAL(pci_clk));


--U1_low_ad_IR_data[15] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_IR_data[15]
--operation mode is normal

U1_low_ad_IR_data[15] = AMPP_FUNCTION(U1_ad_IR_ce_data, pci_ad_15, pci_rstn, GLOBAL(pci_clk));


--X1_xxl[3] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pk:parity_Chk|xxl[3]
--operation mode is normal

X1_xxl[3] = AMPP_FUNCTION(U1_low_ad_IR_data[12], U1_low_ad_IR_data[13], U1_low_ad_IR_data[14], U1_low_ad_IR_data[15]);


--U1_low_ad_IR_data[11] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_IR_data[11]
--operation mode is normal

U1_low_ad_IR_data[11] = AMPP_FUNCTION(U1_ad_IR_ce_data, pci_ad_11, pci_rstn, GLOBAL(pci_clk));


--U1_low_ad_IR_data[10] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_ad_IR_data[10]
--operation mode is normal

U1_low_ad_IR_data[10] = AMPP_FUNCTION(U1_ad_IR_ce_data, pci_ad_10, pci_rstn, GLOBAL(pci_clk));


--X1_xxl[2] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pk:parity_Chk|xxl[2]
--operation mode is normal

X1_xxl[2] = AMPP_FUNCTION(U1_low_ad_IR_data[8], U1_low_ad_IR_data[9], U1_low_ad_IR_data[11], U1_low_ad_IR_data[10]);


--X1_xxl[1] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pk:parity_Chk|xxl[1]
--operation mode is normal

X1_xxl[1] = AMPP_FUNCTION(U1_low_ad_IR_data[7], U1_low_ad_IR_data[6], U1_low_ad_IR_data[5], U1_low_ad_IR_data[4]);


--X1_xxl[0] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pk:parity_Chk|xxl[0]
--operation mode is normal

X1_xxl[0] = AMPP_FUNCTION(U1_low_ad_IR_data[3], U1_low_ad_IR_data[2], U1_low_ad_IR_data[1], U1_low_ad_IR_data[0]);


--Z1_cfg_adr_dec_ena is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|cfg_adr_dec_ena
--operation mode is normal

Z1_cfg_adr_dec_ena = AMPP_FUNCTION(Z1_adr_phase_lc1, Z1_cfg_adr_dec_ena_lc2, Z1_cfg_adr_dec_ena_lc1);


--U1_mstr_cben_ir_ce_d is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|mstr_cben_ir_ce_d
--operation mode is normal

U1_mstr_cben_ir_ce_d = AMPP_FUNCTION(W1_MS_ENA, W1_MS_ADR, W1_MS_DXFR);


--Z1_$00184 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|$00184
--operation mode is normal

Z1_$00184 = AMPP_FUNCTION(Z1_TS_DISC, Z1_LR_DONE, Z1_LR_IDLE_NOT, Z1_trdy_OR_NOT);


--Z1L55 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|_~58
--operation mode is normal

Z1L55 = AMPP_FUNCTION(Z1_cfg_cyc, Z1_TS_ADR_CLMD, Z1_retry);


--Z1L91 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|$00180~10
--operation mode is normal

Z1L91 = AMPP_FUNCTION(Z1_TS_ADR_CLMD, Z1_trdy_OR_lc[4], Z1_retry, Z1L55);


--Z1L65 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|_~60
--operation mode is normal

Z1L65 = AMPP_FUNCTION(Z1_LR_WAIT, Z1L54, Z1_LR_WAIT_32);


--Z1_wait_wait32_lc[1] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|wait_wait32_lc[1]
--operation mode is normal

Z1_wait_wait32_lc[1] = AMPP_FUNCTION(Z1_lt_rdynR, Z1_LR_PXFR, Z1_TS_DISC);


--K3_cs22a[9] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_gray2bin_7qa:a_gray2bin12|cs22a[9]
--operation mode is arithmetic

K3_cs22a[9] = S3_dffe50a[9] $ K3L12;

--K3L02 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_gray2bin_7qa:a_gray2bin12|cs22a[9]~COUT
--operation mode is arithmetic

K3L02 = CARRY(S3_dffe50a[9] $ K3L12);


--K3_cs22a[8] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_gray2bin_7qa:a_gray2bin12|cs22a[8]
--operation mode is arithmetic

K3_cs22a[8] = S3_dffe50a[8] $ K3L02;

--K3L81 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_gray2bin_7qa:a_gray2bin12|cs22a[8]~COUT
--operation mode is arithmetic

K3L81 = CARRY(S3_dffe50a[8] $ K3L02);


--K3_cs22a[7] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_gray2bin_7qa:a_gray2bin12|cs22a[7]
--operation mode is arithmetic

K3_cs22a[7] = S3_dffe50a[7] $ K3L81;

--K3L61 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_gray2bin_7qa:a_gray2bin12|cs22a[7]~COUT
--operation mode is arithmetic

K3L61 = CARRY(S3_dffe50a[7] $ K3L81);


--K3_cs22a[6] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_gray2bin_7qa:a_gray2bin12|cs22a[6]
--operation mode is arithmetic

K3_cs22a[6] = S3_dffe50a[6] $ K3L61;

--K3L41 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_gray2bin_7qa:a_gray2bin12|cs22a[6]~COUT
--operation mode is arithmetic

K3L41 = CARRY(S3_dffe50a[6] $ K3L61);


--K3_cs22a[5] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_gray2bin_7qa:a_gray2bin12|cs22a[5]
--operation mode is arithmetic

K3_cs22a[5] = S3_dffe50a[5] $ K3L41;

--K3L21 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_gray2bin_7qa:a_gray2bin12|cs22a[5]~COUT
--operation mode is arithmetic

K3L21 = CARRY(S3_dffe50a[5] $ K3L41);


--K3_cs22a[4] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_gray2bin_7qa:a_gray2bin12|cs22a[4]
--operation mode is arithmetic

K3_cs22a[4] = S3_dffe50a[4] $ K3L21;

--K3L01 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_gray2bin_7qa:a_gray2bin12|cs22a[4]~COUT
--operation mode is arithmetic

K3L01 = CARRY(S3_dffe50a[4] $ K3L21);


--K3_cs22a[3] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_gray2bin_7qa:a_gray2bin12|cs22a[3]
--operation mode is arithmetic

K3_cs22a[3] = S3_dffe50a[3] $ K3L01;

--K3L8 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_gray2bin_7qa:a_gray2bin12|cs22a[3]~COUT
--operation mode is arithmetic

K3L8 = CARRY(S3_dffe50a[3] $ K3L01);


--K3_cs22a[1] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_gray2bin_7qa:a_gray2bin12|cs22a[1]
--operation mode is arithmetic

K3_cs22a[1] = S3_dffe50a[1] $ K3L6;

--K3L4 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_gray2bin_7qa:a_gray2bin12|cs22a[1]~COUT
--operation mode is arithmetic

K3L4 = CARRY(S3_dffe50a[1] $ K3L6);


--K3_cs22a[2] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_gray2bin_7qa:a_gray2bin12|cs22a[2]
--operation mode is arithmetic

K3_cs22a[2] = S3_dffe50a[2] $ K3L8;

--K3L6 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_gray2bin_7qa:a_gray2bin12|cs22a[2]~COUT
--operation mode is arithmetic

K3L6 = CARRY(S3_dffe50a[2] $ K3L8);


--U1_high_data_out_HR_ena is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|high_data_out_HR_ena
--operation mode is normal

U1_high_data_out_HR_ena = AMPP_FUNCTION(W1_MS_ENA, W1_dati_hr_ena_lc, Z1_TS_IDLE_NOT, Z1_dati_hr_ena_lc);


--W1_DXFR_write_lc3 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|DXFR_write_lc3
--operation mode is normal

W1_DXFR_write_lc3 = AMPP_FUNCTION(W1_wr_rdn, W1_DXFR_write_lc1, W1_DXFR_write_lc2);


--W1_DXFR_write_lc4 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|DXFR_write_lc4
--operation mode is normal

W1_DXFR_write_lc4 = AMPP_FUNCTION(W1_wr_rdn, W1_DXFR_write_lc4a);


--Z1L66 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|_~186
--operation mode is normal

Z1L66 = AMPP_FUNCTION(Z1L911, Z1_trans64_R);


--Z1L81 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|$00169~10
--operation mode is normal

Z1L81 = AMPP_FUNCTION(Z1_TS_ADR_VLD, Z1_trans64_R, X1_serr_or, Z1L66);


--Z1_lt_hdata_ack_r_prn[2] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_hdata_ack_r_prn[2]
--operation mode is normal

Z1_lt_hdata_ack_r_prn[2] = AMPP_FUNCTION(Z1_lt_hdata_ack_r_prn[1], Z1L27, Z1_mem_cyc, Z1_retry);


--W1_devsel_toR_lc1 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|devsel_toR_lc1
--operation mode is normal

W1_devsel_toR_lc1 = AMPP_FUNCTION(E9_q[0], E9_q[2], W1_dac_cyc_reg, E9_q[1]);


--dpm_dec_reg_tmp2 is dpm_dec_reg_tmp2
--operation mode is normal

dpm_dec_reg_tmp2_lut_out = dpm_dec_reg_tmp1;
dpm_dec_reg_tmp2 = DFFEA(dpm_dec_reg_tmp2_lut_out, GLOBAL(pci_clk), pci_rstn, , , , );


--Z1_retry_set_lc is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|retry_set_lc
--operation mode is normal

Z1_retry_set_lc = AMPP_FUNCTION(Z1_cfg_cyc, Z1_adr_phase_lc1, Z1_TS_IDLE_NOT);


--Z1_io_cyc_s_lc is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|io_cyc_s_lc
--operation mode is normal

Z1_io_cyc_s_lc = AMPP_FUNCTION(U1_cben_ir_address[1], U1_cben_ir_address[3], U1_cben_ir_address[2]);


--Z1_LW_DONE_lc[1] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|LW_DONE_lc[1]
--operation mode is normal

Z1_LW_DONE_lc[1] = AMPP_FUNCTION(Z1_TS_DISC, dpm_dec_reg_LT_RDY_n_pci);


--W1_no_op_reg[7] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|no_op_reg[7]
--operation mode is normal

W1_no_op_reg[7] = AMPP_FUNCTION(pci_rstn, GLOBAL(pci_clk));


--Z1L25 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|$00244~0
--operation mode is normal

Z1L25 = AMPP_FUNCTION(Z1_no_op_reg[1], A1L734, A1L234);


--Z1L06 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|_~99
--operation mode is normal

Z1L06 = AMPP_FUNCTION(A1L734, A1L234);


--W1_MW_WAIT is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MW_WAIT
--operation mode is normal

W1_MW_WAIT = AMPP_FUNCTION(A1L744, W1_no_op_reg[2], W1L824, W1_MW_WAIT_lc[2], pci_rstn, GLOBAL(pci_clk), W1L44);


--W1_MW_END_lc1 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MW_END_lc1
--operation mode is normal

W1_MW_END_lc1 = AMPP_FUNCTION(W1_MW_LAST, W1_MW_DXFR, W1_MW_WAIT);


--Z1_LR_PXFR_lc[3] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|LR_PXFR_lc[3]
--operation mode is normal

Z1_LR_PXFR_lc[3] = AMPP_FUNCTION(Z1_direct_xfr, Z1_lt_rdynR, Z1_LR_PXFR, Z1_TS_DISC);


--Z1L63 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|$00220~0
--operation mode is normal

Z1L63 = AMPP_FUNCTION(Z1_TS_DISC, Z1_LR_LXFR_lc[1], Z1_lt_rdynR, Z1_direct_xfr);


--Z1L62 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|$00206~0
--operation mode is normal

Z1L62 = AMPP_FUNCTION(Z1_TS_ADR_CLMD, W1_mstr_actv_lc, Z1_LW_IDLE_NOT, Z1_retry);


--Z1_LW_LXFR_lc[3] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|LW_LXFR_lc[3]
--operation mode is normal

Z1_LW_LXFR_lc[3] = AMPP_FUNCTION(dpm_dec_reg_LT_RDY_n_pci, Z1_LW_WAIT, Z1_TS_DXFR);


--Z1L16 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|_~143
--operation mode is normal

Z1L16 = AMPP_FUNCTION(Z1_TS_DISC, Z1_low_dword_discard);


--Z1L42 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|$00199~10
--operation mode is normal

Z1L42 = AMPP_FUNCTION(Z1_TS_ADR_CLMD, W1_mstr_actv_lc, Z1_retry, Z1_cfg_cyc, Z1L16);


--GB11_aeb_out is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|lpm_compare:bar0_comp|comptree:comparator|cmpchain:cmp_end|comptree:comp|cmpchain:cmp[0]|aeb_out
--operation mode is normal

GB11_aeb_out = AMPP_FUNCTION(U1_ad_ir_address[28], BB1_bar0_reg[28], U1_ad_ir_address[29], BB1_bar0_reg[29]);


--GB21_aeb_out is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|lpm_compare:bar0_comp|comptree:comparator|cmpchain:cmp_end|comptree:comp|cmpchain:cmp[1]|aeb_out
--operation mode is normal

GB21_aeb_out = AMPP_FUNCTION(U1_ad_ir_address[30], BB1_bar0_reg[30], U1_ad_ir_address[31], BB1_bar0_reg[31]);


--GB8_aeb_out is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|lpm_compare:bar0_comp|comptree:comparator|cmpchain:cmp[0]|comptree:comp|cmpchain:cmp[3]|aeb_out
--operation mode is normal

GB8_aeb_out = AMPP_FUNCTION(U1_ad_ir_address[26], BB1_bar0_reg[26], U1_ad_ir_address[27], BB1_bar0_reg[27]);


--GB7_aeb_out is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|lpm_compare:bar0_comp|comptree:comparator|cmpchain:cmp[0]|comptree:comp|cmpchain:cmp[2]|aeb_out
--operation mode is normal

GB7_aeb_out = AMPP_FUNCTION(U1_ad_ir_address[24], BB1_bar0_reg[24], U1_ad_ir_address[25], BB1_bar0_reg[25]);


--GB5_aeb_out is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|lpm_compare:bar0_comp|comptree:comparator|cmpchain:cmp[0]|comptree:comp|cmpchain:cmp[0]|aeb_out
--operation mode is normal

GB5_aeb_out = AMPP_FUNCTION(U1_ad_ir_address[20], BB1_bar0_reg[20], U1_ad_ir_address[21], BB1_bar0_reg[21]);


--GB6_aeb_out is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|lpm_compare:bar0_comp|comptree:comparator|cmpchain:cmp[0]|comptree:comp|cmpchain:cmp[1]|aeb_out
--operation mode is normal

GB6_aeb_out = AMPP_FUNCTION(U1_ad_ir_address[22], BB1_bar0_reg[22], U1_ad_ir_address[23], BB1_bar0_reg[23]);


--A1L94 is dpm_ni2f_modgen_eq_100_ix34_lc~0
--operation mode is normal

A1L94 = (!dpm_ni2f_reg_cdata_3 & !dpm_ni2f_reg_cdata_2 & !dpm_ni2f_reg_cdata_1 & !dpm_ni2f_reg_cdata_0) & CASCADE(A1L84);


--W1_WAIT_ndirect_lc is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|WAIT_ndirect_lc
--operation mode is normal

W1_WAIT_ndirect_lc = AMPP_FUNCTION(W1_MW_WAIT, W1_MW_DXFR_32, W1_devsel_toR, W1_lm_rdynR);


--Z1_wait_wait32_lc[4] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|wait_wait32_lc[4]
--operation mode is normal

Z1_wait_wait32_lc[4] = AMPP_FUNCTION(Z1_wait_wait32_lc[2], Z1_wait_wait32_lc[3], Z1_cfg_cyc);


--W1_WAIT_WAIT32_lc3 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|WAIT_WAIT32_lc3
--operation mode is normal

W1_WAIT_WAIT32_lc3 = AMPP_FUNCTION(W1_MW_WAIT_32_d_lc_1c, W1_WAIT_WAIT32_lc1, W1_WAIT_WAIT32_lc2);


--W1_MW_WAIT_32_d_lc_1d is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MW_WAIT_32_d_lc_1d
--operation mode is normal

W1_MW_WAIT_32_d_lc_1d = AMPP_FUNCTION(W1_MW_WAIT_32_d_lc_1a, W1_MW_WAIT, W1_direct_xfr, W1_devsel_toR);


--W1_no_op_reg[2] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|no_op_reg[2]
--operation mode is normal

W1_no_op_reg[2] = AMPP_FUNCTION(pci_rstn, GLOBAL(pci_clk));


--W1L64 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00226~0
--operation mode is normal

W1L64 = AMPP_FUNCTION(A1L944, W1_no_op_reg[2]);


--W1_MW_LAST_lc[3] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MW_LAST_lc[3]
--operation mode is normal

W1_MW_LAST_lc[3] = AMPP_FUNCTION(W1_MW_LXFR, W1_lm_rdynR, W1_devsel_toR);


--W1L2 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00060~3
--operation mode is arithmetic

W1L2 = AMPP_FUNCTION(A1L944, W1_no_op_reg[2]);

--W1_$00060 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00060
--operation mode is arithmetic

W1_$00060 = AMPP_FUNCTION(A1L944, W1_no_op_reg[2]);


--BB1L28 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|latency_cache_ena[0]~49
--operation mode is normal

BB1L28 = AMPP_FUNCTION(Z1_cfg_dat_vld, DB1_decR[3], U1_low_cben_IR_data[0]);


--W1_ADOR_ena_lc is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|ADOR_ena_lc
--operation mode is normal

W1_ADOR_ena_lc = AMPP_FUNCTION(W1_MS_ENA, W1_MS_ADR2, W1_dac_cyc_strobe);


--U1L132 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|l_dato[41]~59
--operation mode is normal

U1L132 = AMPP_FUNCTION(U1_high_ad_IR_data[9], U1_low_ad_IR_data[9], U1_local_dat_sel);


--BB1L38 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|latency_cache_ena[1]~50
--operation mode is normal

BB1L38 = AMPP_FUNCTION(Z1_cfg_dat_vld, DB1_decR[3], U1_low_cben_IR_data[1]);


--BB1L83 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|bar0_ena[2]~49
--operation mode is normal

BB1L83 = AMPP_FUNCTION(Z1_cfg_dat_vld, DB1_decR[4], U1_low_cben_IR_data[2]);


--BB1L93 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|bar0_ena[3]~50
--operation mode is normal

BB1L93 = AMPP_FUNCTION(Z1_cfg_dat_vld, DB1_decR[4], U1_low_cben_IR_data[3]);


--W1_perr_rep_setR is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|perr_rep_setR
--operation mode is normal

W1_perr_rep_setR = AMPP_FUNCTION(W1_MS_TAR_R, W1_MS_DXFR, W1_MS_TAR, A1L244, pci_rstn, GLOBAL(pci_clk));


--ix2019_lc is ix2019_lc
--operation mode is normal

ix2019_lc = !dpm_ni2f_reg_sm_11 & !dpm_ni2f_reg_sm_10 & !dpm_ni2f_reg_sm_9 & !dpm_ni2f_reg_sm_8;


--ix2020_lc is ix2020_lc
--operation mode is normal

ix2020_lc = !dpm_ni2f_reg_sm_3 & !dpm_ni2f_reg_sm_2 & !dpm_ni2f_reg_sm_1 & dpm_ni2f_reg_sm_0;


--ix2016_lc is ix2016_lc
--operation mode is normal

ix2016_lc = !dpm_ni2f_reg_sm_7 & !dpm_ni2f_reg_sm_6 & !dpm_ni2f_reg_sm_5 & !dpm_ni2f_reg_sm_4;


--X1_perr_det_setR_r2 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pk:parity_Chk|perr_det_setR_r2
--operation mode is normal

X1_perr_det_setR_r2 = AMPP_FUNCTION(X1_$00005, U1_par_oeR, U1_par64_or, X1_xxh[11], pci_rstn, GLOBAL(pci_clk));


--X1_perr_det_setR_r3 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pk:parity_Chk|perr_det_setR_r3
--operation mode is normal

X1_perr_det_setR_r3 = AMPP_FUNCTION(U1_trg_serr_vld, A1L044, X1_xxlad[11], pci_rstn, GLOBAL(pci_clk));


--X1_perr_det_setR_r1 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pk:parity_Chk|perr_det_setR_r1
--operation mode is normal

X1_perr_det_setR_r1 = AMPP_FUNCTION(W1_perr_vldR, Z1_perr_vldR, A1L044, X1_xxl[11], pci_rstn, GLOBAL(pci_clk));


--AB01L2 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|pcimt64_sr:$00216|REG~17
--operation mode is normal

AB01L2 = AMPP_FUNCTION(X1_perr_det_setR_r3, X1_perr_det_setR_r1);


--Z1L32 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|$00195~0
--operation mode is normal

Z1L32 = AMPP_FUNCTION(Z1_TS_ADR_CLMD, Z1_cfg_cyc, Z1_retry, W1_mstr_actv_lc);


--Z1L773 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|TS_DXFR_d_lc[1]~45
--operation mode is normal

Z1L773 = AMPP_FUNCTION(Z1_cfg_cyc, dpm_dec_reg_LT_RDY_n_pci, Z1L32);


--W1_latcntr_toR is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|latcntr_toR
--operation mode is normal

W1_latcntr_toR = AMPP_FUNCTION(W1_latcntr_toR_lc1, W1_latcntr_toR_lc2, W1_latcntr_toR, pci_rstn, GLOBAL(pci_clk), W1_$00064);


--W1_MW_WAIT_32_r[2] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MW_WAIT_32_r[2]
--operation mode is normal

W1_MW_WAIT_32_r[2] = AMPP_FUNCTION(A1L744, W1_MW_WAIT_32_lc[2], W1_last_xfr, W1_MW_WAIT_32_lc[3], pci_rstn, GLOBAL(pci_clk), W1L17);


--W1_MW_WAIT_32_r[1] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MW_WAIT_32_r[1]
--operation mode is normal

W1_MW_WAIT_32_r[1] = AMPP_FUNCTION(A1L744, W1_MW_WAIT_32_lc[1], W1_MW_WAIT, W1_direct_xfr, pci_rstn, GLOBAL(pci_clk), W1L15);


--W1_MW_WAIT_32 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MW_WAIT_32
--operation mode is normal

W1_MW_WAIT_32 = AMPP_FUNCTION(W1_MW_WAIT_32_r[2], W1_MW_WAIT_32_r[1]);


--W1_frame_or_lc3a is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|frame_or_lc3a
--operation mode is normal

W1_frame_or_lc3a = AMPP_FUNCTION(W1_MW_WAIT_32, W1_MW_DXFR_32, W1_last_xfr_lc1, W1_latcntr_toR);


--W1_frame_or_lc3b is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|frame_or_lc3b
--operation mode is normal

W1_frame_or_lc3b = AMPP_FUNCTION(W1_direct_xfr, W1_MW_WAIT, W1_MW_DXFR, W1_lm_rdynR);


--W1_frame_or_lc2a is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|frame_or_lc2a
--operation mode is normal

W1_frame_or_lc2a = AMPP_FUNCTION(W1_MS_DXFR, W1_wr_rdn, W1_MW_LXFR);


--W1_MW_HOLD_lc[2] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MW_HOLD_lc[2]
--operation mode is normal

W1_MW_HOLD_lc[2] = AMPP_FUNCTION(W1_MW_HOLD, W1_devsel_toR);


--W1_MW_HOLD_lc[1] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MW_HOLD_lc[1]
--operation mode is normal

W1_MW_HOLD_lc[1] = AMPP_FUNCTION(W1_MW_LXFR, W1_lm_rdynR, W1_devsel_toR, W1_direct_xfr);


--W1_MW_LXFR_lc[1] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MW_LXFR_lc[1]
--operation mode is normal

W1_MW_LXFR_lc[1] = AMPP_FUNCTION(W1_lm_rdynR, W1_MW_LXFR, W1_devsel_toR);


--W1_MW_LXFR_lc[2] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MW_LXFR_lc[2]
--operation mode is normal

W1_MW_LXFR_lc[2] = AMPP_FUNCTION(W1_lm_rdynR, W1_MW_DXFR, W1_devsel_toR);


--W1_adr_phase_end is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|adr_phase_end
--operation mode is normal

W1_adr_phase_end = AMPP_FUNCTION(W1_adr_phase_end_lc1, W1_MS_ENA, pci_gntn, W1_dac_cmd, pci_rstn, GLOBAL(pci_clk));


--W1_irdy_or_lc[3] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|irdy_or_lc[3]
--operation mode is normal

W1_irdy_or_lc[3] = AMPP_FUNCTION(W1_MW_DXFR_32, W1_adr_phase_end, W1_MR_IDLE_not, W1_wr_rdn);


--W1_irdy_or_lc[1] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|irdy_or_lc[1]
--operation mode is normal

W1_irdy_or_lc[1] = AMPP_FUNCTION(W1_MW_WAIT, W1_MW_WAIT_32, W1_MW_DXFR, W1_lm_rdynR);


--Y1_par[9] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pg:parity_gen|par[9]
--operation mode is normal

Y1_par[9] = AMPP_FUNCTION(Y1_par[7], Y1_par[6], Y1_par[5], Y1_par[4]);


--Y1_par[8] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pg:parity_gen|par[8]
--operation mode is normal

Y1_par[8] = AMPP_FUNCTION(Y1_par[3], Y1_par[2], Y1_par[1], Y1_par[0]);


--W1_req64_or_not is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|req64_or_not
--operation mode is normal

W1_req64_or_not = AMPP_FUNCTION(W1_req64_or_lc[3], W1_req64_or_lc[2], GND, pci_gntn, !pci_rstn, GLOBAL(pci_clk), W1L57);


--Z1_cfg_adr_dec_ena_lc1 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|cfg_adr_dec_ena_lc1
--operation mode is normal

Z1_cfg_adr_dec_ena_lc1 = AMPP_FUNCTION(Z1_idsel_IR, Z1_TS_IDLE_NOT, U1_ad_ir_address[1], U1_ad_ir_address[0]);


--Z1L75 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|_~65
--operation mode is normal

Z1L75 = AMPP_FUNCTION(Z1_TS_ADR_CLMD, Z1_cfg_cyc);


--Z1L023 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|stop_or_cc1~0
--operation mode is normal

Z1L023 = AMPP_FUNCTION(Z1_no_op_reg[1], Z1_LR_LXFR);


--Z1_burst_trans_r is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|burst_trans_r
--operation mode is normal

Z1_burst_trans_r = AMPP_FUNCTION(W1_mstr_actv_lc, Z1_TS_TURN_AR, Z1_TS_IDLE_NOT);


--Z1_trdy_OR_lc[4] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|trdy_OR_lc[4]
--operation mode is normal

Z1_trdy_OR_lc[4] = AMPP_FUNCTION(AB5_REG, dpm_dec_reg_LT_RDY_n_pci, W1_mstr_actv_lc, Z1_LW_IDLE_NOT);


--Z1L47 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|_~295
--operation mode is normal

Z1L47 = AMPP_FUNCTION(Z1_trdy_OR_lc[2], Z1_lt_ldata_ack_r, Z1_direct_xfr);


--Z1L953 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|trdy_OR_lc[3]~74
--operation mode is normal

Z1L953 = AMPP_FUNCTION(Z1_LR_LXFR, Z1_trdy_OR_lc[1], Z1L47);


--S3_dffe50a[0] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|alt_synch_pipe_cb3:alt_synch_pipe10|dffpipe_cb3:dffpipe47|dffe50a[0]
--operation mode is normal

S3_dffe50a[0]_lut_out = S3_dffe49a[0];
S3_dffe50a[0] = DFFEA(S3_dffe50a[0]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );


--K3L2 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|a_gray2bin_7qa:a_gray2bin12|cs22a[0]~19
--operation mode is normal

K3L2 = K3L4 $ S3_dffe50a[0];


--W1_dati_hr_ena_lc is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|dati_hr_ena_lc
--operation mode is normal

W1_dati_hr_ena_lc = AMPP_FUNCTION(W1_MS_DXFR, W1_MW_WAIT, W1_MW_WAIT_32_r[2], W1_MW_WAIT_32_r[1]);


--Z1_dati_hr_ena_lc is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|dati_hr_ena_lc
--operation mode is normal

Z1_dati_hr_ena_lc = AMPP_FUNCTION(Z1_LR_DONE, Z1_LR_PXFR, Z1_LR_LXFR, Z1L54);


--W1_DXFR_write_lc1 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|DXFR_write_lc1
--operation mode is normal

W1_DXFR_write_lc1 = AMPP_FUNCTION(W1_MS_DXFR, W1_irdy_or_not, W1_mstr_abrt, W1_frame_or_not);


--W1L742 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|lm_hdata_ack_lc[4]~101
--operation mode is normal

W1L742 = AMPP_FUNCTION(W1_lm_hdata_ack, W1_$00119, W1_direct_xfr, W1L252);


--W1L42 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00137~0
--operation mode is normal

W1L42 = AMPP_FUNCTION(W1_MR_END, W1_MR_LLXFR_r1, W1_MR_LLXFR_r2);


--W1L642 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|lm_hdata_ack_lc[3]~102
--operation mode is normal

W1L642 = AMPP_FUNCTION(W1_lm_hdata_ack, W1_MR_IDLE_not, W1_$00119, W1L42);


--W1_trdy_det is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|trdy_det
--operation mode is normal

W1_trdy_det = AMPP_FUNCTION(W1_no_op_reg[3], W1_trdy_det, W1_trdy_det_reset, pci_rstn, GLOBAL(pci_clk), W1_$00080);


--W1_disc1_det is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|disc1_det
--operation mode is normal

W1_disc1_det = AMPP_FUNCTION(W1_disc1_det_set, W1_MS_ENA, W1_MS_REQ, W1_disc1_det, pci_rstn, GLOBAL(pci_clk));


--W1_trdyR is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|trdyR
--operation mode is normal

W1_trdyR = AMPP_FUNCTION(W1_no_op_reg[1], pci_rstn, GLOBAL(pci_clk), W1_$00060);


--W1_disc0_det_set is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|disc0_det_set
--operation mode is normal

W1_disc0_det_set = AMPP_FUNCTION(W1_trdy_det, W1_retry_det_set1, W1_disc1_det, W1_trdyR);


--W1_retry_det_set2 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|retry_det_set2
--operation mode is normal

W1_retry_det_set2 = AMPP_FUNCTION(W1_retry_det_set1, W1_MS_DXFR, W1_MS_TAR, W1_trdy_det);


--W1_MR_LLWAIT_r1_lc1 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MR_LLWAIT_r1_lc1
--operation mode is normal

W1_MR_LLWAIT_r1_lc1 = AMPP_FUNCTION(W1_MR_PXFR, W1_devsel_toR);


--dpm_dec_reg_tmp1 is dpm_dec_reg_tmp1
--operation mode is normal

dpm_dec_reg_tmp1_lut_out = dpm_dec_reg_tmp;
dpm_dec_reg_tmp1 = DFFEA(dpm_dec_reg_tmp1_lut_out, GLOBAL(pci_clk), pci_rstn, , , , );


--W1_lm_ack_or_lc[8] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|lm_ack_or_lc[8]
--operation mode is normal

W1_lm_ack_or_lc[8] = AMPP_FUNCTION(W1_MR_LWAIT, W1_MR_LLWAIT_r1_lc2, W1_wr_rdn, W1_dac_cyc_strobe);


--W1_lm_ack_or_lc[9] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|lm_ack_or_lc[9]
--operation mode is normal

W1_lm_ack_or_lc[9] = AMPP_FUNCTION(W1_wr_rdn, W1_MW_IDLE_not);


--W1_lm_ack_or_lc[10] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|lm_ack_or_lc[10]
--operation mode is normal

W1_lm_ack_or_lc[10] = AMPP_FUNCTION(W1L512, W1_lm_ack_or_lc[7]);


--W1_lm_ack_or_lc[4] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|lm_ack_or_lc[4]
--operation mode is normal

W1_lm_ack_or_lc[4] = AMPP_FUNCTION(W1_MW_HOLD, W1_MW_LXFR, W1_last_xfr, W1_devsel_toR);


--W1L33 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00183~0
--operation mode is normal

W1L33 = AMPP_FUNCTION(W1_no_op_reg[3], W1L04, W1_no_op_reg[2]);


--W1L23 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00178~0
--operation mode is normal

W1L23 = AMPP_FUNCTION(A1L944, W1_lm_rdynR);


--Z1_LR_WAIT_lc[1] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|LR_WAIT_lc[1]
--operation mode is normal

Z1_LR_WAIT_lc[1] = AMPP_FUNCTION(Z1_LR_PXFR, Z1_TS_DISC);


--Z1_LR_PXFR_32_r1 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|LR_PXFR_32_r1
--operation mode is normal

Z1_LR_PXFR_32_r1 = AMPP_FUNCTION(Z1L851, pci_rstn, GLOBAL(pci_clk), Z1_$00230);


--Z1_LR_PXFR_32_r2 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|LR_PXFR_32_r2
--operation mode is normal

Z1_LR_PXFR_32_r2 = AMPP_FUNCTION(Z1_LR_WAIT_32, Z1_LR_PXFR_32_lc[2], pci_rstn, GLOBAL(pci_clk), Z1L64);


--Z1_LR_PXFR_32 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|LR_PXFR_32
--operation mode is normal

Z1_LR_PXFR_32 = AMPP_FUNCTION(Z1_LR_PXFR_32_r1, Z1_LR_PXFR_32_r2);


--Z1_LR_WAIT_32_lc1 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|LR_WAIT_32_lc1
--operation mode is normal

Z1_LR_WAIT_32_lc1 = AMPP_FUNCTION(Z1_lt_rdynR, Z1_LR_PXFR, Z1_direct_xfr, Z1_TS_DISC);


--Z1L361 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|LR_PXFR_cc1~1
--operation mode is normal

Z1L361 = AMPP_FUNCTION(Z1_TS_DISC, Z1_lt_rdynR, Z1_direct_xfr, Z1_LR_LXFR_lc[1]);


--Z1L73 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|$00223~0
--operation mode is normal

Z1L73 = AMPP_FUNCTION(Z1_TS_ADR_VLD, Z1_LR_IDLE_NOT, X1_serr_or, Z1_cfg_cyc);


--Z1_LR_LXFR_lc[2] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|LR_LXFR_lc[2]
--operation mode is normal

Z1_LR_LXFR_lc[2] = AMPP_FUNCTION(Z1_lt_ldata_ack_r, Z1_lt_rdynR, Z1_direct_xfr);


--A1L84 is dpm_ni2f_modgen_eq_100_ix30~0
--operation mode is normal

A1L84 = (!dpm_ni2f_reg_cdata_7 & !dpm_ni2f_reg_cdata_6 & !dpm_ni2f_reg_cdata_5 & !dpm_ni2f_reg_cdata_4) & CASCADE(A1L74);


--W1L05 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00236~0
--operation mode is normal

W1L05 = AMPP_FUNCTION(A1L944, W1_no_op_reg[1]);


--W1L94 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00235~0
--operation mode is normal

W1L94 = AMPP_FUNCTION(W1_no_op_reg[3], Z1_ack64_OR_not, Z1_targ_oeR_reg, A1L034);


--W1L84 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00232~0
--operation mode is normal

W1L84 = AMPP_FUNCTION(W1_no_op_reg[1], W1L2);


--Z1_wait_wait32_lc[2] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|wait_wait32_lc[2]
--operation mode is normal

Z1_wait_wait32_lc[2] = AMPP_FUNCTION(Z1_LR_WAIT, Z1_direct_xfr, Z1_wait_wait32_lc[1]);


--Z1_wait_wait32_lc[3] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|wait_wait32_lc[3]
--operation mode is normal

Z1_wait_wait32_lc[3] = AMPP_FUNCTION(Z1_LR_WAIT_32, Z1_wait_wait32_lc[1], Z1_direct_xfr);


--W1_MW_WAIT_32_d_lc_1c is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MW_WAIT_32_d_lc_1c
--operation mode is normal

W1_MW_WAIT_32_d_lc_1c = AMPP_FUNCTION(W1_MW_WAIT_32_d_lc_1b, W1_MW_WAIT_32_r[2], W1_MW_WAIT_32_r[1]);


--W1_WAIT_WAIT32_lc1 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|WAIT_WAIT32_lc1
--operation mode is normal

W1_WAIT_WAIT32_lc1 = AMPP_FUNCTION(W1_direct_xfr, W1_MW_DXFR, W1_lm_rdynR, W1_devsel_toR);


--W1_MW_WAIT_32_d_lc_1a is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MW_WAIT_32_d_lc_1a
--operation mode is normal

W1_MW_WAIT_32_d_lc_1a = AMPP_FUNCTION(W1_MW_DXFR_32, W1_lm_rdynR, W1_last_xfr_lc1);


--A1L371 is ix1998_lc~0
--operation mode is normal

A1L371 = (!Z1L412 & U1_cben_ir_address[1] & ix2054_lc & ix2069_lc) & CASCADE(A1L213);


--DB1_dec_up[1] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|pcimt64_cd:cfg_adr_dec|dec_up[1]
--operation mode is normal

DB1_dec_up[1] = AMPP_FUNCTION(U1_ad_ir_address[4], U1_ad_ir_address[5], U1_ad_ir_address[6], U1_ad_ir_address[7]);


--W1_MS_TAR_R is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MS_TAR_R
--operation mode is normal

W1_MS_TAR_R = AMPP_FUNCTION(W1_MS_TAR, pci_rstn, GLOBAL(pci_clk));


--BB1_par_rep_rst is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|par_rep_rst
--operation mode is normal

BB1_par_rep_rst = AMPP_FUNCTION(U1_low_ad_IR_data[24], Z1_cfg_dat_vld, DB1_decR[1], U1_low_cben_IR_data[3]);


--BB1_targ_abrt_rcvd_rst is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|targ_abrt_rcvd_rst
--operation mode is normal

BB1_targ_abrt_rcvd_rst = AMPP_FUNCTION(U1_low_ad_IR_data[28], Z1_cfg_dat_vld, DB1_decR[1], U1_low_cben_IR_data[3]);


--BB1_mstr_abrt_rst is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|mstr_abrt_rst
--operation mode is normal

BB1_mstr_abrt_rst = AMPP_FUNCTION(U1_low_ad_IR_data[29], Z1_cfg_dat_vld, DB1_decR[1], U1_low_cben_IR_data[3]);


--BB1_serr_rst is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|serr_rst
--operation mode is normal

BB1_serr_rst = AMPP_FUNCTION(U1_low_ad_IR_data[30], Z1_cfg_dat_vld, DB1_decR[1], U1_low_cben_IR_data[3]);


--BB1_perr_det_rst is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|perr_det_rst
--operation mode is normal

BB1_perr_det_rst = AMPP_FUNCTION(U1_low_ad_IR_data[31], Z1_cfg_dat_vld, DB1_decR[1], U1_low_cben_IR_data[3]);


--W1L872 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MR_IDLE_lc1~23
--operation mode is normal

W1L872 = AMPP_FUNCTION(W1_MS_ADR2, W1_MS_ADR, W1_dac_cyc_reg);


--W1_MR_PXFR_lc1 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MR_PXFR_lc1
--operation mode is normal

W1_MR_PXFR_lc1 = AMPP_FUNCTION(W1L872, W1_wr_rdn, W1_MR_IDLE_not);


--W1L34 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00216~0
--operation mode is normal

W1L34 = AMPP_FUNCTION(W1_no_op_reg[1], A1L944, W1_devsel_toR);


--W1L14 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00214~0
--operation mode is normal

W1L14 = AMPP_FUNCTION(W1_no_op_reg[3], W1L04, W1_no_op_reg[2]);


--W1L24 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00215~0
--operation mode is normal

W1L24 = AMPP_FUNCTION(W1_MW_LXFR, W1_devsel_toR);


--W1_MR_LPXFR_lc2 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MR_LPXFR_lc2
--operation mode is normal

W1_MR_LPXFR_lc2 = AMPP_FUNCTION(W1_MR_LPXFR, W1_devsel_toR);


--Y1_par[7] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pg:parity_gen|par[7]
--operation mode is normal

Y1_par[7] = AMPP_FUNCTION(U1_low_ad_or[28], U1_low_ad_or[29], U1_low_ad_or[30], U1_low_ad_or[31]);


--Y1_par[6] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pg:parity_gen|par[6]
--operation mode is normal

Y1_par[6] = AMPP_FUNCTION(U1_low_ad_or[24], U1_low_ad_or[25], U1_low_ad_or[26], U1_low_ad_or[27]);


--Y1_par[5] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pg:parity_gen|par[5]
--operation mode is normal

Y1_par[5] = AMPP_FUNCTION(U1_low_ad_or[20], U1_low_ad_or[21], U1_low_ad_or[22], U1_low_ad_or[23]);


--Y1_par[4] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pg:parity_gen|par[4]
--operation mode is normal

Y1_par[4] = AMPP_FUNCTION(U1_low_ad_or[16], U1_low_ad_or[17], U1_low_ad_or[18], U1_low_ad_or[19]);


--Y1_par[3] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pg:parity_gen|par[3]
--operation mode is normal

Y1_par[3] = AMPP_FUNCTION(U1_low_ad_or[12], U1_low_ad_or[13], U1_low_ad_or[14], U1_low_ad_or[15]);


--Y1_par[2] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pg:parity_gen|par[2]
--operation mode is normal

Y1_par[2] = AMPP_FUNCTION(U1_low_ad_or[8], U1_low_ad_or[9], U1_low_ad_or[10], U1_low_ad_or[11]);


--Y1_par[1] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pg:parity_gen|par[1]
--operation mode is normal

Y1_par[1] = AMPP_FUNCTION(U1_low_ad_or[4], U1_low_ad_or[5], U1_low_ad_or[6], U1_low_ad_or[7]);


--Y1_par[0] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pg:parity_gen|par[0]
--operation mode is normal

Y1_par[0] = AMPP_FUNCTION(U1_low_ad_or[0], U1_low_ad_or[1], U1_low_ad_or[2], U1_low_ad_or[3]);


--Z1_trdy_OR_lc[2] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|trdy_OR_lc[2]
--operation mode is normal

Z1_trdy_OR_lc[2] = AMPP_FUNCTION(Z1_lt_rdynR, Z1_LR_LXFR, Z1_TS_DISC);


--S3_dffe49a[10] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|alt_synch_pipe_cb3:alt_synch_pipe10|dffpipe_cb3:dffpipe47|dffe49a[10]
--operation mode is normal

S3_dffe49a[10]_lut_out = S3_dffe48a[10];
S3_dffe49a[10] = DFFEA(S3_dffe49a[10]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );


--S3_dffe50a[9] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|alt_synch_pipe_cb3:alt_synch_pipe10|dffpipe_cb3:dffpipe47|dffe50a[9]
--operation mode is normal

S3_dffe50a[9]_lut_out = S3_dffe49a[9];
S3_dffe50a[9] = DFFEA(S3_dffe50a[9]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );


--S3_dffe50a[8] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|alt_synch_pipe_cb3:alt_synch_pipe10|dffpipe_cb3:dffpipe47|dffe50a[8]
--operation mode is normal

S3_dffe50a[8]_lut_out = S3_dffe49a[8];
S3_dffe50a[8] = DFFEA(S3_dffe50a[8]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );


--S3_dffe50a[7] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|alt_synch_pipe_cb3:alt_synch_pipe10|dffpipe_cb3:dffpipe47|dffe50a[7]
--operation mode is normal

S3_dffe50a[7]_lut_out = S3_dffe49a[7];
S3_dffe50a[7] = DFFEA(S3_dffe50a[7]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );


--S3_dffe50a[6] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|alt_synch_pipe_cb3:alt_synch_pipe10|dffpipe_cb3:dffpipe47|dffe50a[6]
--operation mode is normal

S3_dffe50a[6]_lut_out = S3_dffe49a[6];
S3_dffe50a[6] = DFFEA(S3_dffe50a[6]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );


--S3_dffe50a[5] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|alt_synch_pipe_cb3:alt_synch_pipe10|dffpipe_cb3:dffpipe47|dffe50a[5]
--operation mode is normal

S3_dffe50a[5]_lut_out = S3_dffe49a[5];
S3_dffe50a[5] = DFFEA(S3_dffe50a[5]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );


--S3_dffe50a[4] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|alt_synch_pipe_cb3:alt_synch_pipe10|dffpipe_cb3:dffpipe47|dffe50a[4]
--operation mode is normal

S3_dffe50a[4]_lut_out = S3_dffe49a[4];
S3_dffe50a[4] = DFFEA(S3_dffe50a[4]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );


--S3_dffe50a[3] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|alt_synch_pipe_cb3:alt_synch_pipe10|dffpipe_cb3:dffpipe47|dffe50a[3]
--operation mode is normal

S3_dffe50a[3]_lut_out = S3_dffe49a[3];
S3_dffe50a[3] = DFFEA(S3_dffe50a[3]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );


--S3_dffe50a[1] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|alt_synch_pipe_cb3:alt_synch_pipe10|dffpipe_cb3:dffpipe47|dffe50a[1]
--operation mode is normal

S3_dffe50a[1]_lut_out = S3_dffe49a[1];
S3_dffe50a[1] = DFFEA(S3_dffe50a[1]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );


--S3_dffe50a[2] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|alt_synch_pipe_cb3:alt_synch_pipe10|dffpipe_cb3:dffpipe47|dffe50a[2]
--operation mode is normal

S3_dffe50a[2]_lut_out = S3_dffe49a[2];
S3_dffe50a[2] = DFFEA(S3_dffe50a[2]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );


--S3_dffe49a[0] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|alt_synch_pipe_cb3:alt_synch_pipe10|dffpipe_cb3:dffpipe47|dffe49a[0]
--operation mode is normal

S3_dffe49a[0]_lut_out = S3_dffe48a[0];
S3_dffe49a[0] = DFFEA(S3_dffe49a[0]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );


--W1_stopR is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|stopR
--operation mode is normal

W1_stopR = AMPP_FUNCTION(A1L744, pci_rstn, GLOBAL(pci_clk));


--W1_retry_det_set1 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|retry_det_set1
--operation mode is normal

W1_retry_det_set1 = AMPP_FUNCTION(W1_stopR, Z1_TS_IDLE_NOT, W1_tabrt_set);


--W1_devselR is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|devselR
--operation mode is normal

W1_devselR = AMPP_FUNCTION(A1L034, pci_rstn, GLOBAL(pci_clk));


--W1_$00065 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00065
--operation mode is normal

W1_$00065 = AMPP_FUNCTION(W1_MS_DXFR, W1_devselR);


--dpm_dec_reg_tmp is dpm_dec_reg_tmp
--operation mode is normal

dpm_dec_reg_tmp_lut_out = Z1_TS_IDLE_NOT & BB1_bar_hitR[0];
dpm_dec_reg_tmp = DFFEA(dpm_dec_reg_tmp_lut_out, GLOBAL(pci_clk), pci_rstn, , , , );


--W1_lm_ack_or_lc[7] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|lm_ack_or_lc[7]
--operation mode is normal

W1_lm_ack_or_lc[7] = AMPP_FUNCTION(W1_lm_rdynR, W1_lm_ack_or_lc[6], W1_devsel_toR);


--W1_lm_ack_or_lc[2] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|lm_ack_or_lc[2]
--operation mode is normal

W1_lm_ack_or_lc[2] = AMPP_FUNCTION(W1_lm_ack_or_lc[1], W1_direct_xfr, W1_MW_WAIT);


--W1L44 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00221~0
--operation mode is normal

W1L44 = AMPP_FUNCTION(A1L944, W1_no_op_reg[1]);


--dpm_ni2f_modgen_eq_100_ix22 is dpm_ni2f_modgen_eq_100_ix22
--operation mode is normal

dpm_ni2f_modgen_eq_100_ix22 = !dpm_ni2f_reg_cdata_15 & !dpm_ni2f_reg_cdata_14 & !dpm_ni2f_reg_cdata_13 & !dpm_ni2f_reg_cdata_12;


--A1L74 is dpm_ni2f_modgen_eq_100_ix26~0
--operation mode is normal

A1L74 = (!dpm_ni2f_reg_cdata_11 & !dpm_ni2f_reg_cdata_10 & !dpm_ni2f_reg_cdata_9 & !dpm_ni2f_reg_cdata_8) & CASCADE(dpm_ni2f_modgen_eq_100_ix22);


--W1_MW_DXFR_32_lc[1] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MW_DXFR_32_lc[1]
--operation mode is normal

W1_MW_DXFR_32_lc[1] = AMPP_FUNCTION(W1_MW_DXFR, W1_lm_rdynR, W1_direct_xfr);


--W1_MW_WAIT_32_d_lc_1b is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MW_WAIT_32_d_lc_1b
--operation mode is normal

W1_MW_WAIT_32_d_lc_1b = AMPP_FUNCTION(W1_MW_DXFR, W1_lm_rdynR, W1_direct_xfr, W1_devsel_toR);


--X1_$00005 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pk:parity_Chk|$00005
--operation mode is normal

X1_$00005 = AMPP_FUNCTION(W1_tgt_64_response_reg, AB3_REG, Z1_perr_vldR, W1_perr_vldR);


--W1_latcntr_toR_lc1 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|latcntr_toR_lc1
--operation mode is normal

W1_latcntr_toR_lc1 = AMPP_FUNCTION(W1_MS_ENA, W1_MS_REQ);


--W1_latcntr_toR_lc2 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|latcntr_toR_lc2
--operation mode is normal

W1_latcntr_toR_lc2 = AMPP_FUNCTION(W1_MS_TAR, W1_MS_ENA, W1_MS_REQ, W1_MS_IDLE_not);


--W1L17 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|_~152
--operation mode is normal

W1L17 = AMPP_FUNCTION(A1L944, W1_devsel_toR);


--W1_no_op_reg[4] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|no_op_reg[4]
--operation mode is normal

W1_no_op_reg[4] = AMPP_FUNCTION(pci_rstn, GLOBAL(pci_clk));


--W1L45 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00248~0
--operation mode is normal

W1L45 = AMPP_FUNCTION(A1L944, W1_no_op_reg[4]);


--W1_MW_DXFR_lc[1] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MW_DXFR_lc[1]
--operation mode is normal

W1_MW_DXFR_lc[1] = AMPP_FUNCTION(W1_lm_rdynR, W1_MW_DXFR_32, W1_last_xfr_lc1);


--W1L492 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MR_LPXFR_lc1~16
--operation mode is normal

W1L492 = AMPP_FUNCTION(W1_last_xfr, W1_MR_IDLE_not, W1L972);


--W1_no_op_reg[5] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|no_op_reg[5]
--operation mode is normal

W1_no_op_reg[5] = AMPP_FUNCTION(pci_rstn, GLOBAL(pci_clk));


--Y2_par[9] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pg:parity_gen64|par[9]
--operation mode is normal

Y2_par[9] = AMPP_FUNCTION(Y2_par[7], Y2_par[6], Y2_par[5], Y2_par[4]);


--Y2_par[8] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pg:parity_gen64|par[8]
--operation mode is normal

Y2_par[8] = AMPP_FUNCTION(Y2_par[3], Y2_par[2], Y2_par[1], Y2_par[0]);


--W1L57 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|_~221
--operation mode is normal

W1L57 = AMPP_FUNCTION(W1_req64_or_lc[1], W1L62, W1_$00165);


--S3_dffe48a[10] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|alt_synch_pipe_cb3:alt_synch_pipe10|dffpipe_cb3:dffpipe47|dffe48a[10]
--operation mode is normal

S3_dffe48a[10]_lut_out = G2_dffe9a[10];
S3_dffe48a[10] = DFFEA(S3_dffe48a[10]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );


--S3_dffe49a[9] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|alt_synch_pipe_cb3:alt_synch_pipe10|dffpipe_cb3:dffpipe47|dffe49a[9]
--operation mode is normal

S3_dffe49a[9]_lut_out = S3_dffe48a[9];
S3_dffe49a[9] = DFFEA(S3_dffe49a[9]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );


--S3_dffe49a[8] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|alt_synch_pipe_cb3:alt_synch_pipe10|dffpipe_cb3:dffpipe47|dffe49a[8]
--operation mode is normal

S3_dffe49a[8]_lut_out = S3_dffe48a[8];
S3_dffe49a[8] = DFFEA(S3_dffe49a[8]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );


--S3_dffe49a[7] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|alt_synch_pipe_cb3:alt_synch_pipe10|dffpipe_cb3:dffpipe47|dffe49a[7]
--operation mode is normal

S3_dffe49a[7]_lut_out = S3_dffe48a[7];
S3_dffe49a[7] = DFFEA(S3_dffe49a[7]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );


--S3_dffe49a[6] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|alt_synch_pipe_cb3:alt_synch_pipe10|dffpipe_cb3:dffpipe47|dffe49a[6]
--operation mode is normal

S3_dffe49a[6]_lut_out = S3_dffe48a[6];
S3_dffe49a[6] = DFFEA(S3_dffe49a[6]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );


--S3_dffe49a[5] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|alt_synch_pipe_cb3:alt_synch_pipe10|dffpipe_cb3:dffpipe47|dffe49a[5]
--operation mode is normal

S3_dffe49a[5]_lut_out = S3_dffe48a[5];
S3_dffe49a[5] = DFFEA(S3_dffe49a[5]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );


--S3_dffe49a[4] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|alt_synch_pipe_cb3:alt_synch_pipe10|dffpipe_cb3:dffpipe47|dffe49a[4]
--operation mode is normal

S3_dffe49a[4]_lut_out = S3_dffe48a[4];
S3_dffe49a[4] = DFFEA(S3_dffe49a[4]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );


--S3_dffe49a[3] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|alt_synch_pipe_cb3:alt_synch_pipe10|dffpipe_cb3:dffpipe47|dffe49a[3]
--operation mode is normal

S3_dffe49a[3]_lut_out = S3_dffe48a[3];
S3_dffe49a[3] = DFFEA(S3_dffe49a[3]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );


--S3_dffe49a[1] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|alt_synch_pipe_cb3:alt_synch_pipe10|dffpipe_cb3:dffpipe47|dffe49a[1]
--operation mode is normal

S3_dffe49a[1]_lut_out = S3_dffe48a[1];
S3_dffe49a[1] = DFFEA(S3_dffe49a[1]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );


--S3_dffe49a[2] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|alt_synch_pipe_cb3:alt_synch_pipe10|dffpipe_cb3:dffpipe47|dffe49a[2]
--operation mode is normal

S3_dffe49a[2]_lut_out = S3_dffe48a[2];
S3_dffe49a[2] = DFFEA(S3_dffe49a[2]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );


--S3_dffe48a[0] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|alt_synch_pipe_cb3:alt_synch_pipe10|dffpipe_cb3:dffpipe47|dffe48a[0]
--operation mode is normal

S3_dffe48a[0]_lut_out = G2_dffe9a[0];
S3_dffe48a[0] = DFFEA(S3_dffe48a[0]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );


--W1L76 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|_~17
--operation mode is normal

W1L76 = AMPP_FUNCTION(W1_MS_DXFR, W1_MS_TAR);


--W1_disc1_det_set is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|disc1_det_set
--operation mode is normal

W1_disc1_det_set = AMPP_FUNCTION(W1_stopR, W1L76, W1_trdyR, Z1_TS_IDLE_NOT);


--W1L43 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00186~0
--operation mode is normal

W1L43 = AMPP_FUNCTION(W1_MW_LXFR, W1_MW_HOLD, W1_lm_rdynR);


--W1L512 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|lm_ack_or_lc[5]~143
--operation mode is normal

W1L512 = AMPP_FUNCTION(W1_direct_xfr, W1_devsel_toR, W1_last_xfr, W1L43);


--W1_lm_ack_or_lc[6] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|lm_ack_or_lc[6]
--operation mode is normal

W1_lm_ack_or_lc[6] = AMPP_FUNCTION(W1_MW_LXFR, W1_MW_DXFR, W1_MW_DXFR_32, W1_last_xfr_lc1);


--W1_lm_ack_or_lc[1] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|lm_ack_or_lc[1]
--operation mode is normal

W1_lm_ack_or_lc[1] = AMPP_FUNCTION(W1_MW_WAIT_32_r[2], W1_MW_WAIT_32_r[1], W1_MW_DXFR, W1_devsel_toR);


--W1L58 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|_~355
--operation mode is normal

W1L58 = AMPP_FUNCTION(W1_MR_LPXFR, W1_MR_PXFR, W1_devsel_toR);


--W1L212 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|lm_ack_or_lc[3]~144
--operation mode is normal

W1L212 = AMPP_FUNCTION(W1_lm_rdynR, W1_MW_LXFR, W1L58);


--Z1_LR_LXFR_lc[4] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|LR_LXFR_lc[4]
--operation mode is normal

Z1_LR_LXFR_lc[4] = AMPP_FUNCTION(Z1_LR_PXFR, Z1_lt_rdynR, Z1_TS_DISC);


--W1_MW_WAIT_32_lc[2] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MW_WAIT_32_lc[2]
--operation mode is normal

W1_MW_WAIT_32_lc[2] = AMPP_FUNCTION(W1_MW_WAIT_32, W1_MW_DXFR, W1_lm_rdynR, W1_direct_xfr);


--W1_MW_WAIT_32_lc[3] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MW_WAIT_32_lc[3]
--operation mode is normal

W1_MW_WAIT_32_lc[3] = AMPP_FUNCTION(W1_MW_DXFR, W1_direct_xfr);


--Y2_par[7] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pg:parity_gen64|par[7]
--operation mode is normal

Y2_par[7] = AMPP_FUNCTION(U1_high_ad_or[60], U1_high_ad_or[61], U1_high_ad_or[62], U1_high_ad_or[63]);


--Y2_par[6] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pg:parity_gen64|par[6]
--operation mode is normal

Y2_par[6] = AMPP_FUNCTION(U1_high_ad_or[56], U1_high_ad_or[57], U1_high_ad_or[58], U1_high_ad_or[59]);


--Y2_par[5] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pg:parity_gen64|par[5]
--operation mode is normal

Y2_par[5] = AMPP_FUNCTION(U1_high_ad_or[52], U1_high_ad_or[53], U1_high_ad_or[54], U1_high_ad_or[55]);


--Y2_par[4] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pg:parity_gen64|par[4]
--operation mode is normal

Y2_par[4] = AMPP_FUNCTION(U1_high_ad_or[48], U1_high_ad_or[49], U1_high_ad_or[50], U1_high_ad_or[51]);


--Y2_par[3] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pg:parity_gen64|par[3]
--operation mode is normal

Y2_par[3] = AMPP_FUNCTION(U1_high_ad_or[44], U1_high_ad_or[45], U1_high_ad_or[46], U1_high_ad_or[47]);


--Y2_par[2] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pg:parity_gen64|par[2]
--operation mode is normal

Y2_par[2] = AMPP_FUNCTION(U1_high_ad_or[40], U1_high_ad_or[41], U1_high_ad_or[42], U1_high_ad_or[43]);


--Y2_par[1] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pg:parity_gen64|par[1]
--operation mode is normal

Y2_par[1] = AMPP_FUNCTION(U1_high_ad_or[37], U1_high_ad_or[36], U1_high_ad_or[39], U1_high_ad_or[38]);


--Y2_par[0] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_pg:parity_gen64|par[0]
--operation mode is normal

Y2_par[0] = AMPP_FUNCTION(U1_high_ad_or[33], U1_high_ad_or[32], U1_high_ad_or[35], U1_high_ad_or[34]);


--G2_dffe9a[10] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|dffe9a[10]
--operation mode is normal

G2_dffe9a[10]_lut_out = L2_power_modified_counter_values[10];
G2_dffe9a[10] = DFFEA(G2_dffe9a[10]_lut_out, ADC2_D[2], !dpm_ni2f_reg_sreset120, , , , );


--S3_dffe48a[9] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|alt_synch_pipe_cb3:alt_synch_pipe10|dffpipe_cb3:dffpipe47|dffe48a[9]
--operation mode is normal

S3_dffe48a[9]_lut_out = G2_dffe9a[9];
S3_dffe48a[9] = DFFEA(S3_dffe48a[9]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );


--S3_dffe48a[8] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|alt_synch_pipe_cb3:alt_synch_pipe10|dffpipe_cb3:dffpipe47|dffe48a[8]
--operation mode is normal

S3_dffe48a[8]_lut_out = G2_dffe9a[8];
S3_dffe48a[8] = DFFEA(S3_dffe48a[8]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );


--S3_dffe48a[7] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|alt_synch_pipe_cb3:alt_synch_pipe10|dffpipe_cb3:dffpipe47|dffe48a[7]
--operation mode is normal

S3_dffe48a[7]_lut_out = G2_dffe9a[7];
S3_dffe48a[7] = DFFEA(S3_dffe48a[7]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );


--S3_dffe48a[6] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|alt_synch_pipe_cb3:alt_synch_pipe10|dffpipe_cb3:dffpipe47|dffe48a[6]
--operation mode is normal

S3_dffe48a[6]_lut_out = G2_dffe9a[6];
S3_dffe48a[6] = DFFEA(S3_dffe48a[6]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );


--S3_dffe48a[5] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|alt_synch_pipe_cb3:alt_synch_pipe10|dffpipe_cb3:dffpipe47|dffe48a[5]
--operation mode is normal

S3_dffe48a[5]_lut_out = G2_dffe9a[5];
S3_dffe48a[5] = DFFEA(S3_dffe48a[5]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );


--S3_dffe48a[4] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|alt_synch_pipe_cb3:alt_synch_pipe10|dffpipe_cb3:dffpipe47|dffe48a[4]
--operation mode is normal

S3_dffe48a[4]_lut_out = G2_dffe9a[4];
S3_dffe48a[4] = DFFEA(S3_dffe48a[4]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );


--S3_dffe48a[3] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|alt_synch_pipe_cb3:alt_synch_pipe10|dffpipe_cb3:dffpipe47|dffe48a[3]
--operation mode is normal

S3_dffe48a[3]_lut_out = G2_dffe9a[3];
S3_dffe48a[3] = DFFEA(S3_dffe48a[3]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );


--S3_dffe48a[1] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|alt_synch_pipe_cb3:alt_synch_pipe10|dffpipe_cb3:dffpipe47|dffe48a[1]
--operation mode is normal

S3_dffe48a[1]_lut_out = G2_dffe9a[1];
S3_dffe48a[1] = DFFEA(S3_dffe48a[1]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );


--S3_dffe48a[2] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|alt_synch_pipe_cb3:alt_synch_pipe10|dffpipe_cb3:dffpipe47|dffe48a[2]
--operation mode is normal

S3_dffe48a[2]_lut_out = G2_dffe9a[2];
S3_dffe48a[2] = DFFEA(S3_dffe48a[2]_lut_out, CLK50M, !dpm_ni2f_reg_sreset120, , , , );


--G2_dffe9a[0] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|dffe9a[0]
--operation mode is normal

G2_dffe9a[0]_lut_out = L2_power_modified_counter_values[0];
G2_dffe9a[0] = DFFEA(G2_dffe9a[0]_lut_out, ADC2_D[2], !dpm_ni2f_reg_sreset120, , , , );


--Z1L651 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|LR_PXFR_32_cc1~0
--operation mode is normal

Z1L651 = AMPP_FUNCTION(Z1_LR_LXFR_lc[1], Z1_lt_rdynR, Z1_direct_xfr);


--Z1L851 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|LR_PXFR_32_lc[1]~15
--operation mode is normal

Z1L851 = AMPP_FUNCTION(Z1_LR_LXFR, Z1_LR_LXFR_lc[2], Z1_LR_LXFR_lc[1], Z1_TS_DISC, Z1L651);


--W1L824 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MW_WAIT_lc[1]~20
--operation mode is normal

W1L824 = AMPP_FUNCTION(W1_direct_xfr, W1_last_xfr, W1_lm_rdynR, W1_devsel_toR, W1L463);


--G2_dffe9a[9] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|dffe9a[9]
--operation mode is normal

G2_dffe9a[9]_lut_out = L2_power_modified_counter_values[9];
G2_dffe9a[9] = DFFEA(G2_dffe9a[9]_lut_out, ADC2_D[2], !dpm_ni2f_reg_sreset120, , , , );


--G2_dffe9a[8] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|dffe9a[8]
--operation mode is normal

G2_dffe9a[8]_lut_out = L2_power_modified_counter_values[8];
G2_dffe9a[8] = DFFEA(G2_dffe9a[8]_lut_out, ADC2_D[2], !dpm_ni2f_reg_sreset120, , , , );


--G2_dffe9a[7] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|dffe9a[7]
--operation mode is normal

G2_dffe9a[7]_lut_out = L2_power_modified_counter_values[7];
G2_dffe9a[7] = DFFEA(G2_dffe9a[7]_lut_out, ADC2_D[2], !dpm_ni2f_reg_sreset120, , , , );


--G2_dffe9a[6] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|dffe9a[6]
--operation mode is normal

G2_dffe9a[6]_lut_out = L2_power_modified_counter_values[6];
G2_dffe9a[6] = DFFEA(G2_dffe9a[6]_lut_out, ADC2_D[2], !dpm_ni2f_reg_sreset120, , , , );


--G2_dffe9a[5] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|dffe9a[5]
--operation mode is normal

G2_dffe9a[5]_lut_out = L2_power_modified_counter_values[5];
G2_dffe9a[5] = DFFEA(G2_dffe9a[5]_lut_out, ADC2_D[2], !dpm_ni2f_reg_sreset120, , , , );


--G2_dffe9a[4] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|dffe9a[4]
--operation mode is normal

G2_dffe9a[4]_lut_out = L2_power_modified_counter_values[4];
G2_dffe9a[4] = DFFEA(G2_dffe9a[4]_lut_out, ADC2_D[2], !dpm_ni2f_reg_sreset120, , , , );


--G2_dffe9a[3] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|dffe9a[3]
--operation mode is normal

G2_dffe9a[3]_lut_out = L2_power_modified_counter_values[3];
G2_dffe9a[3] = DFFEA(G2_dffe9a[3]_lut_out, ADC2_D[2], !dpm_ni2f_reg_sreset120, , , , );


--G2_dffe9a[1] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|dffe9a[1]
--operation mode is normal

G2_dffe9a[1]_lut_out = L2_power_modified_counter_values[1];
G2_dffe9a[1] = DFFEA(G2_dffe9a[1]_lut_out, ADC2_D[2], !dpm_ni2f_reg_sreset120, , , , );


--G2_dffe9a[2] is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|dffe9a[2]
--operation mode is normal

G2_dffe9a[2]_lut_out = L2_power_modified_counter_values[2];
G2_dffe9a[2] = DFFEA(G2_dffe9a[2]_lut_out, ADC2_D[2], !dpm_ni2f_reg_sreset120, , , , );


--W1_trdy_det_set is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|trdy_det_set
--operation mode is normal

W1_trdy_det_set = AMPP_FUNCTION(W1_MS_DXFR, Z1_TS_IDLE_NOT);


--W1L09 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|_~1319
--operation mode is normal

W1L09 = AMPP_FUNCTION(E01_q[0], E01_q[3], E01_q[2], E01_q[1]);


--W1L202 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|latcntr_tc~1
--operation mode is normal

W1L202 = AMPP_FUNCTION(E01_q[7], E01_q[6], E01_q[5], E01_q[4], W1L09);


--W1_latcntr_cnt_en is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|latcntr_cnt_en
--operation mode is normal

W1_latcntr_cnt_en = AMPP_FUNCTION(W1_MS_DXFR, W1L202);


--W1_$00061 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00061
--operation mode is normal

W1_$00061 = AMPP_FUNCTION(W1_MS_REQ, W1_MS_TAR, W1_MS_IDLE_not);


--ix2011_lc is ix2011_lc
--operation mode is normal

ix2011_lc = Z1_no_op_reg[1] & U1_ad_ir_address[19] & dpm_ni2f_reg_sram_qH_12;


--ix2010_lc is ix2010_lc
--operation mode is normal

ix2010_lc = Z1_no_op_reg[1] & U1_ad_ir_address[19] & dpm_ni2f_reg_sram_qH_13;


--A1L471 is ix1999_lc~0
--operation mode is normal

A1L471 = (Z1L012 & !ix2070_lc & (!U1_ad_ir_address[19] # !Z1_no_op_reg[1])) & CASCADE(ix2052);


--A1L223 is ix2098~1
--operation mode is normal

A1L223 = dpm_ni2f_reg_sram_qL_0 # !U1_ad_ir_address[19] # !Z1_no_op_reg[1];


--A1L123 is ix2097~1
--operation mode is normal

A1L123 = dpm_ni2f_reg_sram_qL_1 # !U1_ad_ir_address[19] # !Z1_no_op_reg[1];


--A1L023 is ix2096~1
--operation mode is normal

A1L023 = dpm_ni2f_reg_sram_qL_2 # !U1_ad_ir_address[19] # !Z1_no_op_reg[1];


--A1L913 is ix2095~1
--operation mode is normal

A1L913 = dpm_ni2f_reg_sram_qL_3 # !U1_ad_ir_address[19] # !Z1_no_op_reg[1];


--A1L813 is ix2094~1
--operation mode is normal

A1L813 = dpm_ni2f_reg_sram_qL_4 # !U1_ad_ir_address[19] # !Z1_no_op_reg[1];


--A1L713 is ix2093~1
--operation mode is normal

A1L713 = dpm_ni2f_reg_sram_qL_5 # !U1_ad_ir_address[19] # !Z1_no_op_reg[1];


--A1L613 is ix2092~1
--operation mode is normal

A1L613 = dpm_ni2f_reg_sram_qL_6 # !U1_ad_ir_address[19] # !Z1_no_op_reg[1];


--A1L513 is ix2091~1
--operation mode is normal

A1L513 = dpm_ni2f_reg_sram_qL_7 # !U1_ad_ir_address[19] # !Z1_no_op_reg[1];


--A1L413 is ix2090~1
--operation mode is normal

A1L413 = dpm_ni2f_reg_sram_qL_8 # !U1_ad_ir_address[19] # !Z1_no_op_reg[1];


--A1L313 is ix2089~1
--operation mode is normal

A1L313 = dpm_ni2f_reg_sram_qL_9 # !U1_ad_ir_address[19] # !Z1_no_op_reg[1];


--A1L161 is ix1986_lc~0
--operation mode is normal

A1L161 = (!dpm_ni2f_reg_sram_qL_10 # !U1_ad_ir_address[19] # !Z1_no_op_reg[1]) & CASCADE(ix2037);


--A1L061 is ix1985_lc~0
--operation mode is normal

A1L061 = (!dpm_ni2f_reg_sram_qL_11 # !U1_ad_ir_address[19] # !Z1_no_op_reg[1]) & CASCADE(ix2036);


--A1L951 is ix1984_lc~0
--operation mode is normal

A1L951 = (!dpm_ni2f_reg_sram_qL_12 # !U1_ad_ir_address[19] # !Z1_no_op_reg[1]) & CASCADE(ix2035);


--A1L851 is ix1983_lc~0
--operation mode is normal

A1L851 = (!dpm_ni2f_reg_sram_qL_13 # !U1_ad_ir_address[19] # !Z1_no_op_reg[1]) & CASCADE(ix2034);


--A1L751 is ix1982_lc~0
--operation mode is normal

A1L751 = (!dpm_ni2f_reg_sram_qL_14 # !U1_ad_ir_address[19] # !Z1_no_op_reg[1]) & CASCADE(ix2033);


--A1L651 is ix1981_lc~0
--operation mode is normal

A1L651 = (!dpm_ni2f_reg_sram_qL_15 # !U1_ad_ir_address[19] # !Z1_no_op_reg[1]) & CASCADE(ix2032);


--A1L551 is ix1980_lc~0
--operation mode is normal

A1L551 = (!dpm_ni2f_reg_sram_qH_0 # !U1_ad_ir_address[19] # !Z1_no_op_reg[1]) & CASCADE(ix2031);


--A1L451 is ix1979_lc~0
--operation mode is normal

A1L451 = (!dpm_ni2f_reg_sram_qH_1 # !U1_ad_ir_address[19] # !Z1_no_op_reg[1]) & CASCADE(ix2030);


--A1L351 is ix1978_lc~0
--operation mode is normal

A1L351 = (!dpm_ni2f_reg_sram_qH_2 # !U1_ad_ir_address[19] # !Z1_no_op_reg[1]) & CASCADE(ix2029);


--A1L251 is ix1977_lc~0
--operation mode is normal

A1L251 = (!dpm_ni2f_reg_sram_qH_3 # !U1_ad_ir_address[19] # !Z1_no_op_reg[1]) & CASCADE(ix2028);


--A1L151 is ix1976_lc~0
--operation mode is normal

A1L151 = (!dpm_ni2f_reg_sram_qH_4 # !U1_ad_ir_address[19] # !Z1_no_op_reg[1]) & CASCADE(ix2027);


--A1L051 is ix1975_lc~0
--operation mode is normal

A1L051 = (!dpm_ni2f_reg_sram_qH_5 # !U1_ad_ir_address[19] # !Z1_no_op_reg[1]) & CASCADE(ix2026);


--A1L941 is ix1974_lc~0
--operation mode is normal

A1L941 = (!dpm_ni2f_reg_sram_qH_6 # !U1_ad_ir_address[19] # !Z1_no_op_reg[1]) & CASCADE(ix2025);


--A1L841 is ix1973_lc~0
--operation mode is normal

A1L841 = (!dpm_ni2f_reg_sram_qH_7 # !U1_ad_ir_address[19] # !Z1_no_op_reg[1]) & CASCADE(ix2024);


--A1L203 is ix2080~1
--operation mode is normal

A1L203 = !dpm_ni2f_reg_sram_qH_8 # !U1_ad_ir_address[19] # !Z1_no_op_reg[1];


--A1L741 is ix1972_lc~0
--operation mode is normal

A1L741 = (Z1_no_op_reg[1] & U1_ad_ir_address[19] # !ix2023_lc # !ix2022_lc) & CASCADE(A1L203);


--A1L303 is ix2081~1
--operation mode is normal

A1L303 = !dpm_ni2f_reg_sram_qH_9 # !U1_ad_ir_address[19] # !Z1_no_op_reg[1];


--A1L603 is ix2083~1
--operation mode is normal

A1L603 = !dpm_ni2f_reg_sram_qH_10 # !U1_ad_ir_address[19] # !Z1_no_op_reg[1];


--A1L013 is ix2086~1
--operation mode is normal

A1L013 = !dpm_ni2f_reg_sram_qH_11 # !U1_ad_ir_address[19] # !Z1_no_op_reg[1];


--A1L341 is ix1968_lc~0
--operation mode is normal

A1L341 = (!dpm_ni2f_reg_sram_qH_14 # !U1_ad_ir_address[19] # !Z1_no_op_reg[1]) & CASCADE(ix2014);


--A1L241 is ix1967_lc~0
--operation mode is normal

A1L241 = (!dpm_ni2f_reg_sram_qH_15 # !U1_ad_ir_address[19] # !Z1_no_op_reg[1]) & CASCADE(ix2013);


--ix2070_lc is ix2070_lc
--operation mode is normal

ix2070_lc = U1_cben_ir_address[3] & !U1_cben_ir_address[2] # !BB1_bar_hitR[0] # !Z1_TS_IDLE_NOT;


--ix2063_lc is ix2063_lc
--operation mode is normal

ix2063_lc = Z1_no_op_reg[1] & (U1_ad_ir_address[5] & E7_q[8] # !U1_ad_ir_address[5] & dpm_dec_reg_rdata_LED_8) # !Z1_no_op_reg[1] & dpm_dec_reg_rdata_LED_8;


--ix2062_lc is ix2062_lc
--operation mode is normal

ix2062_lc = Z1_no_op_reg[1] & (U1_ad_ir_address[5] & E7_q[9] # !U1_ad_ir_address[5] & dpm_dec_reg_rdata_LED_9) # !Z1_no_op_reg[1] & dpm_dec_reg_rdata_LED_9;


--ix2054_lc is ix2054_lc
--operation mode is normal

ix2054_lc = Z1_TS_IDLE_NOT & BB1_bar_hitR[0] & U1_cben_ir_address[0] & Z1L012;


--A1L361 is ix1988_lc~0
--operation mode is normal

A1L361 = (Z1_no_op_reg[1] & (U1_ad_ir_address[19] # U1_ad_ir_address[4] & ix2063_lc)) & CASCADE(A1L413);


--A1L261 is ix1987_lc~0
--operation mode is normal

A1L261 = (Z1_no_op_reg[1] & (U1_ad_ir_address[19] # U1_ad_ir_address[4] & ix2062_lc)) & CASCADE(A1L313);


--ix2078_lc is ix2078_lc
--operation mode is normal

ix2078_lc = Z1_no_op_reg[1] & U1_ad_ir_address[4] & !U1_ad_ir_address[5];


--ix2082_lc is ix2082_lc
--operation mode is normal

ix2082_lc = Z1_no_op_reg[1] & U1_ad_ir_address[4] & U1_ad_ir_address[5];


--A1L213 is ix2088~5
--operation mode is normal

A1L213 = Z1_no_op_reg[1] & U1_ad_ir_address[5] & !U1_ad_ir_address[19];


--W1_MS_REQ_d_lc[2] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MS_REQ_d_lc[2]
--operation mode is normal

W1_MS_REQ_d_lc[2] = AMPP_FUNCTION(W1_MS_ENA, W1_l_req_vld, W1_MS_PARK);


--Z1_retry_rst_lc1 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|retry_rst_lc1
--operation mode is normal

Z1_retry_rst_lc1 = AMPP_FUNCTION(Z1_LW_DONE, Z1_LW_IDLE_NOT);


--W1_trdy_det_reset is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|trdy_det_reset
--operation mode is normal

W1_trdy_det_reset = AMPP_FUNCTION(W1_MW_IDLE_not, W1_MR_IDLE_not);


--U1_low_mstr_cbe_out_lc1[0] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_mstr_cbe_out_lc1[0]
--operation mode is normal

U1_low_mstr_cbe_out_lc1[0] = AMPP_FUNCTION();


--U1_low_mstr_cbe_out_lc1[1] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_mstr_cbe_out_lc1[1]
--operation mode is normal

U1_low_mstr_cbe_out_lc1[1] = AMPP_FUNCTION();


--U1_low_mstr_cbe_out_lc1[2] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_mstr_cbe_out_lc1[2]
--operation mode is normal

U1_low_mstr_cbe_out_lc1[2] = AMPP_FUNCTION();


--U1_low_mstr_cbe_out_lc1[3] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_mstr_cbe_out_lc1[3]
--operation mode is normal

U1_low_mstr_cbe_out_lc1[3] = AMPP_FUNCTION();


--BB1_mbar_hit is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|mbar_hit
--operation mode is normal

BB1_mbar_hit = AMPP_FUNCTION(BB1_bar_hit[0]);


--W1_l_req_vld is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|l_req_vld
--operation mode is normal

W1_l_req_vld = AMPP_FUNCTION();


--U1_trg_serr_vld is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|trg_serr_vld
--operation mode is normal

U1_trg_serr_vld = AMPP_FUNCTION(Z1_adr_phase_lc1);


--U1_trg_cben_IR_ce_D is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|trg_cben_IR_ce_D
--operation mode is normal

U1_trg_cben_IR_ce_D = AMPP_FUNCTION(Z1_ad_ir_ce_D_lc1, Z1_TS_TURN_AR, Z1_cfg_cyc, W1_mstr_actv_lc);


--Z1_lt_hdata_ack_r_prn[3] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_hdata_ack_r_prn[3]
--operation mode is normal

Z1_lt_hdata_ack_r_prn[3] = AMPP_FUNCTION(Z1_lt_ldata_ack_r_prn1, Z1L27, Z1_mem_cyc, Z1_retry);


--W1_lm_ldata_ack_lc[3] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|lm_ldata_ack_lc[3]
--operation mode is normal

W1_lm_ldata_ack_lc[3] = AMPP_FUNCTION();


--U1_trg_cfg_cyc_out is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|trg_cfg_cyc_out
--operation mode is normal

U1_trg_cfg_cyc_out = AMPP_FUNCTION(Z1_cfg_cyc);


--V1_ad_ce[0] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[0]
--operation mode is normal

V1_ad_ce[0] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[1] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[1]
--operation mode is normal

V1_ad_ce[1] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[2] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[2]
--operation mode is normal

V1_ad_ce[2] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[3] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[3]
--operation mode is normal

V1_ad_ce[3] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[4] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[4]
--operation mode is normal

V1_ad_ce[4] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[5] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[5]
--operation mode is normal

V1_ad_ce[5] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[6] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[6]
--operation mode is normal

V1_ad_ce[6] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[7] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[7]
--operation mode is normal

V1_ad_ce[7] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[8] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[8]
--operation mode is normal

V1_ad_ce[8] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[9] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[9]
--operation mode is normal

V1_ad_ce[9] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[10] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[10]
--operation mode is normal

V1_ad_ce[10] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[11] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[11]
--operation mode is normal

V1_ad_ce[11] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[12] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[12]
--operation mode is normal

V1_ad_ce[12] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[13] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[13]
--operation mode is normal

V1_ad_ce[13] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[14] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[14]
--operation mode is normal

V1_ad_ce[14] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[15] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[15]
--operation mode is normal

V1_ad_ce[15] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[16] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[16]
--operation mode is normal

V1_ad_ce[16] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[17] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[17]
--operation mode is normal

V1_ad_ce[17] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[18] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[18]
--operation mode is normal

V1_ad_ce[18] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[19] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[19]
--operation mode is normal

V1_ad_ce[19] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[20] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[20]
--operation mode is normal

V1_ad_ce[20] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[21] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[21]
--operation mode is normal

V1_ad_ce[21] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[22] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[22]
--operation mode is normal

V1_ad_ce[22] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[23] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[23]
--operation mode is normal

V1_ad_ce[23] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[24] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[24]
--operation mode is normal

V1_ad_ce[24] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[25] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[25]
--operation mode is normal

V1_ad_ce[25] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[26] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[26]
--operation mode is normal

V1_ad_ce[26] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[27] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[27]
--operation mode is normal

V1_ad_ce[27] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[28] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[28]
--operation mode is normal

V1_ad_ce[28] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[29] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[29]
--operation mode is normal

V1_ad_ce[29] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[30] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[30]
--operation mode is normal

V1_ad_ce[30] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[31] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[31]
--operation mode is normal

V1_ad_ce[31] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[39] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[39]
--operation mode is normal

V1_ad_ce[39] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[38] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[38]
--operation mode is normal

V1_ad_ce[38] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[37] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[37]
--operation mode is normal

V1_ad_ce[37] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[36] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[36]
--operation mode is normal

V1_ad_ce[36] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[35] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[35]
--operation mode is normal

V1_ad_ce[35] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[34] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[34]
--operation mode is normal

V1_ad_ce[34] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[33] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[33]
--operation mode is normal

V1_ad_ce[33] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[32] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[32]
--operation mode is normal

V1_ad_ce[32] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[41] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[41]
--operation mode is normal

V1_ad_ce[41] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[42] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[42]
--operation mode is normal

V1_ad_ce[42] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[43] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[43]
--operation mode is normal

V1_ad_ce[43] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[44] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[44]
--operation mode is normal

V1_ad_ce[44] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[45] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[45]
--operation mode is normal

V1_ad_ce[45] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[46] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[46]
--operation mode is normal

V1_ad_ce[46] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[47] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[47]
--operation mode is normal

V1_ad_ce[47] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[48] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[48]
--operation mode is normal

V1_ad_ce[48] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[49] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[49]
--operation mode is normal

V1_ad_ce[49] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[50] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[50]
--operation mode is normal

V1_ad_ce[50] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[51] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[51]
--operation mode is normal

V1_ad_ce[51] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[52] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[52]
--operation mode is normal

V1_ad_ce[52] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[53] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[53]
--operation mode is normal

V1_ad_ce[53] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[54] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[54]
--operation mode is normal

V1_ad_ce[54] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[55] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[55]
--operation mode is normal

V1_ad_ce[55] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[56] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[56]
--operation mode is normal

V1_ad_ce[56] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[57] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[57]
--operation mode is normal

V1_ad_ce[57] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[58] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[58]
--operation mode is normal

V1_ad_ce[58] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[59] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[59]
--operation mode is normal

V1_ad_ce[59] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[60] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[60]
--operation mode is normal

V1_ad_ce[60] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[61] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[61]
--operation mode is normal

V1_ad_ce[61] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[62] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[62]
--operation mode is normal

V1_ad_ce[62] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--V1_ad_ce[63] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_adce:adce|ad_ce[63]
--operation mode is normal

V1_ad_ce[63] = AMPP_FUNCTION(U1_ad_ce_nc, A1L734, A1L944);


--W1_cbe_oer_r1_lc1 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|cbe_oer_r1_lc1
--operation mode is normal

W1_cbe_oer_r1_lc1 = AMPP_FUNCTION(W1_idle_reg, W1_MS_REQ, W1_MS_IDLE_not);


--Z1_devsel_OR_lc[3] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|devsel_OR_lc[3]
--operation mode is normal

Z1_devsel_OR_lc[3] = AMPP_FUNCTION();


--Z1_stop_or_lc[6] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|stop_or_lc[6]
--operation mode is normal

Z1_stop_or_lc[6] = AMPP_FUNCTION();


--U1_trg_cben_IR_ce_A is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|trg_cben_IR_ce_A
--operation mode is normal

U1_trg_cben_IR_ce_A = AMPP_FUNCTION(Z1_ad_ir_ce_A_lc1, Z1_ad_ir_ce_A_lc2);


--Z1_lt_ldata_ack_r_prn1 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_ldata_ack_r_prn1
--operation mode is normal

Z1_lt_ldata_ack_r_prn1 = AMPP_FUNCTION(U1_ad_ir_address[2]);


--Z1_lt_ldata_ack_r_ena_lc2 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_ldata_ack_r_ena_lc2
--operation mode is normal

Z1_lt_ldata_ack_r_ena_lc2 = AMPP_FUNCTION(Z1_io_cyc);


--W1_MW_IDLE_lc1 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MW_IDLE_lc1
--operation mode is normal

W1_MW_IDLE_lc1 = AMPP_FUNCTION(W1_MW_IDLE_not);


--Z1_rd_backoff is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|rd_backoff
--operation mode is normal

Z1_rd_backoff = AMPP_FUNCTION(Z1_TS_DISC);


--U1_trg_cfg_ad_out[0] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|trg_cfg_ad_out[0]
--operation mode is normal

U1_trg_cfg_ad_out[0] = AMPP_FUNCTION(BB1L11Q);


--U1_trg_cfg_ad_out[1] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|trg_cfg_ad_out[1]
--operation mode is normal

U1_trg_cfg_ad_out[1] = AMPP_FUNCTION(BB1L21Q);


--U1_trg_cfg_ad_out[2] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|trg_cfg_ad_out[2]
--operation mode is normal

U1_trg_cfg_ad_out[2] = AMPP_FUNCTION(BB1L31Q);


--U1_trg_cfg_ad_out[3] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|trg_cfg_ad_out[3]
--operation mode is normal

U1_trg_cfg_ad_out[3] = AMPP_FUNCTION(BB1L41Q);


--U1_trg_cfg_ad_out[4] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|trg_cfg_ad_out[4]
--operation mode is normal

U1_trg_cfg_ad_out[4] = AMPP_FUNCTION(BB1L51Q);


--U1_trg_cfg_ad_out[5] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|trg_cfg_ad_out[5]
--operation mode is normal

U1_trg_cfg_ad_out[5] = AMPP_FUNCTION(BB1L61Q);


--U1_trg_cfg_ad_out[6] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|trg_cfg_ad_out[6]
--operation mode is normal

U1_trg_cfg_ad_out[6] = AMPP_FUNCTION(BB1L71Q);


--U1_trg_cfg_ad_out[7] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|trg_cfg_ad_out[7]
--operation mode is normal

U1_trg_cfg_ad_out[7] = AMPP_FUNCTION(BB1L81Q);


--U1_trg_cfg_ad_out[8] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|trg_cfg_ad_out[8]
--operation mode is normal

U1_trg_cfg_ad_out[8] = AMPP_FUNCTION(BB1L91Q);


--U1_trg_cfg_ad_out[9] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|trg_cfg_ad_out[9]
--operation mode is normal

U1_trg_cfg_ad_out[9] = AMPP_FUNCTION();


--U1_trg_cfg_ad_out[10] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|trg_cfg_ad_out[10]
--operation mode is normal

U1_trg_cfg_ad_out[10] = AMPP_FUNCTION();


--U1_trg_cfg_ad_out[11] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|trg_cfg_ad_out[11]
--operation mode is normal

U1_trg_cfg_ad_out[11] = AMPP_FUNCTION(BB1L02Q);


--U1_trg_cfg_ad_out[12] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|trg_cfg_ad_out[12]
--operation mode is normal

U1_trg_cfg_ad_out[12] = AMPP_FUNCTION(BB1L12Q);


--U1_trg_cfg_ad_out[13] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|trg_cfg_ad_out[13]
--operation mode is normal

U1_trg_cfg_ad_out[13] = AMPP_FUNCTION(BB1L22Q);


--U1_trg_cfg_ad_out[14] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|trg_cfg_ad_out[14]
--operation mode is normal

U1_trg_cfg_ad_out[14] = AMPP_FUNCTION(BB1L32Q);


--U1_trg_cfg_ad_out[15] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|trg_cfg_ad_out[15]
--operation mode is normal

U1_trg_cfg_ad_out[15] = AMPP_FUNCTION(BB1L42Q);


--U1_trg_cfg_ad_out[16] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|trg_cfg_ad_out[16]
--operation mode is normal

U1_trg_cfg_ad_out[16] = AMPP_FUNCTION();


--U1_trg_cfg_ad_out[17] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|trg_cfg_ad_out[17]
--operation mode is normal

U1_trg_cfg_ad_out[17] = AMPP_FUNCTION();


--U1_trg_cfg_ad_out[18] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|trg_cfg_ad_out[18]
--operation mode is normal

U1_trg_cfg_ad_out[18] = AMPP_FUNCTION(BB1L52Q);


--U1_trg_cfg_ad_out[19] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|trg_cfg_ad_out[19]
--operation mode is normal

U1_trg_cfg_ad_out[19] = AMPP_FUNCTION();


--U1_trg_cfg_ad_out[20] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|trg_cfg_ad_out[20]
--operation mode is normal

U1_trg_cfg_ad_out[20] = AMPP_FUNCTION(BB1L62Q);


--U1_trg_cfg_ad_out[21] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|trg_cfg_ad_out[21]
--operation mode is normal

U1_trg_cfg_ad_out[21] = AMPP_FUNCTION(BB1L72Q);


--U1_trg_cfg_ad_out[22] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|trg_cfg_ad_out[22]
--operation mode is normal

U1_trg_cfg_ad_out[22] = AMPP_FUNCTION(BB1L82Q);


--U1_trg_cfg_ad_out[23] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|trg_cfg_ad_out[23]
--operation mode is normal

U1_trg_cfg_ad_out[23] = AMPP_FUNCTION(BB1L92Q);


--U1_trg_cfg_ad_out[24] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|trg_cfg_ad_out[24]
--operation mode is normal

U1_trg_cfg_ad_out[24] = AMPP_FUNCTION(BB1L03Q);


--U1_trg_cfg_ad_out[25] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|trg_cfg_ad_out[25]
--operation mode is normal

U1_trg_cfg_ad_out[25] = AMPP_FUNCTION(BB1L13Q);


--U1_trg_cfg_ad_out[26] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|trg_cfg_ad_out[26]
--operation mode is normal

U1_trg_cfg_ad_out[26] = AMPP_FUNCTION(BB1L23Q);


--U1_trg_cfg_ad_out[27] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|trg_cfg_ad_out[27]
--operation mode is normal

U1_trg_cfg_ad_out[27] = AMPP_FUNCTION(BB1L33Q);


--U1_trg_cfg_ad_out[28] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|trg_cfg_ad_out[28]
--operation mode is normal

U1_trg_cfg_ad_out[28] = AMPP_FUNCTION(BB1L43Q);


--U1_trg_cfg_ad_out[29] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|trg_cfg_ad_out[29]
--operation mode is normal

U1_trg_cfg_ad_out[29] = AMPP_FUNCTION(BB1L53Q);


--U1_trg_cfg_ad_out[30] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|trg_cfg_ad_out[30]
--operation mode is normal

U1_trg_cfg_ad_out[30] = AMPP_FUNCTION(BB1L63Q);


--U1_trg_cfg_ad_out[31] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|trg_cfg_ad_out[31]
--operation mode is normal

U1_trg_cfg_ad_out[31] = AMPP_FUNCTION(BB1L73Q);


--W1_dac_cmd is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|dac_cmd
--operation mode is normal

W1_dac_cmd = AMPP_FUNCTION();


--W1_direct_xfr is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|direct_xfr
--operation mode is normal

W1_direct_xfr = AMPP_FUNCTION(W1_tgt_64_response_reg);


--W1_DXFR_write_lc4a is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|DXFR_write_lc4a
--operation mode is normal

W1_DXFR_write_lc4a = AMPP_FUNCTION(W1_MS_DXFR, W1_irdy_or_not, W1_frame_or_not, W1_mstr_abrt);


--W1_wr_rdn_set is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|wr_rdn_set
--operation mode is normal

W1_wr_rdn_set = AMPP_FUNCTION();


--BB1_mem_cyc is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|pcimt64_c:cfg|mem_cyc
--operation mode is normal

BB1_mem_cyc = AMPP_FUNCTION(U1_cben_ir_address[2], U1_cben_ir_address[1], U1_cben_ir_address[3], U1_cben_ir_address[0]);


--W1_MR_LLXFR_r1_d_lc1 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MR_LLXFR_r1_d_lc1
--operation mode is normal

W1_MR_LLXFR_r1_d_lc1 = AMPP_FUNCTION();


--W1_MR_LWAIT_lc2 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MR_LWAIT_lc2
--operation mode is normal

W1_MR_LWAIT_lc2 = AMPP_FUNCTION(W1_MR_LWAIT);


--Z1_trdy_OR_lc[1] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|trdy_OR_lc[1]
--operation mode is normal

Z1_trdy_OR_lc[1] = AMPP_FUNCTION(Z1_lt_ldata_ack_r, Z1_lt_rdynR_R, Z1_direct_xfr);


--W1_lm_adr_ack_R_lc2 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|lm_adr_ack_R_lc2
--operation mode is normal

W1_lm_adr_ack_R_lc2 = AMPP_FUNCTION();


--W1_last_xfr is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|last_xfr
--operation mode is normal

W1_last_xfr = AMPP_FUNCTION(W1_last_xfr_lc1);


--W1_MR_LPXFR is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MR_LPXFR
--operation mode is normal

W1_MR_LPXFR = AMPP_FUNCTION(W1_MR_LPXFR_r1);


--W1_DXFR_write_lc2 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|DXFR_write_lc2
--operation mode is normal

W1_DXFR_write_lc2 = AMPP_FUNCTION(W1_MS_ADR2, W1_MS_ADR, W1_dac_cyc_reg);


--U1_low_data_out_hr_ena_d is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|low_data_out_hr_ena_d
--operation mode is normal

U1_low_data_out_hr_ena_d = AMPP_FUNCTION(W1_MS_ENA, W1_dati_hr_ena_lc, Z1_TS_IDLE_NOT, Z1_dati_hr_ena_lc);


--W1_lm_hdata_ack_lc[1] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|lm_hdata_ack_lc[1]
--operation mode is normal

W1_lm_hdata_ack_lc[1] = AMPP_FUNCTION();


--W1_lm_hdata_ack_lc[2] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|lm_hdata_ack_lc[2]
--operation mode is normal

W1_lm_hdata_ack_lc[2] = AMPP_FUNCTION();


--W1_WAIT_WAIT32_lc2 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|WAIT_WAIT32_lc2
--operation mode is normal

W1_WAIT_WAIT32_lc2 = AMPP_FUNCTION(W1_MW_WAIT, W1_MW_DXFR_32, W1_devsel_toR, W1_lm_rdynR);


--W1_MW_WAIT_lc[2] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MW_WAIT_lc[2]
--operation mode is normal

W1_MW_WAIT_lc[2] = AMPP_FUNCTION(W1_MW_WAIT, W1_MW_DXFR_32, W1_devsel_toR, W1_lm_rdynR);


--ix2017_lc is ix2017_lc
--operation mode is normal

ix2017_lc = !dpm_ni2f_reg_sm_3 & !dpm_ni2f_reg_sm_2 & !dpm_ni2f_reg_sm_1 & dpm_ni2f_reg_sm_0;


--W1_last_xfr_lc1 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|last_xfr_lc1
--operation mode is normal

W1_last_xfr_lc1 = AMPP_FUNCTION(W1_latcntr_toR);


--W1_MW_LAST_lc[1] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MW_LAST_lc[1]
--operation mode is normal

W1_MW_LAST_lc[1] = AMPP_FUNCTION(W1_MW_WAIT_32, W1_MW_DXFR_32, W1_last_xfr_lc1, W1_latcntr_toR);


--W1_MW_LAST_lc[2] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MW_LAST_lc[2]
--operation mode is normal

W1_MW_LAST_lc[2] = AMPP_FUNCTION(W1_direct_xfr, W1_MW_WAIT, W1_MW_DXFR, W1_lm_rdynR);


--W1_MW_DXFR_lc[2] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MW_DXFR_lc[2]
--operation mode is normal

W1_MW_DXFR_lc[2] = AMPP_FUNCTION(W1_direct_xfr, W1_MW_WAIT, W1_MW_DXFR, W1_lm_rdynR);


--W1_frame_or_lc3c is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|frame_or_lc3c
--operation mode is normal

W1_frame_or_lc3c = AMPP_FUNCTION();


--W1_frame_or_lc2b is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|frame_or_lc2b
--operation mode is normal

W1_frame_or_lc2b = AMPP_FUNCTION(W1_MR_PXFR);


--W1_MW_DXFR_32_lc[2] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MW_DXFR_32_lc[2]
--operation mode is normal

W1_MW_DXFR_32_lc[2] = AMPP_FUNCTION(W1_MW_LXFR, W1_lm_rdynR, W1_devsel_toR, W1_direct_xfr);


--W1_MW_DXFR_32_lc[3] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MW_DXFR_32_lc[3]
--operation mode is normal

W1_MW_DXFR_32_lc[3] = AMPP_FUNCTION(W1_MW_HOLD, W1_devsel_toR);


--W1_MW_LXFR_lc[3] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MW_LXFR_lc[3]
--operation mode is normal

W1_MW_LXFR_lc[3] = AMPP_FUNCTION();


--W1_irdy_or_lc[2] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|irdy_or_lc[2]
--operation mode is normal

W1_irdy_or_lc[2] = AMPP_FUNCTION();


--W1_$00070 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00070
--operation mode is normal

W1_$00070 = AMPP_FUNCTION(W1_devsel_toR);


--Z1_lt_hdata_ack_r_prn[1] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|lt_hdata_ack_r_prn[1]
--operation mode is normal

Z1_lt_hdata_ack_r_prn[1] = AMPP_FUNCTION(U1_ad_ir_address[2]);


--W1_MR_LWAIT_lc1 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MR_LWAIT_lc1
--operation mode is normal

W1_MR_LWAIT_lc1 = AMPP_FUNCTION(W1_MR_PXFR, W1_devsel_toR);


--W1_MR_LLXFR_r2_d_lc1 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MR_LLXFR_r2_d_lc1
--operation mode is normal

W1_MR_LLXFR_r2_d_lc1 = AMPP_FUNCTION();


--Z1_LR_PXFR_32_lc[2] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|LR_PXFR_32_lc[2]
--operation mode is normal

Z1_LR_PXFR_32_lc[2] = AMPP_FUNCTION(Z1_lt_rdynR, Z1_LR_PXFR, Z1_direct_xfr, Z1_TS_DISC);


--W1_MW_WAIT_32_lc[1] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MW_WAIT_32_lc[1]
--operation mode is normal

W1_MW_WAIT_32_lc[1] = AMPP_FUNCTION(W1_MW_DXFR_32, W1_lm_rdynR, W1_last_xfr_lc1);


--W1_MR_PXFR_lc2 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MR_PXFR_lc2
--operation mode is normal

W1_MR_PXFR_lc2 = AMPP_FUNCTION();


--Z1_LR_PXFR_lc[2] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|LR_PXFR_lc[2]
--operation mode is normal

Z1_LR_PXFR_lc[2] = AMPP_FUNCTION(Z1_LR_PXFR, Z1_lt_rdynR, Z1_TS_DISC);


--W1_req64_or_lc[1] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|req64_or_lc[1]
--operation mode is normal

W1_req64_or_lc[1] = AMPP_FUNCTION();


--W1_req64_or_lc[3] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|req64_or_lc[3]
--operation mode is normal

W1_req64_or_lc[3] = AMPP_FUNCTION();


--W1_req64_or_lc[2] is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|req64_or_lc[2]
--operation mode is normal

W1_req64_or_lc[2] = AMPP_FUNCTION();


--W1L562 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|lm_ldata_ack_lc[1]~65
--operation mode is normal

W1L562 = AMPP_FUNCTION(W1_MR_IDLE_not, W1_MR_END, W1_MR_LLXFR_r1, W1_MR_LLXFR_r2, W1L32);


--W1L662 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|lm_ldata_ack_lc[2]~66
--operation mode is normal

W1L662 = AMPP_FUNCTION(W1_tgt_64_response_reg, W1L18);


--Z1L911 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|devsel_OR_lc[2]~10
--operation mode is normal

Z1L911 = AMPP_FUNCTION(Z1_TS_ADR_CLMD, Z1L61);


--W1L92 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00169~31
--operation mode is normal

W1L92 = AMPP_FUNCTION(W1_MW_LXFR, W1_direct_xfr, W1_lm_rdynR, W1L03);


--Z1L523 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|stop_or_lc[3]~44
--operation mode is normal

Z1L523 = AMPP_FUNCTION(Z1L323, Z1L85);


--Z1L363 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|trdy_OR_lc[6]~73
--operation mode is normal

Z1L363 = AMPP_FUNCTION(Z1_LW_LXFR, Z1_TS_DXFR, dpm_dec_reg_LT_RDY_n_pci, Z1L02);


--Z1L241 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|LR_IDLE_lc1~33
--operation mode is normal

Z1L241 = AMPP_FUNCTION(Z1_retry, Z1L53);


--Z1L482 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|LW_IDLE_lc1~37
--operation mode is normal

Z1L482 = AMPP_FUNCTION(dpm_dec_reg_LT_RDY_n_pci, Z1L52);


--Z1L61 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|$00165~10
--operation mode is normal

Z1L61 = AMPP_FUNCTION(Z1_trdy_OR_NOT, Z1_TS_DXFR, Z1L45);


--Z1L02 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|$00182~10
--operation mode is normal

Z1L02 = AMPP_FUNCTION(Z1_lt_rdynR, Z1_LR_PXFR, Z1_TS_DISC, Z1L65);


--Z1L941 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|LR_LXFR_lc[3]~86
--operation mode is normal

Z1L941 = AMPP_FUNCTION(Z1_lt_ldata_ack_r, Z1_lt_rdynR, Z1_direct_xfr, Z1L63);


--Z1L292 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|LW_LXFR_lc[1]~75
--operation mode is normal

Z1L292 = AMPP_FUNCTION(dpm_dec_reg_LT_RDY_n_pci, Z1L62);


--Z1L083 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|TS_DXFR_d_lc[3]~44
--operation mode is normal

Z1L083 = AMPP_FUNCTION(Z1_cfg_cyc, Z1_targ_burst_lc, Z1L86);


--Z1L423 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|stop_or_lc[2]~45
--operation mode is normal

Z1L423 = AMPP_FUNCTION(Z1_retry, Z1L75);


--Z1L323 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|stop_or_lc[1]~46
--operation mode is normal

Z1L323 = AMPP_FUNCTION(Z1_TS_DISC, Z1L023);


--Z1L561 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|LR_PXFR_lc[1]~44
--operation mode is normal

Z1L561 = AMPP_FUNCTION(Z1_LR_LXFR, Z1L361);


--Z1L351 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|LR_LXFR_lc[5]~87
--operation mode is normal

Z1L351 = AMPP_FUNCTION(Z1_retry, Z1L73);


--W1L013 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MR_PXFR_r2_d~25
--operation mode is normal

W1L013 = AMPP_FUNCTION(A1L744, W1L45);


--A1L671 is ix2000_cas~0
--operation mode is normal

A1L671 = !ix2000_lc;


--W1L54 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00224~11
--operation mode is normal

W1L54 = AMPP_FUNCTION(W1L2);


--W1L15 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|$00239~1
--operation mode is normal

W1L15 = AMPP_FUNCTION(W1L04);


--Z1L64 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_t:trg|$00232~1
--operation mode is normal

Z1L64 = AMPP_FUNCTION(Z1L15);


--R1L4 is nififo:dpm_ni2f_fifo_n|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|altdpram:dpram4|q[0]~0
--operation mode is normal

R1L4 = !M1_flx10ke_lcell35;


--R2L4 is nififo:dpm_ni2f_fifo_p|dcfifo:dcfifo_component|dcfifo_n2r:auto_generated|altdpram:dpram4|q[0]~0
--operation mode is normal

R2L4 = !M2_flx10ke_lcell35;


--~GND is ~GND
--operation mode is normal

~GND = GND;


--ADC1_D[7] is ADC1_D[7]
--operation mode is input

ADC1_D[7] = INPUT();


--ADC2_D[1] is ADC2_D[1]
--operation mode is input

ADC2_D[1] = INPUT();


--ADC2_D[3] is ADC2_D[3]
--operation mode is input

ADC2_D[3] = INPUT();


--LVDS_in[0] is LVDS_in[0]
--operation mode is input

LVDS_in[0] = INPUT();


--LVDS_in[1] is LVDS_in[1]
--operation mode is input

LVDS_in[1] = INPUT();


--LVDS_in[2] is LVDS_in[2]
--operation mode is input

LVDS_in[2] = INPUT();


--LVDS_in[3] is LVDS_in[3]
--operation mode is input

LVDS_in[3] = INPUT();


--pci_lockn is pci_lockn
--operation mode is input

pci_lockn = INPUT();


--pci_rstn is pci_rstn
--operation mode is input

pci_rstn = INPUT();


--CLK50M is CLK50M
--operation mode is input

CLK50M = INPUT();


--pci_clk is pci_clk
--operation mode is input

pci_clk = INPUT();


--ADC1_D[0] is ADC1_D[0]
--operation mode is input

ADC1_D[0] = INPUT();


--ADC2_D[2] is ADC2_D[2]
--operation mode is input

ADC2_D[2] = INPUT();


--ADC1_D[1] is ADC1_D[1]
--operation mode is input

ADC1_D[1] = INPUT();


--pci_gntn is pci_gntn
--operation mode is input

pci_gntn = INPUT();


--ADC1_D[2] is ADC1_D[2]
--operation mode is input

ADC1_D[2] = INPUT();


--ADC1_D[3] is ADC1_D[3]
--operation mode is input

ADC1_D[3] = INPUT();


--ADC1_D[4] is ADC1_D[4]
--operation mode is input

ADC1_D[4] = INPUT();


--ADC1_D[5] is ADC1_D[5]
--operation mode is input

ADC1_D[5] = INPUT();


--ADC1_D[6] is ADC1_D[6]
--operation mode is input

ADC1_D[6] = INPUT();


--ADC2_D[0] is ADC2_D[0]
--operation mode is input

ADC2_D[0] = INPUT();


--pci_idsel is pci_idsel
--operation mode is input

pci_idsel = INPUT();


--ADC2oD[4] is ADC2oD[4]
--operation mode is output

ADC2oD[4] = OUTPUT(!dpm_dec_reg_rdata_LED_8);


--ADC2oD[5] is ADC2oD[5]
--operation mode is output

ADC2oD[5] = OUTPUT(GND);


--ADC2oD[6] is ADC2oD[6]
--operation mode is output

ADC2oD[6] = OUTPUT(dpm_ni2f_reg_not_empty);


--ADC2oD[7] is ADC2oD[7]
--operation mode is output

ADC2oD[7] = OUTPUT(GND);


--ADC_OEn is ADC_OEn
--operation mode is output

ADC_OEn = OUTPUT(VCC);


--KCLK is KCLK
--operation mode is output

KCLK = OUTPUT(!dpm_ni2f_reg_not_empty);


--KDAT is KDAT
--operation mode is output

KDAT = OUTPUT(dpm_ni2f_reg_not_empty);


--LED_GRN is LED_GRN
--operation mode is output

LED_GRN = OUTPUT(!dpm_ni2f_reg_not_empty);


--LED_RED is LED_RED
--operation mode is output

LED_RED = OUTPUT(dpm_ni2f_reg_not_empty);


--LVDS_EN is LVDS_EN
--operation mode is output

LVDS_EN = OUTPUT(VCC);


--LVDS_out[0] is LVDS_out[0]
--operation mode is output

LVDS_out[0] = OUTPUT(dpm_ni2f_reg_cdata_0);


--LVDS_out[1] is LVDS_out[1]
--operation mode is output

LVDS_out[1] = OUTPUT(dpm_ni2f_reg_cdata_1);


--LVDS_out[2] is LVDS_out[2]
--operation mode is output

LVDS_out[2] = OUTPUT(SRAM_IO_0);


--LVDS_out[3] is LVDS_out[3]
--operation mode is output

LVDS_out[3] = OUTPUT(SRAM_IO_1);


--MCLK is MCLK
--operation mode is output

MCLK = OUTPUT(!dpm_ni2f_reg_not_empty);


--MDAT is MDAT
--operation mode is output

MDAT = OUTPUT(dpm_ni2f_reg_not_empty);


--pci_ad_0 is pci_ad_0
--operation mode is bidir

pci_ad_0 = pci_ad[0];

--pci_ad[0] is pci_ad[0]
--operation mode is bidir

pci_ad[0]_tri_out = TRI(U1_low_ad_or[0], U1_ad_tri_oe);
pci_ad[0] = BIDIR(pci_ad[0]_tri_out);


--pci_ad_1 is pci_ad_1
--operation mode is bidir

pci_ad_1 = pci_ad[1];

--pci_ad[1] is pci_ad[1]
--operation mode is bidir

pci_ad[1]_tri_out = TRI(U1_low_ad_or[1], U1_ad_tri_oe);
pci_ad[1] = BIDIR(pci_ad[1]_tri_out);


--pci_ad_2 is pci_ad_2
--operation mode is bidir

pci_ad_2 = pci_ad[2];

--pci_ad[2] is pci_ad[2]
--operation mode is bidir

pci_ad[2]_tri_out = TRI(U1_low_ad_or[2], U1_ad_tri_oe);
pci_ad[2] = BIDIR(pci_ad[2]_tri_out);


--pci_ad_3 is pci_ad_3
--operation mode is bidir

pci_ad_3 = pci_ad[3];

--pci_ad[3] is pci_ad[3]
--operation mode is bidir

pci_ad[3]_tri_out = TRI(U1_low_ad_or[3], U1_ad_tri_oe);
pci_ad[3] = BIDIR(pci_ad[3]_tri_out);


--pci_ad_4 is pci_ad_4
--operation mode is bidir

pci_ad_4 = pci_ad[4];

--pci_ad[4] is pci_ad[4]
--operation mode is bidir

pci_ad[4]_tri_out = TRI(U1_low_ad_or[4], U1_ad_tri_oe);
pci_ad[4] = BIDIR(pci_ad[4]_tri_out);


--pci_ad_5 is pci_ad_5
--operation mode is bidir

pci_ad_5 = pci_ad[5];

--pci_ad[5] is pci_ad[5]
--operation mode is bidir

pci_ad[5]_tri_out = TRI(U1_low_ad_or[5], U1_ad_tri_oe);
pci_ad[5] = BIDIR(pci_ad[5]_tri_out);


--pci_ad_6 is pci_ad_6
--operation mode is bidir

pci_ad_6 = pci_ad[6];

--pci_ad[6] is pci_ad[6]
--operation mode is bidir

pci_ad[6]_tri_out = TRI(U1_low_ad_or[6], U1_ad_tri_oe);
pci_ad[6] = BIDIR(pci_ad[6]_tri_out);


--pci_ad_7 is pci_ad_7
--operation mode is bidir

pci_ad_7 = pci_ad[7];

--pci_ad[7] is pci_ad[7]
--operation mode is bidir

pci_ad[7]_tri_out = TRI(U1_low_ad_or[7], U1_ad_tri_oe);
pci_ad[7] = BIDIR(pci_ad[7]_tri_out);


--pci_ad_8 is pci_ad_8
--operation mode is bidir

pci_ad_8 = pci_ad[8];

--pci_ad[8] is pci_ad[8]
--operation mode is bidir

pci_ad[8]_tri_out = TRI(U1_low_ad_or[8], U1_ad_tri_oe);
pci_ad[8] = BIDIR(pci_ad[8]_tri_out);


--pci_ad_9 is pci_ad_9
--operation mode is bidir

pci_ad_9 = pci_ad[9];

--pci_ad[9] is pci_ad[9]
--operation mode is bidir

pci_ad[9]_tri_out = TRI(U1_low_ad_or[9], U1_ad_tri_oe);
pci_ad[9] = BIDIR(pci_ad[9]_tri_out);


--pci_ad_10 is pci_ad_10
--operation mode is bidir

pci_ad_10 = pci_ad[10];

--pci_ad[10] is pci_ad[10]
--operation mode is bidir

pci_ad[10]_tri_out = TRI(U1_low_ad_or[10], U1_ad_tri_oe);
pci_ad[10] = BIDIR(pci_ad[10]_tri_out);


--pci_ad_11 is pci_ad_11
--operation mode is bidir

pci_ad_11 = pci_ad[11];

--pci_ad[11] is pci_ad[11]
--operation mode is bidir

pci_ad[11]_tri_out = TRI(U1_low_ad_or[11], U1_ad_tri_oe);
pci_ad[11] = BIDIR(pci_ad[11]_tri_out);


--pci_ad_12 is pci_ad_12
--operation mode is bidir

pci_ad_12 = pci_ad[12];

--pci_ad[12] is pci_ad[12]
--operation mode is bidir

pci_ad[12]_tri_out = TRI(U1_low_ad_or[12], U1_ad_tri_oe);
pci_ad[12] = BIDIR(pci_ad[12]_tri_out);


--pci_ad_13 is pci_ad_13
--operation mode is bidir

pci_ad_13 = pci_ad[13];

--pci_ad[13] is pci_ad[13]
--operation mode is bidir

pci_ad[13]_tri_out = TRI(U1_low_ad_or[13], U1_ad_tri_oe);
pci_ad[13] = BIDIR(pci_ad[13]_tri_out);


--pci_ad_14 is pci_ad_14
--operation mode is bidir

pci_ad_14 = pci_ad[14];

--pci_ad[14] is pci_ad[14]
--operation mode is bidir

pci_ad[14]_tri_out = TRI(U1_low_ad_or[14], U1_ad_tri_oe);
pci_ad[14] = BIDIR(pci_ad[14]_tri_out);


--pci_ad_15 is pci_ad_15
--operation mode is bidir

pci_ad_15 = pci_ad[15];

--pci_ad[15] is pci_ad[15]
--operation mode is bidir

pci_ad[15]_tri_out = TRI(U1_low_ad_or[15], U1_ad_tri_oe);
pci_ad[15] = BIDIR(pci_ad[15]_tri_out);


--pci_ad_16 is pci_ad_16
--operation mode is bidir

pci_ad_16 = pci_ad[16];

--pci_ad[16] is pci_ad[16]
--operation mode is bidir

pci_ad[16]_tri_out = TRI(U1_low_ad_or[16], U1_ad_tri_oe);
pci_ad[16] = BIDIR(pci_ad[16]_tri_out);


--pci_ad_17 is pci_ad_17
--operation mode is bidir

pci_ad_17 = pci_ad[17];

--pci_ad[17] is pci_ad[17]
--operation mode is bidir

pci_ad[17]_tri_out = TRI(U1_low_ad_or[17], U1_ad_tri_oe);
pci_ad[17] = BIDIR(pci_ad[17]_tri_out);


--pci_ad_18 is pci_ad_18
--operation mode is bidir

pci_ad_18 = pci_ad[18];

--pci_ad[18] is pci_ad[18]
--operation mode is bidir

pci_ad[18]_tri_out = TRI(U1_low_ad_or[18], U1_ad_tri_oe);
pci_ad[18] = BIDIR(pci_ad[18]_tri_out);


--pci_ad_19 is pci_ad_19
--operation mode is bidir

pci_ad_19 = pci_ad[19];

--pci_ad[19] is pci_ad[19]
--operation mode is bidir

pci_ad[19]_tri_out = TRI(U1_low_ad_or[19], U1_ad_tri_oe);
pci_ad[19] = BIDIR(pci_ad[19]_tri_out);


--pci_ad_20 is pci_ad_20
--operation mode is bidir

pci_ad_20 = pci_ad[20];

--pci_ad[20] is pci_ad[20]
--operation mode is bidir

pci_ad[20]_tri_out = TRI(U1_low_ad_or[20], U1_ad_tri_oe);
pci_ad[20] = BIDIR(pci_ad[20]_tri_out);


--pci_ad_21 is pci_ad_21
--operation mode is bidir

pci_ad_21 = pci_ad[21];

--pci_ad[21] is pci_ad[21]
--operation mode is bidir

pci_ad[21]_tri_out = TRI(U1_low_ad_or[21], U1_ad_tri_oe);
pci_ad[21] = BIDIR(pci_ad[21]_tri_out);


--pci_ad_22 is pci_ad_22
--operation mode is bidir

pci_ad_22 = pci_ad[22];

--pci_ad[22] is pci_ad[22]
--operation mode is bidir

pci_ad[22]_tri_out = TRI(U1_low_ad_or[22], U1_ad_tri_oe);
pci_ad[22] = BIDIR(pci_ad[22]_tri_out);


--pci_ad_23 is pci_ad_23
--operation mode is bidir

pci_ad_23 = pci_ad[23];

--pci_ad[23] is pci_ad[23]
--operation mode is bidir

pci_ad[23]_tri_out = TRI(U1_low_ad_or[23], U1_ad_tri_oe);
pci_ad[23] = BIDIR(pci_ad[23]_tri_out);


--pci_ad_24 is pci_ad_24
--operation mode is bidir

pci_ad_24 = pci_ad[24];

--pci_ad[24] is pci_ad[24]
--operation mode is bidir

pci_ad[24]_tri_out = TRI(U1_low_ad_or[24], U1_ad_tri_oe);
pci_ad[24] = BIDIR(pci_ad[24]_tri_out);


--pci_ad_25 is pci_ad_25
--operation mode is bidir

pci_ad_25 = pci_ad[25];

--pci_ad[25] is pci_ad[25]
--operation mode is bidir

pci_ad[25]_tri_out = TRI(U1_low_ad_or[25], U1_ad_tri_oe);
pci_ad[25] = BIDIR(pci_ad[25]_tri_out);


--pci_ad_26 is pci_ad_26
--operation mode is bidir

pci_ad_26 = pci_ad[26];

--pci_ad[26] is pci_ad[26]
--operation mode is bidir

pci_ad[26]_tri_out = TRI(U1_low_ad_or[26], U1_ad_tri_oe);
pci_ad[26] = BIDIR(pci_ad[26]_tri_out);


--pci_ad_27 is pci_ad_27
--operation mode is bidir

pci_ad_27 = pci_ad[27];

--pci_ad[27] is pci_ad[27]
--operation mode is bidir

pci_ad[27]_tri_out = TRI(U1_low_ad_or[27], U1_ad_tri_oe);
pci_ad[27] = BIDIR(pci_ad[27]_tri_out);


--pci_ad_28 is pci_ad_28
--operation mode is bidir

pci_ad_28 = pci_ad[28];

--pci_ad[28] is pci_ad[28]
--operation mode is bidir

pci_ad[28]_tri_out = TRI(U1_low_ad_or[28], U1_ad_tri_oe);
pci_ad[28] = BIDIR(pci_ad[28]_tri_out);


--pci_ad_29 is pci_ad_29
--operation mode is bidir

pci_ad_29 = pci_ad[29];

--pci_ad[29] is pci_ad[29]
--operation mode is bidir

pci_ad[29]_tri_out = TRI(U1_low_ad_or[29], U1_ad_tri_oe);
pci_ad[29] = BIDIR(pci_ad[29]_tri_out);


--pci_ad_30 is pci_ad_30
--operation mode is bidir

pci_ad_30 = pci_ad[30];

--pci_ad[30] is pci_ad[30]
--operation mode is bidir

pci_ad[30]_tri_out = TRI(U1_low_ad_or[30], U1_ad_tri_oe);
pci_ad[30] = BIDIR(pci_ad[30]_tri_out);


--pci_ad_31 is pci_ad_31
--operation mode is bidir

pci_ad_31 = pci_ad[31];

--pci_ad[31] is pci_ad[31]
--operation mode is bidir

pci_ad[31]_tri_out = TRI(U1_low_ad_or[31], U1_ad_tri_oe);
pci_ad[31] = BIDIR(pci_ad[31]_tri_out);


--pci_cben_0 is pci_cben_0
--operation mode is bidir

pci_cben_0 = pci_cben[0];

--pci_cben[0] is pci_cben[0]
--operation mode is bidir

pci_cben[0]_tri_out = TRI(U1_low_cben_or[0], !W1_cbe_oer_not);
pci_cben[0] = BIDIR(pci_cben[0]_tri_out);


--pci_cben_1 is pci_cben_1
--operation mode is bidir

pci_cben_1 = pci_cben[1];

--pci_cben[1] is pci_cben[1]
--operation mode is bidir

pci_cben[1]_tri_out = TRI(U1_low_cben_or[1], !W1_cbe_oer_not);
pci_cben[1] = BIDIR(pci_cben[1]_tri_out);


--pci_cben_2 is pci_cben_2
--operation mode is bidir

pci_cben_2 = pci_cben[2];

--pci_cben[2] is pci_cben[2]
--operation mode is bidir

pci_cben[2]_tri_out = TRI(U1_low_cben_or[2], !W1_cbe_oer_not);
pci_cben[2] = BIDIR(pci_cben[2]_tri_out);


--pci_cben_3 is pci_cben_3
--operation mode is bidir

pci_cben_3 = pci_cben[3];

--pci_cben[3] is pci_cben[3]
--operation mode is bidir

pci_cben[3]_tri_out = TRI(U1_low_cben_or[3], !W1_cbe_oer_not);
pci_cben[3] = BIDIR(pci_cben[3]_tri_out);


--A1L034 is pci_devseln~0
--operation mode is bidir

A1L034 = pci_devseln;

--pci_devseln is pci_devseln
--operation mode is bidir

pci_devseln_tri_out = TRI(Z1_devsel_OR_not, Z1_targ_oeR_reg);
pci_devseln = BIDIR(pci_devseln_tri_out);


--A1L234 is pci_framen~0
--operation mode is bidir

A1L234 = pci_framen;

--pci_framen is pci_framen
--operation mode is bidir

pci_framen_tri_out = TRI(W1_frame_or_not, !W1_cbe_oer_not);
pci_framen = BIDIR(pci_framen_tri_out);


--pci_intan is pci_intan
--operation mode is output

pci_intan = OUTPUT(VCC);


--A1L734 is pci_irdyn~0
--operation mode is bidir

A1L734 = pci_irdyn;

--pci_irdyn is pci_irdyn
--operation mode is bidir

pci_irdyn_tri_out = TRI(W1_irdy_or_not, W1_irdy_oer);
pci_irdyn = BIDIR(pci_irdyn_tri_out);


--A1L044 is pci_par~0
--operation mode is bidir

A1L044 = pci_par;

--pci_par is pci_par
--operation mode is bidir

pci_par_tri_out = TRI(U1_par_or, U1_par_oeR);
pci_par = BIDIR(pci_par_tri_out);


--A1L244 is pci_perrn~0
--operation mode is bidir

A1L244 = pci_perrn;

--pci_perrn is pci_perrn
--operation mode is bidir

pci_perrn_tri_out = TRI(X1_perr_or_not, U1_perr_oe_r);
pci_perrn = BIDIR(pci_perrn_tri_out);


--pci_reqn is pci_reqn
--operation mode is output

pci_reqn_tri_out = TRI(!W1_req_or, pci_rstn);
pci_reqn = OUTPUT(pci_reqn_tri_out);


--pci_serrn is pci_serrn
--operation mode is output

pci_serrn_open_drain_out = OPNDRN(!X1_serr_or);
pci_serrn = OUTPUT(pci_serrn_open_drain_out);


--A1L744 is pci_stopn~0
--operation mode is bidir

A1L744 = pci_stopn;

--pci_stopn is pci_stopn
--operation mode is bidir

pci_stopn_tri_out = TRI(Z1_stop_OR_NOT, Z1_targ_oeR_reg);
pci_stopn = BIDIR(pci_stopn_tri_out);


--A1L944 is pci_trdyn~0
--operation mode is bidir

A1L944 = pci_trdyn;

--pci_trdyn is pci_trdyn
--operation mode is bidir

pci_trdyn_tri_out = TRI(Z1_trdy_OR_NOT, Z1_targ_oeR_reg);
pci_trdyn = BIDIR(pci_trdyn_tri_out);


--R7S[7] is R7S[7]
--operation mode is output

R7S[7] = OUTPUT(ix2237_lc);


--R7S[6] is R7S[6]
--operation mode is output

R7S[6] = OUTPUT(ix2236_lc);


--R7S[5] is R7S[5]
--operation mode is output

R7S[5] = OUTPUT(ix2235_lc);


--R7S[4] is R7S[4]
--operation mode is output

R7S[4] = OUTPUT(ix2234_lc);


--R7S[3] is R7S[3]
--operation mode is output

R7S[3] = OUTPUT(ix2233_lc);


--R7S[2] is R7S[2]
--operation mode is output

R7S[2] = OUTPUT(ix2232_lc);


--R7S[1] is R7S[1]
--operation mode is output

R7S[1] = OUTPUT(ix2231_lc);


--R7S_mux is R7S_mux
--operation mode is output

R7S_mux = OUTPUT(sg_reg_mx_q);


--SRAM_AD[0] is SRAM_AD[0]
--operation mode is output

SRAM_AD[0] = OUTPUT(dpm_ni2f_reg_addr_0);


--SRAM_AD[1] is SRAM_AD[1]
--operation mode is output

SRAM_AD[1] = OUTPUT(dpm_ni2f_reg_addr_1);


--SRAM_AD[2] is SRAM_AD[2]
--operation mode is output

SRAM_AD[2] = OUTPUT(dpm_ni2f_reg_addr_2);


--SRAM_AD[3] is SRAM_AD[3]
--operation mode is output

SRAM_AD[3] = OUTPUT(dpm_ni2f_reg_addr_3);


--SRAM_AD[4] is SRAM_AD[4]
--operation mode is output

SRAM_AD[4] = OUTPUT(dpm_ni2f_reg_addr_4);


--SRAM_AD[5] is SRAM_AD[5]
--operation mode is output

SRAM_AD[5] = OUTPUT(dpm_ni2f_reg_addr_5);


--SRAM_AD[6] is SRAM_AD[6]
--operation mode is output

SRAM_AD[6] = OUTPUT(dpm_ni2f_reg_addr_6);


--SRAM_AD[7] is SRAM_AD[7]
--operation mode is output

SRAM_AD[7] = OUTPUT(dpm_ni2f_reg_addr_7);


--SRAM_AD[8] is SRAM_AD[8]
--operation mode is output

SRAM_AD[8] = OUTPUT(dpm_ni2f_reg_addr_8);


--SRAM_AD[9] is SRAM_AD[9]
--operation mode is output

SRAM_AD[9] = OUTPUT(dpm_ni2f_reg_addr_9);


--SRAM_AD[10] is SRAM_AD[10]
--operation mode is output

SRAM_AD[10] = OUTPUT(dpm_ni2f_reg_addr_10);


--SRAM_AD[11] is SRAM_AD[11]
--operation mode is output

SRAM_AD[11] = OUTPUT(dpm_ni2f_reg_addr_11);


--SRAM_AD[12] is SRAM_AD[12]
--operation mode is output

SRAM_AD[12] = OUTPUT(dpm_ni2f_reg_addr_12);


--SRAM_AD[13] is SRAM_AD[13]
--operation mode is output

SRAM_AD[13] = OUTPUT(dpm_ni2f_reg_addr_13);


--SRAM_AD[14] is SRAM_AD[14]
--operation mode is output

SRAM_AD[14] = OUTPUT(dpm_ni2f_reg_addr_14);


--SRAM_AD[15] is SRAM_AD[15]
--operation mode is output

SRAM_AD[15] = OUTPUT(dpm_ni2f_reg_addr_15);


--SRAM_AD[16] is SRAM_AD[16]
--operation mode is output

SRAM_AD[16] = OUTPUT(dpm_ni2f_reg_addr_16);


--SRAM_AD[17] is SRAM_AD[17]
--operation mode is output

SRAM_AD[17] = OUTPUT(dpm_ni2f_reg_addr_17);


--SRAM_BW1n is SRAM_BW1n
--operation mode is output

SRAM_BW1n = OUTPUT(!dpm_ni2f_reg_we_n);


--SRAM_BW2n is SRAM_BW2n
--operation mode is output

SRAM_BW2n = OUTPUT(!dpm_ni2f_reg_we_n);


--SRAM_CEn is SRAM_CEn
--operation mode is output

SRAM_CEn = OUTPUT(!dpm_ni2f_reg_ce_n);


--SRAM_CLK is SRAM_CLK
--operation mode is output

SRAM_CLK = OUTPUT(!dpm_ni2f_reg_clk_sram_i);


--SRAM_IO_0 is SRAM_IO_0
--operation mode is bidir

SRAM_IO_0 = SRAM_IO[0];

--SRAM_IO[0] is SRAM_IO[0]
--operation mode is bidir

SRAM_IO[0]_tri_out = TRI(dpm_ni2f_reg_cdata_0, dpm_ni2f_reg_we_n);
SRAM_IO[0] = BIDIR(SRAM_IO[0]_tri_out);


--SRAM_IO_1 is SRAM_IO_1
--operation mode is bidir

SRAM_IO_1 = SRAM_IO[1];

--SRAM_IO[1] is SRAM_IO[1]
--operation mode is bidir

SRAM_IO[1]_tri_out = TRI(dpm_ni2f_reg_cdata_1, dpm_ni2f_reg_we_n);
SRAM_IO[1] = BIDIR(SRAM_IO[1]_tri_out);


--SRAM_IO_2 is SRAM_IO_2
--operation mode is bidir

SRAM_IO_2 = SRAM_IO[2];

--SRAM_IO[2] is SRAM_IO[2]
--operation mode is bidir

SRAM_IO[2]_tri_out = TRI(dpm_ni2f_reg_cdata_2, dpm_ni2f_reg_we_n);
SRAM_IO[2] = BIDIR(SRAM_IO[2]_tri_out);


--SRAM_IO_3 is SRAM_IO_3
--operation mode is bidir

SRAM_IO_3 = SRAM_IO[3];

--SRAM_IO[3] is SRAM_IO[3]
--operation mode is bidir

SRAM_IO[3]_tri_out = TRI(dpm_ni2f_reg_cdata_3, dpm_ni2f_reg_we_n);
SRAM_IO[3] = BIDIR(SRAM_IO[3]_tri_out);


--SRAM_IO_4 is SRAM_IO_4
--operation mode is bidir

SRAM_IO_4 = SRAM_IO[4];

--SRAM_IO[4] is SRAM_IO[4]
--operation mode is bidir

SRAM_IO[4]_tri_out = TRI(dpm_ni2f_reg_cdata_4, dpm_ni2f_reg_we_n);
SRAM_IO[4] = BIDIR(SRAM_IO[4]_tri_out);


--SRAM_IO_5 is SRAM_IO_5
--operation mode is bidir

SRAM_IO_5 = SRAM_IO[5];

--SRAM_IO[5] is SRAM_IO[5]
--operation mode is bidir

SRAM_IO[5]_tri_out = TRI(dpm_ni2f_reg_cdata_5, dpm_ni2f_reg_we_n);
SRAM_IO[5] = BIDIR(SRAM_IO[5]_tri_out);


--SRAM_IO_6 is SRAM_IO_6
--operation mode is bidir

SRAM_IO_6 = SRAM_IO[6];

--SRAM_IO[6] is SRAM_IO[6]
--operation mode is bidir

SRAM_IO[6]_tri_out = TRI(dpm_ni2f_reg_cdata_6, dpm_ni2f_reg_we_n);
SRAM_IO[6] = BIDIR(SRAM_IO[6]_tri_out);


--SRAM_IO_7 is SRAM_IO_7
--operation mode is bidir

SRAM_IO_7 = SRAM_IO[7];

--SRAM_IO[7] is SRAM_IO[7]
--operation mode is bidir

SRAM_IO[7]_tri_out = TRI(dpm_ni2f_reg_cdata_7, dpm_ni2f_reg_we_n);
SRAM_IO[7] = BIDIR(SRAM_IO[7]_tri_out);


--SRAM_IO_8 is SRAM_IO_8
--operation mode is bidir

SRAM_IO_8 = SRAM_IO[8];

--SRAM_IO[8] is SRAM_IO[8]
--operation mode is bidir

SRAM_IO[8]_tri_out = TRI(dpm_ni2f_reg_cdata_8, dpm_ni2f_reg_we_n);
SRAM_IO[8] = BIDIR(SRAM_IO[8]_tri_out);


--SRAM_IO_9 is SRAM_IO_9
--operation mode is bidir

SRAM_IO_9 = SRAM_IO[9];

--SRAM_IO[9] is SRAM_IO[9]
--operation mode is bidir

SRAM_IO[9]_tri_out = TRI(dpm_ni2f_reg_cdata_9, dpm_ni2f_reg_we_n);
SRAM_IO[9] = BIDIR(SRAM_IO[9]_tri_out);


--SRAM_IO_10 is SRAM_IO_10
--operation mode is bidir

SRAM_IO_10 = SRAM_IO[10];

--SRAM_IO[10] is SRAM_IO[10]
--operation mode is bidir

SRAM_IO[10]_tri_out = TRI(dpm_ni2f_reg_cdata_10, dpm_ni2f_reg_we_n);
SRAM_IO[10] = BIDIR(SRAM_IO[10]_tri_out);


--SRAM_IO_11 is SRAM_IO_11
--operation mode is bidir

SRAM_IO_11 = SRAM_IO[11];

--SRAM_IO[11] is SRAM_IO[11]
--operation mode is bidir

SRAM_IO[11]_tri_out = TRI(dpm_ni2f_reg_cdata_11, dpm_ni2f_reg_we_n);
SRAM_IO[11] = BIDIR(SRAM_IO[11]_tri_out);


--SRAM_IO_12 is SRAM_IO_12
--operation mode is bidir

SRAM_IO_12 = SRAM_IO[12];

--SRAM_IO[12] is SRAM_IO[12]
--operation mode is bidir

SRAM_IO[12]_tri_out = TRI(dpm_ni2f_reg_cdata_12, dpm_ni2f_reg_we_n);
SRAM_IO[12] = BIDIR(SRAM_IO[12]_tri_out);


--SRAM_IO_13 is SRAM_IO_13
--operation mode is bidir

SRAM_IO_13 = SRAM_IO[13];

--SRAM_IO[13] is SRAM_IO[13]
--operation mode is bidir

SRAM_IO[13]_tri_out = TRI(dpm_ni2f_reg_cdata_13, dpm_ni2f_reg_we_n);
SRAM_IO[13] = BIDIR(SRAM_IO[13]_tri_out);


--SRAM_IO_14 is SRAM_IO_14
--operation mode is bidir

SRAM_IO_14 = SRAM_IO[14];

--SRAM_IO[14] is SRAM_IO[14]
--operation mode is bidir

SRAM_IO[14]_tri_out = TRI(dpm_ni2f_reg_cdata_14, dpm_ni2f_reg_we_n);
SRAM_IO[14] = BIDIR(SRAM_IO[14]_tri_out);


--SRAM_IO_15 is SRAM_IO_15
--operation mode is bidir

SRAM_IO_15 = SRAM_IO[15];

--SRAM_IO[15] is SRAM_IO[15]
--operation mode is bidir

SRAM_IO[15]_tri_out = TRI(dpm_ni2f_reg_cdata_15, dpm_ni2f_reg_we_n);
SRAM_IO[15] = BIDIR(SRAM_IO[15]_tri_out);


--SRAM_IO[16] is SRAM_IO[16]
--operation mode is bidir

SRAM_IO[16]_open_drain_out = OPNDRN(!dpm_ni2f_reg_we_n);
SRAM_IO[16] = BIDIR(SRAM_IO[16]_open_drain_out);


--SRAM_IO[17] is SRAM_IO[17]
--operation mode is bidir

SRAM_IO[17]_open_drain_out = OPNDRN(!dpm_ni2f_reg_we_n);
SRAM_IO[17] = BIDIR(SRAM_IO[17]_open_drain_out);


--SRAM_OEn is SRAM_OEn
--operation mode is output

SRAM_OEn = OUTPUT(!dpm_ni2f_reg_re_n);


--A1L931 is dpm_ni2f_reg_sreset120~1
--operation mode is normal

A1L931 = !dpm_ni2f_reg_sreset120;


--W1L413 is pci_contr:pci|pci_contr_params:pci_contr_params_component|pci_mt64:inst|pcimt64_m:mstr|MS_ADR~69
--operation mode is normal

W1L413 = AMPP_FUNCTION(W1_MS_ADR);