d:\LS2004a_30\bin\win32\spectrum -file read_top_trap_pci.tcl -logfile \ REPORTS/compile_top_trap_pci.txt ------------------------------------------------- LeonardoSpectrum Level 3 - 2004a.30 (Release Production Release, compiled Apr 1 2004 at 03:52:06) Copyright 1990-2004 Mentor Graphics. All rights reserved. Portions copyright 1991-2004 Compuware Corporation. Checking Security ... Info, Working Directory is now 'K:/tiserv/ni_sram' Info, Log file moved to new working directory Info: setting extract_ram to false -- Reading file d:\LS2004a_30\\data\standard.vhd for unit standard -- Loading package standard into library std -- Reading vhdl file K:/tiserv/ni_sram/SRC/tsr_translate.vhd into library work -- Reading file d:\LS2004a_30\\data\std_1164.vhd for unit STD_LOGIC_1164 -- Loading package std_logic_1164 into library IEEE -- Loading entity tsr_translate into library work -- Loading architecture a of tsr_translate into library work -- Reading vhdl file K:/tiserv/ni_sram/SRC/decoder.vhd into library work -- Loading entity decoder into library work -- Loading architecture a of decoder into library work "K:/tiserv/ni_sram/SRC/decoder.vhd",line 25: Warning, input rdata_rdy is never used. -- Reading vhdl file K:/tiserv/ni_sram/SRC/s7segm.vhd into library work -- Searching for SYNOPSYS package STD_LOGIC_ARITH.. -- Reading file d:\LS2004a_30\\data\syn_arit.vhd for unit STD_LOGIC_ARITH -- Loading package std_logic_arith into library IEEE -- Searching for SYNOPSYS package STD_LOGIC_UNSIGNED.. -- Reading file d:\LS2004a_30\\data\syn_unsi.vhd for unit STD_LOGIC_UNSIGNED -- Loading package STD_LOGIC_UNSIGNED into library IEEE -- Loading entity s7segm into library work -- Loading architecture angel of s7segm into library work -- Reading vhdl file K:/tiserv/ni_sram/SRC/dbl7seg.vhd into library work -- Loading entity dbl7seg into library work -- Loading architecture angel of dbl7seg into library work -- Reading vhdl file K:/tiserv/ni_sram/SRC/ni2fifo.vhd into library work -- Reading file d:\LS2004a_30\\lib\lpm_components.vhd for unit lpm_components -- Loading package LPM_COMPONENTS into library lpm -- Loading entity ni2fifo into library work "K:/tiserv/ni_sram/SRC/ni2fifo.vhd",line 53: Info, Enumerated type sm_type with 12 elements encoded as onehot. Encodings for sm_type values value sm_type[11-0] ============================== idle -----------1 fifo_rd ----------1- fifo_st ---------1-- sram_A --------1--- sram_Ae -------1---- sram_A1 ------1----- sram_A1e -----1------ sram_D ----1------- sram_De ---1-------- sram_D1 --1--------- sram_D1e -1---------- sram_fin 1----------- -- Loading architecture a of ni2fifo into library work "K:/tiserv/ni_sram/SRC/ni2fifo.vhd",line 66: Warning, signal sram_rdy is never used. -- Reading vhdl file K:/tiserv/ni_sram/SRC/trap_dpm.vhd into library work -- Loading entity trap_dpm into library work -- Loading architecture a of trap_dpm into library work "K:/tiserv/ni_sram/SRC/trap_dpm.vhd",line 132: Warning, signal sel_s is never used. "K:/tiserv/ni_sram/SRC/trap_dpm.vhd",line 133: Warning, signal sel_p is never used. -- Reading vhdl file K:/tiserv/ni_sram/SRC/top_trap_pci.vhd into library work -- Loading entity top_trap_pci into library work -- Loading architecture a of top_trap_pci into library work "K:/tiserv/ni_sram/SRC/top_trap_pci.vhd",line 18: Warning, inout pci_ad is used as output only. "K:/tiserv/ni_sram/SRC/top_trap_pci.vhd",line 19: Warning, inout pci_cben is used as output only. "K:/tiserv/ni_sram/SRC/top_trap_pci.vhd",line 22: Warning, input pci_lockn is never used. "K:/tiserv/ni_sram/SRC/top_trap_pci.vhd",line 27: Warning, input LVDS_in is never used. -- Compiling root entity top_trap_pci(a) "K:/tiserv/ni_sram/SRC/top_trap_pci.vhd",line 157: Warning, component GLOBAL has no visible entity binding. -- Compiling entity dbl7seg(angel) -- Compiling entity s7segm(angel) -- Compiling entity trap_dpm(a) "K:/tiserv/ni_sram/SRC/trap_dpm.vhd",line 102: Warning, component lpm_counter has no visible entity binding. -- Compiling entity decoder_32(a) -- Compiling entity tsr_translate(a) -- Compiling entity ni2fifo(a) "K:/tiserv/ni_sram/SRC/ni2fifo.vhd",line 39: Warning, component nififo has no visible entity binding. "K:/tiserv/ni_sram/SRC/ni2fifo.vhd",line 201: Warning, others clause is never selected. "K:/tiserv/ni_sram/SRC/ni2fifo.vhd",line 123: Warning, rdreq_fifo is not assigned under reset; need loops to preserve its value. "K:/tiserv/ni_sram/SRC/ni2fifo.vhd",line 123: Warning, addr is not assigned under reset; need loops to preserve its value. "K:/tiserv/ni_sram/SRC/ni2fifo.vhd",line 223: Info, conditions are mutually exclusive; resolve without priority. "K:/tiserv/ni_sram/SRC/ni2fifo.vhd",line 296: Warning, rcounter should be declared on the sensitivity list of the process. "K:/tiserv/ni_sram/SRC/top_trap_pci.vhd",line 61: Warning, component pci_contr has no visible entity binding. Warning, Multiple drivers on nx752. -- Boundary optimization. -- Boundary optimization. -- Start pre-optimization for design .work.s7segm.angel -- Start pre-optimization for design .work.dbl7seg.angel_unfold_1539 -- Start pre-optimization for design .work.decoder_32.a_unfold_994 -- Start pre-optimization for design .work.ni2fifo.a_unfold_1029 "K:/tiserv/ni_sram/SRC/ni2fifo.vhd", line 224:Info, Inferred counter instance 'tout' of type 'counter_up_sclear_clock_clk_en_11' "K:/tiserv/ni_sram/SRC/ni2fifo.vhd", line 247:Info, Inferred counter instance 'naddr' of type 'counter_up_cnt_en_sclear_clock_18' "K:/tiserv/ni_sram/SRC/ni2fifo.vhd", line 250:Info, Inferred counter instance 'naddr_dup_2' of type 'counter_up_sclear_clock_clk_en_6' -- Start pre-optimization for design .work.trap_dpm.a_unfold_1316 -- Start pre-optimization for design .work.top_trap_pci.a -- Start pre-optimization for design .work.s7segm.angel -- Start pre-optimization for design .work.dbl7seg.angel_unfold_1539 -- Start pre-optimization for design .work.decoder_32.a_unfold_994 -- Start pre-optimization for design .work.ni2fifo.a_unfold_1029 -- Start pre-optimization for design .work.trap_dpm.a_unfold_1316 -- Start pre-optimization for design .work.top_trap_pci.a Info: setting part to EP1K100QC208 Info: setting process to 2 Reading library file `d:\LS2004a_30\\lib\acex1.syn`... Library version = 4.5 Delays assume: Process=2 Info: setting encoding to auto Using default wire table: STD-1 -- Start optimization for design .work.top_trap_pci.a Using default wire table: STD-1 est est Pass LCs Delay DFFs TRIs PIs POs --CPU-- min:sec 1 332 14 116 0 14 111 00:02 2 290 14 116 0 14 111 00:01 3 315 14 116 0 14 111 00:02 4 315 14 116 0 14 111 00:07 Info, Pass 2 was selected as best. Info: setting opt_best_result to 3991.609300 Info: setting opt_best_pass to 2 Using default wire table: STD-1 -- Start timing optimization for design .work.top_trap_pci.a No critical paths to optimize at this level AutoWrite args are : NETLIST/top_trap_pci.edf -- Saving the design database in NETLIST/top_trap_pci.xdb -- Writing file NETLIST/top_trap_pci.xdb -- Writing XDB version 1999.1 -- Applying renaming rule 'ALTERA' to database Warning, Renaming will cause your database to change -- Calling set_altera_eqn to set up writing Equations Info: setting edif_eqn_or to + Info: setting edif_eqn_and to Info: setting edif_eqn_not to ' Info: setting edif_eqn_not_is_prefix to FALSE Info: setting edif_function_property to lut_function -- write NETLIST/top_trap_pci.edf -- Writing file NETLIST/top_trap_pci.edf Info, About to call 'setacf' for generating/modifying ACF file Info, 'setacf' done. Error writing acf file NETLIST/top_trap_pci.acf: error renaming "NETLIST/tmp0.acf": no such file or directory Info, Writing batch file 'NETLIST/top_trap_pci.tcl' Info: setting quartus_exec_path to D:\QUARTUS4.0/bin Using default wire table: STD-1