LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

entity reg_clr is
generic(Ndata : Integer := 32);
port (  clk   : in  std_logic;
        ce    : in  std_logic;
        rst_n : in  std_logic;
        d     : in  std_logic_vector(Ndata-1 downto 0);
        q     : out std_logic_vector(Ndata-1 downto 0)
     );
end reg_clr;

architecture RTL of reg_clr is

begin
   process(clk, rst_n)
        begin
           if rst_n = '0' then q <= (others => '0');
           elsif clk'event and clk='1' then
                   if ce='1' then q <= d; end if;
           end if;
        end process;
end RTL;