LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; entity trap_dpm is --GENERIC (Aw : Integer := 10); port ( clk_pci : in std_logic; clk120 : in std_logic; reset_n : in std_logic; -- the bus interface data_in : in std_logic_vector(63 downto 0); addr_in : in std_logic_vector(63 downto 0); LT_TSR : in std_logic_vector(11 downto 0); LT_CMD : in std_logic_vector( 3 downto 0); LT_ACQ_n : in std_logic; L_Ldat_acq_n : in std_logic; LT_RDY_n : out std_logic; data_out : out std_logic_vector(63 downto 0); dis_clk : out std_logic; -- trap strobe : in std_logic; -- incoming DDR strobe signal lvds_data_in : in std_logic_vector( 9 downto 0); -- incoming DDR data sync. to strobe SRAM_CLK : OUT STD_LOGIC; SRAM_WEn : OUT STD_LOGIC; SRAM_OEn : OUT STD_LOGIC; SRAM_CEn : OUT STD_LOGIC; SRAM_AD : OUT STD_LOGIC_VECTOR(17 downto 0); SRAM_Q : in std_logic_vector(15 downto 0); SRAM_D : out std_logic_vector(15 downto 0); not_empty : out std_logic; res_reset_n : out std_logic; data_LED : out std_logic_vector( 9 downto 0) ); end trap_dpm; -------------------------------------------------------------------------------------------------------- -- ARCHITECTURE -------------------------------------------------------------------------------------------------------- architecture a of trap_dpm is component decoder is generic (Nrd : Integer := 32); port( clk_pci : in std_logic; reset_n : in std_logic; data_in_pci : in std_logic_vector(63 downto 0); addr_in_pci : in std_logic_vector(63 downto 0); LT_TSR_pci : in std_logic_vector(11 downto 0); LT_CMD_pci : in std_logic_vector( 3 downto 0); LT_ACQ_n_pci : in std_logic; L_Ldat_acq_n_pci : in std_logic; LT_RDY_n_pci : out std_logic; data_out_pci : out std_logic_vector(63 downto 0); wdata : out std_logic_vector(31 downto 0); word_addr : out std_logic_vector(16 downto 0); Rd_rqni : out std_logic; rdata_trap : in std_logic_vector(Nrd-1 downto 0); raddr_trap : in std_logic_vector(31 downto 0); rdata_rdy : in std_logic; data_LED : out std_logic_vector( 9 downto 0); WE : out std_logic; sel_s : out std_logic_vector( 3 downto 0); sel_p : out std_logic_vector( 3 downto 0); soft_rst_n : out std_logic ); end component; component ni2fifo is port ( reset_n : in std_logic; -- asynchronous reset sreset : in std_logic; -- synchronous reset clk : in std_logic; -- 120 MHz clock strobe : in std_logic; -- incoming DDR strobe signal lvds_data_in : in std_logic_vector( 9 downto 0); -- incoming DDR data sync. to strobe -- to pci interface (decoder) naddr : out std_logic_vector(31 downto 0); pci_rd_req : in std_logic; pci_raddr : in std_logic_vector(16 downto 0); pci_rdy : out std_logic; sram_rdata : out std_logic_vector(31 downto 0); not_empty : out std_logic; -- to SRAM ce_n : out std_logic; we_n : out std_logic; re_n : out std_logic; sram_q : in std_logic_vector(15 downto 0); clk_sram : out std_logic; addr : out std_logic_vector(17 downto 0); wdata : out std_logic_vector(15 downto 0) ); end component; COMPONENT lpm_counter GENERIC (LPM_WIDTH: POSITIVE; LPM_MODULUS: NATURAL := 0; LPM_DIRECTION: STRING := "UNUSED"; LPM_AVALUE: STRING := "UNUSED"; LPM_SVALUE: STRING := "UNUSED"; LPM_PVALUE: STRING := "UNUSED"; LPM_TYPE: STRING := "LPM_COUNTER"; LPM_HINT : STRING := "UNUSED"); PORT (data: IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); clock: IN STD_LOGIC; clk_en, cnt_en, updown: IN STD_LOGIC := '1'; sload, sset, sclr, aload, aset, aclr, cin: IN STD_LOGIC := '0'; cout: OUT STD_LOGIC; --eq: OUT STD_LOGIC_VECTOR (15 DOWNTO 0); q: OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0)); END COMPONENT; signal naddr : std_logic_vector(31 downto 0); signal word_addr : std_logic_vector(16 downto 0); signal rdata : std_logic_vector(31 downto 0); signal data_LED_i : std_logic_vector( 9 downto 0); signal sreset : std_logic; signal hreset_n : std_logic; signal soft_rst_n : std_logic; signal Rd_rqni : std_logic; signal rdata_rdy : std_logic; signal qclkd : std_logic_vector(15 downto 0); signal sel_s : std_logic_vector( 3 downto 0); signal sel_p : std_logic_vector( 3 downto 0); begin cdiv: lpm_counter GENERIC map(LPM_WIDTH => qclkd'length, LPM_DIRECTION => "UP") PORT map( clock => clk_pci, q => qclkd); -- LED mux clock dis_clk <= qclkd(qclkd'high); dec: decoder port map( clk_pci => clk_pci, reset_n => reset_n , data_in_pci => data_in , addr_in_pci => addr_in , LT_TSR_pci => LT_TSR , LT_CMD_pci => LT_CMD , LT_ACQ_n_pci => LT_ACQ_n, L_Ldat_acq_n_pci => L_Ldat_acq_n, LT_RDY_n_pci => LT_RDY_n, data_out_pci => data_out, rdata_rdy => rdata_rdy, Rd_rqni => Rd_rqni, wdata => open , word_addr => word_addr , rdata_trap => rdata , raddr_trap => naddr , data_LED => data_LED_i , sel_p => sel_p , sel_s => sel_s , WE => open , soft_rst_n => soft_rst_n ); data_LED <= data_LED_i; res_reset_n <= soft_rst_n; sreset <= not soft_rst_n; hreset_n <= soft_rst_n and reset_n; ni2f: ni2fifo port map( reset_n => hreset_n, sreset => sreset, clk => clk120, strobe => strobe, lvds_data_in => lvds_data_in, -- to pci interface (decoder) naddr => naddr, pci_rd_req => Rd_rqni, pci_raddr => word_addr, pci_rdy => rdata_rdy, sram_rdata => rdata, not_empty => not_empty, -- to SRAM ce_n => SRAM_CEn, we_n => SRAM_WEn, re_n => SRAM_OEn, sram_q => SRAM_Q, clk_sram => SRAM_CLK, addr => SRAM_AD, wdata => SRAM_D ); end;