library IEEE; use IEEE.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all; LIBRARY lpm; USE lpm.lpm_components.all; entity ni2fifo is port ( reset_n : in std_logic; -- asynchronous reset sreset : in std_logic; -- synchronous reset clk : in std_logic; -- 120 MHz clock strobe : in std_logic; -- incoming DDR strobe signal lvds_data_in : in std_logic_vector( 9 downto 0); -- incoming DDR data sync. to strobe -- to pci interface (decoder) naddr : out std_logic_vector(31 downto 0); pci_rd_req : in std_logic; pci_raddr : in std_logic_vector(16 downto 0); pci_rdy : out std_logic; not_empty : out std_logic; sram_rdata : out std_logic_vector(31 downto 0); -- to SRAM ce_n : out std_logic; we_n : out std_logic; re_n : out std_logic; sram_q : in std_logic_vector(15 downto 0); clk_sram : out std_logic; addr : out std_logic_vector(17 downto 0); wdata : out std_logic_vector(15 downto 0) ); end ni2fifo; architecture a of ni2fifo is component nififo PORT ( data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); wrreq : IN STD_LOGIC ; rdreq : IN STD_LOGIC ; rdclk : IN STD_LOGIC ; wrclk : IN STD_LOGIC ; aclr : IN STD_LOGIC := '0'; q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); rdempty : OUT STD_LOGIC ); end component; type sm_type is (idle, fifo_rd, fifo_st, sram_A, sram_Ae, sram_A1, sram_A1e, sram_D, sram_De, sram_D1, sram_D1e, sram_fin); signal sm : sm_type; signal data_in_sel : std_logic_vector(7 downto 0); signal q_p : std_logic_vector(7 downto 0); signal q_p_cor : std_logic_vector(7 downto 0); signal q_n : std_logic_vector(7 downto 0); signal q_n_cor : std_logic_vector(7 downto 0); signal end_marker1 : std_logic; signal end_marker2 : std_logic; signal end_marker32 : std_logic; signal timeout : std_logic; signal sram_rdy : std_logic; signal clk_sram_i : std_logic; signal sreset120 : std_logic; signal rdreq_fifo : std_logic; signal rdempty : std_logic; signal rdempty_s : std_logic; signal ROB_rdy : std_logic; signal strobe_n : std_logic; signal Log1 : std_logic; signal pci_rd_req_s : std_logic; signal wcounter : std_logic_vector(17 downto 0); signal rcounter : std_logic_vector( 5 downto 0); signal cdata : std_logic_vector(15 downto 0); signal end_data : std_logic_vector(15 downto 0); signal sram_qL : std_logic_vector(15 downto 0); signal sram_qH : std_logic_vector(15 downto 0); signal tout : std_logic_vector(10 downto 0); signal sm_num : std_logic_vector( 3 downto 0); begin strobe_n <= not strobe; Log1 <= '1'; end_data <= (others => '0'); data_in_sel <= lvds_data_in(8) & lvds_data_in(6 downto 0); fifo_n: nififo PORT map ( data => data_in_sel, wrreq => Log1, rdreq => rdreq_fifo, rdclk => clk, wrclk => strobe_n, q => q_n, aclr => sreset120, rdempty => open ); fifo_p: nififo PORT map ( data => data_in_sel, wrreq => Log1, rdreq => rdreq_fifo, rdclk => clk, wrclk => strobe, q => q_p, aclr => sreset120, rdempty => rdempty ); -- rdreq_fifo <= sram_rdy and not rdempty_s; process(clk, reset_n) begin if reset_n = '0' then sm <= idle; sram_rdy <= '0'; pci_rdy <= '0'; ce_n <= '1'; we_n <= '1'; re_n <= '1'; clk_sram_i <= '1'; not_empty <= '0'; rdempty_s <= '1'; elsif clk'event and clk='1' then rdempty_s <= rdempty; ce_n <= '1'; we_n <= '1'; re_n <= '1'; clk_sram_i <= '1'; pci_rdy <= '0'; case sm is when idle => if rdempty_s='0' then sm <= fifo_rd; --rdreq_fifo <= '1'; elsif pci_rd_req_s='1' then sm <= sram_A; addr <= pci_raddr & '0'; end if; when fifo_rd => rdreq_fifo <= not rdempty; if rdreq_fifo='1' then sm <= fifo_st; rdreq_fifo <= '0'; we_n <= '0'; ce_n <= '0'; elsif ROB_rdy='1' then sm <= idle; end if; when fifo_st => sm <= fifo_rd; sram_rdy <= '1'; we_n <= '0'; ce_n <= '0'; addr <= wcounter; -- write address clk_sram_i <= '0'; rdreq_fifo <= not rdempty; when sram_A => addr <= pci_raddr & '0'; clk_sram_i <= '0'; ce_n <= '0'; -- re_n <= '0'; sm <= sram_Ae; when sram_Ae => ce_n <= '0'; -- re_n <= '0'; sm <= sram_A1; when sram_A1 => addr <= pci_raddr & '1'; clk_sram_i <= '0'; ce_n <= '0'; re_n <= '0'; sm <= sram_A1e; when sram_A1e=> ce_n <= '0'; re_n <= '0'; sm <= sram_D; when sram_D => clk_sram_i <= '0'; ce_n <= '0'; re_n <= '0'; sm <= sram_De; when sram_De => ce_n <= '0'; re_n <= '0'; sm <= sram_D1; when sram_D1 => clk_sram_i <= '0'; ce_n <= '0'; re_n <= '0'; sm <= sram_D1e; pci_rdy <= '1'; when sram_D1e=> ce_n <= '0'; re_n <= '0'; sm <= sram_fin; pci_rdy <= '1'; when sram_fin => pci_rdy <= '1'; if pci_rd_req_s='0' then sm <= idle; end if; when others => sm <= idle; end case; if sm /= idle then not_empty <= '1'; elsif sreset='1' then not_empty <= '0'; end if; end if; end process; q_p_cor <= q_p xor "00101010"; q_n_cor <= q_n xor "00101010"; -- q_p_cor <= q_p; -- for simulation -- q_n_cor <= q_n; ROB_rdy <= end_marker32 or timeout; process(clk) begin if clk'event and clk='1' then if sm=fifo_st then tout <= (others => '0'); elsif sm=fifo_rd then tout <= tout + 1; end if; if sm=fifo_st then timeout <= '0'; elsif tout(tout'high)='1' then timeout <= '1'; end if; end if; end process; process(clk) begin if clk'event and clk='1' then -- synchronize the software reset from PCI sreset120 <= sreset; pci_rd_req_s <= pci_rd_req; -- write address counter for SRAM if sreset120='1' then wcounter <= (others => '0'); end_marker1 <= '0'; end_marker2 <= '0'; end_marker32 <= '0'; cdata <= (others => '1'); rcounter <= (others => '0'); elsif sm=fifo_st then wcounter <= wcounter + 1; end if; if sm=sram_D1e then rcounter <= rcounter + 1; end if; -- output signals to SRAM if sm=fifo_st then cdata <= q_p_cor & q_n_cor; -- write data end if; if clk_sram_i = '0' then if cdata = end_data then end_marker1 <= '1'; else end_marker1 <= '0'; end if; end_marker2 <= end_marker1; end_marker32 <= (end_marker1 and end_marker2) or end_marker32; end if; if sm=sram_De then sram_qL <= sram_q; end if; if sm=sram_D1e then sram_qH <= sram_q; end if; end if; end process; with sm select sm_num <= "0000" when idle, "0001" when fifo_rd, "0010" when fifo_st, "0011" when sram_A, "0100" when sram_Ae, "0101" when sram_A1, "0110" when sram_A1e, "0111" when sram_D, "1000" when sram_De, "1001" when sram_D1, "1010" when sram_D1e, "1011" when sram_fin, "1111" when others; -- outputs wdata <= cdata; clk_sram <= clk_sram_i; sram_rdata <= sram_qH & sram_qL; -- status readonly process(end_marker32, wcounter, timeout, sm_num) begin naddr <= (others => '0'); naddr(wcounter'range) <= wcounter; naddr(naddr'high ) <= end_marker32; naddr(naddr'high-1 ) <= timeout; naddr(27 downto 24) <= sm_num; naddr(23 downto 18) <= rcounter; end process; end;