LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; entity decoder is generic (Nrd : Integer := 32); port( clk_pci : in std_logic; reset_n : in std_logic; data_in_pci : in std_logic_vector(63 downto 0); addr_in_pci : in std_logic_vector(63 downto 0); LT_TSR_pci : in std_logic_vector(11 downto 0); LT_CMD_pci : in std_logic_vector( 3 downto 0); LT_ACQ_n_pci : in std_logic; L_Ldat_acq_n_pci : in std_logic; LT_RDY_n_pci : out std_logic; data_out_pci : out std_logic_vector(63 downto 0); wdata : out std_logic_vector(31 downto 0); word_addr : out std_logic_vector(16 downto 0); Rd_rqni : out std_logic; rdata_trap : in std_logic_vector(Nrd-1 downto 0); raddr_trap : in std_logic_vector(31 downto 0); data_LED : out std_logic_vector( 9 downto 0); WE : out std_logic; rdata_rdy : in std_logic; sel_s : out std_logic_vector( 3 downto 0); sel_p : out std_logic_vector( 3 downto 0); soft_rst_n : out std_logic ); end decoder; -------------------------------------------------------------------------------------------------------- -- ARCHITECTURE -------------------------------------------------------------------------------------------------------- architecture a of decoder is component tsr_translate is port( lt_tsr : in STD_LOGIC_VECTOR(11 downto 0); bar_hit : out STD_LOGIC_VECTOR(5 downto 0); exp_rom_hit : out STD_LOGIC; trans64 : out STD_LOGIC; targ_access : out STD_LOGIC; burst_trans : out STD_LOGIC; pxfr : out STD_LOGIC; dac : out STD_LOGIC ); end component; CONSTANT INTERRUPT_ACC : STD_LOGIC_VECTOR(3 downto 0):="0000"; CONSTANT SPECIAL_CYCLE : STD_LOGIC_VECTOR(3 downto 0):="0001"; CONSTANT IO_READ : STD_LOGIC_VECTOR(3 downto 0):="0010"; CONSTANT IO_WRITE : STD_LOGIC_VECTOR(3 downto 0):="0011"; CONSTANT RESERVED_1 : STD_LOGIC_VECTOR(3 downto 0):="0100"; CONSTANT RESERVED_2 : STD_LOGIC_VECTOR(3 downto 0):="0101"; CONSTANT MEM_READ : STD_LOGIC_VECTOR(3 downto 0):="0110"; CONSTANT MEM_WRITE : STD_LOGIC_VECTOR(3 downto 0):="0111"; CONSTANT RESERVED_3 : STD_LOGIC_VECTOR(3 downto 0):="1000"; CONSTANT RESERVED_4 : STD_LOGIC_VECTOR(3 downto 0):="1001"; CONSTANT CONF_READ : STD_LOGIC_VECTOR(3 downto 0):="1010"; CONSTANT CONF_WRITE : STD_LOGIC_VECTOR(3 downto 0):="1011"; CONSTANT MEM_READ_MULT : STD_LOGIC_VECTOR(3 downto 0):="1100"; CONSTANT DAC : STD_LOGIC_VECTOR(3 downto 0):="1101"; CONSTANT MEM_READ_LINE : STD_LOGIC_VECTOR(3 downto 0):="1110"; CONSTANT MEM_WRITE_INV : STD_LOGIC_VECTOR(3 downto 0):="1111"; --signal READorWRITE : std_logic; signal READ : std_logic; signal WRITE : std_logic; signal RST_dec : std_logic; signal bar_hit : std_logic_vector( 5 downto 0); signal rdata_CNF : std_logic_vector(sel_p'length+sel_s'length-1 downto 0); signal rdata_LED : std_logic_vector(data_LED'range); signal WE_conf : std_logic; signal WE_LED : std_logic; --signal CS_scsn_i : std_logic; signal tmp : std_logic; signal tmp1 : std_logic; signal tmp2 : std_logic; signal tmp3 : std_logic; signal wdata_i : std_logic_vector(wdata'range); signal data_out_32pci : std_logic_vector(31 downto 0); begin -- decode the PCI commands with LT_CMD_pci select READ <= '1' when IO_READ | MEM_READ | MEM_READ_MULT | MEM_READ_LINE, '0' when others; with LT_CMD_pci select WRITE <= '1' when IO_WRITE | MEM_WRITE | MEM_WRITE_INV, '0' when others; -- READorWRITE <= READ or WRITE; -- outputs to scsn master WE <= WRITE; wdata_i <= data_in_pci(wdata'range) when L_Ldat_acq_n_pci='0' else data_in_pci(wdata'high+32 downto 32); wdata <= wdata_i; word_addr <= addr_in_pci(18 downto 2); -- read mux process(addr_in_pci, rdata_trap, rdata_CNF, rdata_LED, raddr_trap) begin data_out_32pci <= (others => '0'); case addr_in_pci(19) & addr_in_pci(5 downto 4) is when "100" | "101" | "110" | "111" => data_out_32pci(rdata_trap'range) <= rdata_trap; -- added in 20.10.2004 -- data_out_32pci(27 downto 16) <= raddr_trap; when "001" => data_out_32pci(rdata_LED'range) <= rdata_LED; when "010" => data_out_32pci(rdata_CNF'range) <= rdata_CNF; when "011" => data_out_32pci(raddr_trap'range) <= raddr_trap; when others => data_out_32pci <= (others => '-'); end case; end process; data_out_pci <= data_out_32pci & data_out_32pci; tsr: tsr_translate port map( lt_tsr => LT_TSR_pci, bar_hit => bar_hit, exp_rom_hit => open, trans64 => open, targ_access => open, burst_trans => open, pxfr => open, dac => open ); -- address decoder for internal devices -- read only Rd_rqni <= '1' when addr_in_pci(19) = '1' and LT_ACQ_n_pci='0' and bar_hit(0)='1' and READ='1' else '0'; -- CS_trap <= CS_trap_i; RST_dec <= '1' when addr_in_pci(19)='0' and addr_in_pci(5 downto 4)="00" and LT_ACQ_n_pci='0' and bar_hit(0)='1' and WRITE='1' else '0'; WE_LED <= '1' when addr_in_pci(19)='0' and addr_in_pci(5 downto 4)="01" and LT_ACQ_n_pci='0' and bar_hit(0)='1' and WRITE='1' else '0'; WE_conf <= '1' when addr_in_pci(19)='0' and addr_in_pci(5 downto 4)="10" and LT_ACQ_n_pci='0' and bar_hit(0)='1' and WRITE='1' else '0'; -- synchronize soft reset output to avoid glitches process(clk_pci, reset_n) begin if reset_n = '0' then soft_rst_n <= '0'; elsif clk_pci'event and clk_pci='1' then soft_rst_n <= not RST_dec; end if; end process; -- configuration register and ready output process(clk_pci, reset_n) begin if reset_n = '0' then rdata_CNF <= (others => '0'); rdata_LED <= (others => '0'); LT_RDY_n_pci <= '1'; tmp <= '1'; tmp1 <= '1'; tmp2 <= '1'; tmp3 <= '1'; elsif clk_pci'event and clk_pci='1' then if WE_LED ='1' then rdata_LED <= wdata_i(rdata_LED'range); end if; if WE_conf='1' then rdata_CNF <= wdata_i(rdata_CNF'range); end if; tmp <= not Bar_hit(0); tmp1 <= tmp; tmp2 <= tmp1; tmp3 <= tmp2; LT_RDY_n_pci <= tmp3; -- or not rdata_rdy; end if; end process; sel_p <= rdata_CNF(3 downto 0); sel_s <= rdata_CNF(7 downto 4); data_LED <= rdata_LED; end;