library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

-- $Id: top.vhd 3348 2009-10-12 16:20:01Z angelov $:

entity top is
    Port (
        mclk    : in std_logic;
        -- interface to the cypress USB chip
        pdb     : inout std_logic_vector(7 downto 0);
        astb    : in    std_logic;
        dstb    : in    std_logic;
        pwr     : in    std_logic;
        pwait   : out   std_logic;
        -- interface to the board
        Led     : out   std_logic_vector(7 downto 0);
        Swt     : in    std_logic_vector(7 downto 0);
        pbut    : in    std_logic_vector(3 downto 0)
        );
end top;

 
architecture a of top is

component epp2usr is
    Port (
        mclk    : in std_logic;
        -- interface to the cypress USB chip
        pdb     : inout std_logic_vector(7 downto 0);
        astb    : in std_logic;
        dstb    : in std_logic;
        pwr     : in std_logic;
        pwait   : out std_logic;
        -- interface to the user logic
        din     : in  std_logic_vector(7 downto 0);
        dout    : out std_logic_vector(7 downto 0);
        addr    : out std_logic_vector(3 downto 0);
        we      : out std_logic;
        rd_fin  : out std_logic
        );
end component;


component control is
port (
    clk     : in  std_logic;
    we      : in  std_logic;
    rd_fin  : in  std_logic;
    addr    : in  std_logic_vector( 3 downto 0);
    din     : in  std_logic_vector( 7 downto 0);
    dout    : out std_logic_vector( 7 downto 0);
    raddr   : out std_logic_vector(15 downto 0);
    rdata   : in  std_logic_vector(15 downto 0);
    led     : out std_logic_vector( 7 downto 0);
    pbut    : in  std_logic_vector( 3 downto 0);
    dipsw   : in  std_logic_vector( 7 downto 0);
    d1e1_cnt  : in  std_logic_vector(15 downto 0);
    d1e0_cnt  : in  std_logic_vector(15 downto 0);
    d0e1_cnt  : in  std_logic_vector(15 downto 0)
    );
end component;

component nififo8m 
generic (Na : Integer := 10; Nd : Integer := 16);
        PORT
        (
                data            : IN STD_LOGIC_VECTOR (Nd-1 DOWNTO 0);
                wrreq           : IN STD_LOGIC ;
                rdreq           : IN STD_LOGIC ;
                clk             : IN STD_LOGIC ;
                aclr            : IN STD_LOGIC  := '0';
                q               : OUT STD_LOGIC_VECTOR (Nd-1 DOWNTO 0);
                rdempty         : OUT STD_LOGIC
        );
end component;

signal d1e1_cnt : std_logic_vector(15 downto 0);
signal d1e0_cnt : std_logic_vector(15 downto 0);
signal d0e1_cnt : std_logic_vector(15 downto 0);
signal raddr    : std_logic_vector(15 downto 0);
signal rdata    : std_logic_vector(15 downto 0);

signal dout     : std_logic_vector( 7 downto 0);
signal din      : std_logic_vector( 7 downto 0);
signal addr     : std_logic_vector( 3 downto 0);

signal test_cnt    : std_logic_vector(17 downto 0);
signal fempty      : std_logic;
signal fwr	       : std_logic;
signal frd	       : std_logic;

signal we       : std_logic;
signal rd_fin   : std_logic;

signal rd_fin_d   : std_logic;
signal prog_delay : std_logic_vector( 15 downto 0);
signal Led_top    : std_logic_vector( 7 downto 0);
signal i:integer range 0 to 15;

begin

process(mclk)
begin
if mclk'event and mclk='1' then
	prog_delay(15 downto 1)<=prog_delay(14 downto 0);
	prog_delay(0)<=rd_fin;
end if;
end process;

    d1e1_cnt <= (others => '0');
    d1e0_cnt <= (others => '0');
    d0e1_cnt <= (others => '0');
--    rdata    <= (others => '0');

usb: epp2usr
    Port map(
        mclk    => mclk,
        -- interface to the cypress USB chip
        pdb     => pdb,
        astb    => astb,
        dstb    => dstb,
        pwr     => pwr,
        pwait   => pwait,
        -- interface to the user logic
        din     => din,
        dout    => dout,
        addr    => addr,
        we      => we,
        rd_fin  => rd_fin);

Led<=Led_top;
i<=conv_integer(unsigned(Led_top));
rd_fin_d<=prog_delay(i);

cnt: control
port map(
    clk     => mclk,
    we      => we,
    rd_fin  => rd_fin_d,
    addr    => addr,
    din     => dout,
    dout    => din,
    raddr   => raddr,
    rdata   => rdata,
    led     => led_top,
    pbut    => pbut,
    dipsw   => Swt,
    d1e1_cnt  => d1e1_cnt,
    d1e0_cnt  => d1e0_cnt,
    d0e1_cnt  => d0e1_cnt);
	
fifo: nififo8m 
port map(
data =>test_cnt(15 downto 0),
wrreq=>fwr,
rdreq=>frd,
clk=>mclk,
aclr=>'0',
q=>rdata,
rdempty=>fempty
);

frd<='1' when fwr='0' and fempty='0' else '0';

process(mclk)
begin
if mclk'event and mclk='1' then
	test_cnt<=test_cnt+1;
	if test_cnt>x"003FF" then
		fwr<='0';
	else
		fwr<='1';
	end if;
end if;
end process;


end;