library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all; library UNISIM; use UNISIM.Vcomponents.ALL; -- $Id: top.vhd 3348 2009-10-12 16:20:01Z angelov $: entity top is Port ( mclk : in std_logic; -- interface to the cypress USB chip pdb : inout std_logic_vector(7 downto 0); astb : in std_logic; dstb : in std_logic; pwr : in std_logic; pwait : out std_logic; -- HIROSE connector -- interface to TLK2501 and TX_CLOCK fclk_rx : in std_logic; -- fast receiver clock - 125 MHz fclk_tx : in std_logic; -- fast transmitter clock - 125 MHz dv_er : in std_logic_vector(1 downto 0); -- data_valid and error signals data_rx : in std_logic_vector(15 downto 0); data_tx : out std_logic_vector(15 downto 0); tx_en : out std_logic; -- I2C interface to SFP module sda : inout std_logic; scl : out std_logic; -- static signals to SFP module present : in std_logic; tx_fault: in std_logic; los : in std_logic; -- -- interface to the board -- test signals out_tx_ck:out std_logic; out_tx_en:out std_logic; out_tx_dt:out std_logic; out_dv_er:out std_logic_vector(1 downto 0); Led : out std_logic_vector(7 downto 0); Swt : in std_logic_vector(7 downto 0); pbut : in std_logic_vector(3 downto 0) ); end top; architecture a of top is COMPONENT DCM4RX PORT( CLKIN_IN : IN std_logic; RST_IN : IN std_logic; CLKIN_IBUFG_OUT : OUT std_logic; CLK0_OUT : OUT std_logic; LOCKED_OUT : OUT std_logic ); END COMPONENT; component epp2usr is Port ( mclk : in std_logic; mrst : in std_logic; -- interface to the cypress USB chip pdb : inout std_logic_vector(7 downto 0); astb : in std_logic; dstb : in std_logic; pwr : in std_logic; pwait : out std_logic; -- interface to the user logic din : in std_logic_vector(7 downto 0); dout : out std_logic_vector(7 downto 0); addr : out std_logic_vector(7 downto 0); we : out std_logic; rd_fin : out std_logic ); end component; component control is port ( clk : in std_logic; we : in std_logic; rd_fin : in std_logic; rd_wfin : out std_logic; addr : in std_logic_vector( 7 downto 0); din : in std_logic_vector( 7 downto 0); dout : out std_logic_vector( 7 downto 0); raddr : out std_logic_vector(15 downto 0); rdata : in std_logic_vector(15 downto 0); led : out std_logic_vector( 7 downto 0); pbut : in std_logic_vector( 3 downto 0); dipsw : in std_logic_vector( 7 downto 0); go_rx : out std_logic; d1e1_cnt : in std_logic_vector(15 downto 0); d1e0_cnt : in std_logic_vector(15 downto 0); d0e1_cnt : in std_logic_vector(15 downto 0) ); end component; component sc_fifo generic (Na : Integer := 14; Nd : Integer := 16); port( din : in std_logic_vector(Nd-1 downto 0); wrreq : in std_logic; rdreq : in std_logic; clk : in std_logic; sclr : in std_logic; dout : out std_logic_vector(Nd-1 downto 0); full : out std_logic; empty : out std_logic ); end component; component RED -- Rising Edge Detector port( clk:in std_logic; -- system clock X_IN:in std_logic; -- monitored signal X_OUT:out std_logic -- output pulse ); end component; signal d1e1_cnt : std_logic_vector(15 downto 0); signal d1e0_cnt : std_logic_vector(15 downto 0); signal d0e1_cnt : std_logic_vector(15 downto 0); signal raddr : std_logic_vector(15 downto 0); signal rdata : std_logic_vector(15 downto 0); signal dout : std_logic_vector( 7 downto 0); signal din : std_logic_vector( 7 downto 0); signal addr : std_logic_vector( 7 downto 0); signal fempty : std_logic; signal fwr : std_logic; signal fwr_tst : std_logic_vector( 25 downto 0); signal frd : std_logic; signal frd_tst : std_logic_vector( 25 downto 0); signal ffull : std_logic; signal we : std_logic; signal rd_fin : std_logic; signal rd_wfin : std_logic; signal rd_end : std_logic; signal go_rx : std_logic; signal go : std_logic; signal data_rx_top1 : std_logic_vector(15 downto 0); signal dv_er_top1 : std_logic_vector(1 downto 0); signal data_rx_top : std_logic_vector(15 downto 0); signal dv_er_top : std_logic_vector(1 downto 0); signal fclk_rx_top : std_logic; signal fclk : std_logic; signal porst : std_logic_vector( 3 downto 0); signal norm : std_logic_vector( 25 downto 0); begin porst<= pbut; Inst_DCM4RX: DCM4RX PORT MAP( CLKIN_IN => fclk_rx, RST_IN => '0', CLKIN_IBUFG_OUT => open, CLK0_OUT => fclk, LOCKED_OUT =>open ); fclk_rx_top<=fclk; process(fclk_rx_top) begin if fclk_rx_top'event and fclk_rx_top='1' then data_rx_top<=data_rx; dv_er_top<=dv_er; end if; end process; -- process(fclk_rx_top) -- begin -- if fclk_rx_top'event and fclk_rx_top='1' then -- data_rx_top<=data_rx_top1; -- dv_er_top<=dv_er_top1; -- end if; -- end process; usb: epp2usr Port map( mclk => mclk, mrst => porst(0), -- interface to the cypress USB chip pdb => pdb, astb => astb, dstb => dstb, pwr => pwr, pwait => pwait, -- interface to the user logic din => din, dout => dout, addr => addr, we => we, rd_fin => rd_fin ); cnt: control port map( clk => mclk, we => we, rd_fin => rd_fin, rd_wfin => rd_wfin, addr => addr, din => dout, dout => din, raddr => raddr, rdata => rdata, led => open,--led, pbut => pbut, dipsw => Swt, go_rx => go, d1e1_cnt => d1e1_cnt, d1e0_cnt => d1e0_cnt, d0e1_cnt => d0e1_cnt ); go_rising_edge:RED port map( clk=>fclk_rx_top, X_IN=>go, X_OUT=>go_rx ); fifo: sc_fifo port map( din=>data_rx_top, wrreq=>fwr, rdreq=>frd, clk=>fclk_rx_top, sclr=>go_rx, dout=>rdata, full=>ffull, empty=>fempty ); -- fifo write control fwr<='1' when dv_er_top="10" and ffull='0' else '0'; process(fclk_rx_top) begin if fclk_rx_top'event and fclk_rx_top='1' then case dv_er_top is when "11" => d1e1_cnt <= d1e1_cnt+1; when "10" => d1e0_cnt <= d1e0_cnt+1; when "01" => d0e1_cnt <= d0e1_cnt+1; when others => null; end case; end if; end process; rd_fin_rising_edge:RED port map( clk=>fclk_rx_top, X_IN=>rd_wfin, X_OUT=>rd_end ); process(fclk_rx_top) -- fifo read control begin if fclk_rx_top'event and fclk_rx_top='1' then if fwr='0' and fempty='0' then if rd_end='1' then frd<='1'; else frd<='0'; end if; else frd<='0'; end if; end if; end process; data_tx<=(others=>'0'); tx_en<='0'; scl<='0'; out_tx_en<='0'; out_dv_er<=dv_er_top; process(fclk_rx_top) begin if fclk_rx_top'event and fclk_rx_top='1' then norm<=norm+1; end if; end process; -- process(frd,fwr) -- begin -- if frd='1' then Led(6)<='1'; Led(5)<='0'; end if; -- if fwr='1' then Led(5)<='1'; end if; -- end process; Led(0)<='0'; Led(1)<='0'; Led(2)<='0'; Led(3)<=fempty; Led(4)<=go; Led(5)<=frd; Led(6)<=fwr; Led(7)<=norm(25); end;