library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

library UNISIM; 
use UNISIM.Vcomponents.ALL;   

-- $Id$:
 
entity top is
port( 
	mclk    : in std_logic;
        -- interface to the cypress USB chip
	pdb     : inout std_logic_vector(7 downto 0);
	astb    : in    std_logic;
	dstb    : in    std_logic;
	pwr     : in    std_logic;
	pwait   : out   std_logic;
		-- HIROSE connector
		-- interface to TLK2501 and TX_CLOCK
	fclk_rx	: in	std_logic; -- fast receiver clock - 125 MHz
	fclk_tx	: in	std_logic; -- fast transmitter clock - 125 MHz
	dv_er	: in	std_logic_vector(1 downto 0); -- data_valid and error signals
	data_rx	: in	std_logic_vector(15 downto 0);
	data_tx	: out	std_logic_vector(15 downto 0);
	tx_en	: out	std_logic;
		-- I2C interface to SFP module
	sda		: inout	std_logic;
	scl		: out	std_logic;
		-- static signals to SFP module
	present	: in 	std_logic;
	tx_fault: in	std_logic;
	los		: in	std_logic;
		--
        -- interface to the board
	out_dv_er:out	std_logic_vector(1 downto 0);
	Led     : out   std_logic_vector(7 downto 0);
	Swt     : in    std_logic_vector(7 downto 0);
	pbut    : in    std_logic_vector(3 downto 0)
	);
end top;
 
architecture a of top is

component epp2usr is
port (
	mclk    : in std_logic;
	mrst	: in std_logic;
        -- interface to the cypress USB chip
	pdb     : inout std_logic_vector(7 downto 0);
	astb    : in std_logic;
	dstb    : in std_logic;
	pwr     : in std_logic;
	pwait   : out std_logic;
        -- interface to the user logic
	din     : in  std_logic_vector(7 downto 0);
	dout    : out std_logic_vector(7 downto 0);
	addr    : out std_logic_vector(7 downto 0);
	we      : out std_logic;
	rd_fin  : out std_logic
	);
end component;

component control is
port (
    clk     : in  std_logic;
    we      : in  std_logic;
    rd_fin  : in  std_logic;
    rd_wfin : out std_logic;
    addr    : in  std_logic_vector( 7 downto 0);
    din     : in  std_logic_vector( 7 downto 0);
    dout    : out std_logic_vector( 7 downto 0);
--    raddr   : out std_logic_vector(15 downto 0);
    rdata   : in  std_logic_vector(15 downto 0);
    led     : out std_logic_vector( 7 downto 0);
    pbut    : in  std_logic_vector( 3 downto 0);
    dipsw   : in  std_logic_vector( 7 downto 0);
	go_rx	: out std_logic;
    d1e1_cnt  : in  std_logic_vector(15 downto 0);
    d1e0_cnt  : in  std_logic_vector(15 downto 0);
    d0e1_cnt  : in  std_logic_vector(15 downto 0)
    );
end component;

component receiver -- 
port(
	po_rst	: in	std_logic;
		-- interface to receiver part of TLK2501 
	clk_rx	: in	std_logic; -- fast receiver clock - 125 MHz
	clk_out	: out 	std_logic;
	dv_er	: in	std_logic_vector(1 downto 0); -- data_valid and error signals
	data_rx	: in	std_logic_vector(15 downto 0);		
	Leds: out	std_logic_vector(4 downto 0);
		
		-- interface to control entity
	go2rec	: in	std_logic;
	wrd_fin	: in	std_logic;
	st_data	: out	std_logic_vector(15 downto 0);
	d1e1_num: out	std_logic_vector(15 downto 0);
	d1e0_num: out	std_logic_vector(15 downto 0);
	d0e1_num: out	std_logic_vector(15 downto 0)
	);
end component;

signal d1e1_cnt		: std_logic_vector(15 downto 0);
signal d1e0_cnt		: std_logic_vector(15 downto 0);
signal d0e1_cnt		: std_logic_vector(15 downto 0);
--signal raddr    : std_logic_vector(15 downto 0);
signal rdata		: std_logic_vector(15 downto 0);
signal dout			: std_logic_vector( 7 downto 0);
signal din			: std_logic_vector( 7 downto 0);
signal addr			: std_logic_vector( 7 downto 0);
signal norm			: std_logic_vector(25 downto 0); -- counter for testing of the receiver clock

signal we			: std_logic; 
signal rd_fin		: std_logic; -- read finished  by EPP
signal rd_wfin		: std_logic; -- read word from fifo finished
signal porst		: std_logic; -- power_on_reset - button 0 - resets the DCM
signal go			: std_logic; -- 
signal fclk_rx_top	: std_logic; -- receiver clock 

begin

porst<= pbut(0);

usb: epp2usr
port map(
	mclk    => mclk,
	mrst	=> porst,
        -- interface to the cypress USB chip
	pdb     => pdb,
	astb    => astb,
	dstb    => dstb,
	pwr     => pwr,
	pwait   => pwait,
        -- interface to the user logic
	din     => din,
	dout    => dout,
	addr    => addr,
	we      => we,
	rd_fin  => rd_fin
	);

cnt: control
port map(
    clk     => mclk,
    we      => we,
    rd_fin  => rd_fin,
	rd_wfin	=> rd_wfin,
    addr    => addr,
    din     => dout,
    dout    => din,
 --   raddr   => open,--raddr,
    rdata   => rdata,
    led     => open,--led,
    pbut    => pbut,
    dipsw   => Swt,
	go_rx	=> go,
    d1e1_cnt=> d1e1_cnt,
    d1e0_cnt=> d1e0_cnt,
    d0e1_cnt=> d0e1_cnt
	);


inst:receiver
port map(
	po_rst	=> porst,
	clk_rx	=> fclk_rx,
	clk_out	=> fclk_rx_top,
	dv_er	=> dv_er,
	data_rx	=> data_rx,
	Leds	=> Led(6 downto 2),
	go2rec	=> go,
	wrd_fin	=> rd_wfin,
	st_data	=> rdata,
	d1e1_num=> d1e1_cnt,
	d1e0_num=> d1e0_cnt,
	d0e1_num=> d0e1_cnt
	);

out_dv_er<=dv_er; -- dv and er signals on output to monitor

tx_en<='0'; -- transmitting is not implemented
data_tx<=(others=>'0');

scl<='0'; -- sfp interface not implemented. outputs are fixed
sda<='Z';

process(fclk_rx_top) -- receiver clock test
begin
if fclk_rx_top'event and fclk_rx_top='1' then
	norm<=norm+1;
end if;
end process;

Led(7)<=norm(25);

Led(0)<='0'; -- unused leds
Led(1)<='0';

end;