library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

library UNISIM; 
use UNISIM.Vcomponents.ALL;   

entity receiver is
    port (
		po_rst	: in	std_logic;
		-- interface to receiver part of TLK2501 
		clk_rx	: in	std_logic; -- fast receiver clock - 125 MHz
		clk_out	: out 	std_logic;
		dv_er	: in	std_logic_vector(1 downto 0); -- data_valid  - MSB and error  - LSB signals
		data_rx	: in	std_logic_vector(15 downto 0); -- received data
		
		Leds: out	std_logic_vector(4 downto 0);
		
		-- interface to control entity
		go2rec	: in	std_logic; -- rising edge resets the fifo
		wrd_fin	: in	std_logic; -- word read finish
		st_data	: out	std_logic_vector(15 downto 0); -- output of the fifo
		d1e1_num: out	std_logic_vector(15 downto 0); 
		d1e0_num: out	std_logic_vector(15 downto 0);
		d0e1_num: out	std_logic_vector(15 downto 0)
		);
end entity;

architecture a of receiver is

COMPONENT DCM4RX
   port ( CLKIN_IN        : in    std_logic; 
          RST_IN          : in    std_logic;  
          CLKIN_IBUFG_OUT : out   std_logic; 
          CLK0_OUT        : out   std_logic; 
          LOCKED_OUT      : out   std_logic);
END COMPONENT;
	
component sc_fifo
generic (Na : Integer := 14; Nd : Integer := 16);
port(
    din     : in std_logic_vector(Nd-1 downto 0);
    wrreq   : in std_logic;
    rdreq   : in std_logic;
    clk     : in std_logic;
    sclr    : in std_logic;
    dout    : out std_logic_vector(Nd-1 downto 0);
    full    : out std_logic;
    empty   : out std_logic
	);
end component;

component RED  -- Rising Edge Detector
port(
	clk		:in		std_logic; -- system clock
	X_IN	:in		std_logic; -- monitored signal
	X_OUT	:out	std_logic -- output pulse
	);
end component;

signal d1e1_cnt : std_logic_vector(15 downto 0);
signal d1e0_cnt : std_logic_vector(15 downto 0);
signal d0e1_cnt : std_logic_vector(15 downto 0);
signal fempty   : std_logic;
signal fwr	    : std_logic;
signal frd	    : std_logic;
signal ffull    : std_logic; 
signal rd_end   : std_logic; 
signal rst	    : std_logic; 

signal data_rx_reg : std_logic_vector(15 downto 0);
signal dv_er_reg : std_logic_vector(1 downto 0);
signal fclk : std_logic;

begin

Inst_DCM4RX: DCM4RX 
PORT MAP(
	CLKIN_IN => clk_rx,
	RST_IN => po_rst,
--	CLKIN_IBUFG_OUT =>open,
	CLK0_OUT => fclk,
	LOCKED_OUT =>open 
);
clk_out<=fclk; -- improved  received clock from TLK2501

process(fclk) -- registered input data
begin
if fclk'event and fclk='1' then
	data_rx_reg<=data_rx;
	dv_er_reg<=dv_er;
end if;
end process;

rst<=go2rec;

fifo: sc_fifo 
port map(
    din=>data_rx_reg,
    wrreq=>fwr,
    rdreq=>frd,
    clk=>fclk,
    sclr=>rst,
    dout=>st_data,
    full=>ffull,
    empty=>fempty
);

-- fifo write control
fwr<='1' when dv_er_reg="10" and ffull='0' else '0';

process(fclk) -- counters control
begin
if fclk'event and fclk='1' then
	case dv_er_reg is
	when "11" 	=> d1e1_cnt	<= d1e1_cnt+1;
	when "10" 	=> d1e0_cnt <= d1e0_cnt+1;
	when "01" 	=> d0e1_cnt <= d0e1_cnt+1;
	when others => null;
	end case;
end if;
end process;

d1e1_num<=d1e1_cnt;
d1e0_num<=d1e0_cnt;
d0e1_num<=d0e1_cnt;

wrd_fin_rising_edge:RED
port map(
clk=>fclk,
X_IN=>wrd_fin,
X_OUT=>rd_end
);

process(fclk) -- fifo read control
begin
if fclk'event and fclk='1' then
	if fwr='0' and fempty='0' then -- read operation not allowed concurrently with  writing and when the fifo is empty
		if rd_end='1' then
			frd<='1'; 
		else
			frd<='0';
		end if;
	else
		frd<='0';
	end if;
end if;
end process;

Leds(0)<=fempty; -- fifo empty indicator
Leds(1)<=rst;
Leds(2)<=frd;
Leds(3)<=fwr;
Leds(4)<=ffull;

end architecture;