library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- $Id$:

entity control is
port (
    clk     : in  std_logic;
    we      : in  std_logic;
    rd_fin  : in  std_logic;
    rd_wfin : out std_logic;
    addr    : in  std_logic_vector( 7 downto 0);
    din     : in  std_logic_vector( 7 downto 0);
    dout    : out std_logic_vector( 7 downto 0);
--    raddr   : out std_logic_vector(15 downto 0);
    rdata   : in  std_logic_vector(15 downto 0);
    led     : out std_logic_vector( 7 downto 0);
    pbut    : in  std_logic_vector( 3 downto 0);
    dipsw   : in  std_logic_vector( 7 downto 0);
	go_rx	: out std_logic;
    d1e1_cnt  : in  std_logic_vector(15 downto 0);
    d1e0_cnt  : in  std_logic_vector(15 downto 0);
    d0e1_cnt  : in  std_logic_vector(15 downto 0)
    );
end control;

architecture a of control is

subtype data_type is std_logic_vector(7 downto 0);
type data_array is array(0 to 7) of data_type;

-- Registers
signal regData          : data_array;
signal  regLed          : data_type;
signal  regCnf          : data_type;
signal  regExt          : data_type;
signal  regOrx          : data_type;

signal raddr_cnt : std_logic_vector(15 downto 0);-- :=(others=>'0');

begin
    regData(0) <= raddr_cnt( 7 downto 0);
    regData(1) <= raddr_cnt(15 downto 8);

    regData(2) <= d1e0_cnt( 7 downto 0);
    regData(3) <= d1e0_cnt(15 downto 8);

    regData(4) <= d0e1_cnt( 7 downto 0);
    regData(5) <= d0e1_cnt(15 downto 8);

    regData(6) <= d1e1_cnt( 7 downto 0);
    regData(7) <= d1e1_cnt(15 downto 8);

 --   raddr <= raddr_cnt(16 downto 1);
    process(regData, addr, regLed, regExt, regOrx, regCnf, pbut, dipsw, rdata, raddr_cnt)
    begin
        dout <= (others => '0');
        case addr is
        when  x"00" => dout <= regData(0);
        when  x"01" => dout <= regData(1);
        when  x"02" => dout <= regData(2);
        when  x"03" => dout <= regData(3);
        when  x"04" => dout <= regData(4);
        when  x"05" => dout <= regData(5);
        when  x"06" => dout <= regData(6);
        when  x"07" => dout <= regData(7);
        when  x"08" => dout <= regLed;
		when  x"F8" => dout <= regExt;
		when  x"F7" => dout <= regOrx;		
        when  x"09" => dout <= regCnf;
        when  x"0A" => dout(pbut'range) <= pbut;
        when  x"0B" => dout(dipsw'range) <= dipsw;
        when  x"0D" | x"0F" | x"0C" | x"0E" =>
                if raddr_cnt(0) = '0' then 
					dout <= rdata(15 downto 8); 
                else 
					dout <= rdata( 7 downto 0); 
				end if;
        when others => NULL;
        end case;
    end process;
	
led <= regLed;
go_rx<=regExt(0);	
rd_wfin<=not raddr_cnt(0);

    process(clk)
    begin
        if rising_edge(clk) then
            if we='1' then
                case addr is
                when x"08" => regLed <= din;
                when x"F8" => regExt <= din;
				when x"F7" => regOrx <= din;
                when x"09" => regCnf <= din;
                when x"00" | x"01"| x"0C" => raddr_cnt <= (others => '0');
                when others => NULL;
                end case;
            elsif rd_fin = '1' and (addr = x"00" or addr = x"01" or addr=x"0C") then
                raddr_cnt <= raddr_cnt + 1;
            end if;
        end if;
    end process;

end;