-- Rising Edge Detector unit

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity RED is -- Rising Edge Formative Entity
	port(
	clk:in		std_logic; -- system clock
	X_IN:in		std_logic; -- monitored signal
	X_OUT:out	std_logic -- output pulse
	);
end RED;
										 
architecture RTL of RED is 	

signal edge:std_logic_vector(1 downto 0) :="00";													

begin

process(clk)
begin
if clk'event and clk='1' then
	edge<=edge(0) & X_IN;
end if;
end process;
X_OUT<=edge(0) and not edge(1);

end RTL;