-------------------------------------------------------------------------------- -- Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. -------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version : 10.1.03 -- \ \ Application : xaw2vhdl -- / / Filename : DCM4RX.vhd -- /___/ /\ Timestamp : 10/22/2009 15:44:01 -- \ \ / \ -- \___\/\___\ -- --Command: xaw2vhdl-intstyle C:/Electronics/ALICE_TRD/nexys_sfp/xilinx/DCM4RX.xaw -st DCM4RX.vhd --Design Name: DCM4RX --Device: xc3s500e-4fg320 -- -- Module DCM4RX -- Generated by Xilinx Architecture Wizard -- Written for synthesis tool: XST library ieee; use ieee.std_logic_1164.ALL; use ieee.numeric_std.ALL; library UNISIM; use UNISIM.Vcomponents.ALL; entity DCM4RX is port ( CLKIN_IN : in std_logic; RST_IN : in std_logic; CLKIN_IBUFG_OUT : out std_logic; CLK0_OUT : out std_logic; LOCKED_OUT : out std_logic); end DCM4RX; architecture BEHAVIORAL of DCM4RX is signal CLKFB_IN : std_logic; signal CLKIN_IBUFG : std_logic; signal CLK0_BUF : std_logic; signal GND_BIT : std_logic; begin GND_BIT <= '0'; CLKIN_IBUFG_OUT <= CLKIN_IBUFG; CLK0_OUT <= CLKFB_IN; CLKIN_IBUFG_INST : IBUFG port map (I=>CLKIN_IN, O=>CLKIN_IBUFG); CLK0_BUFG_INST : BUFG port map (I=>CLK0_BUF, O=>CLKFB_IN); DCM_SP_INST : DCM_SP generic map( CLK_FEEDBACK => "1X", CLKDV_DIVIDE => 2.0, CLKFX_DIVIDE => 1, CLKFX_MULTIPLY => 2, CLKIN_DIVIDE_BY_2 => FALSE, CLKIN_PERIOD => 8.000, CLKOUT_PHASE_SHIFT => "FIXED", DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW", DUTY_CYCLE_CORRECTION => TRUE, FACTORY_JF => x"C080", PHASE_SHIFT => 0, STARTUP_WAIT => FALSE) port map (CLKFB=>CLKFB_IN, CLKIN=>CLKIN_IBUFG, DSSEN=>GND_BIT, PSCLK=>GND_BIT, PSEN=>GND_BIT, PSINCDEC=>GND_BIT, RST=>RST_IN, CLKDV=>open, CLKFX=>open, CLKFX180=>open, CLK0=>CLK0_BUF, CLK2X=>open, CLK2X180=>open, CLK90=>open, CLK180=>open, CLK270=>open, LOCKED=>LOCKED_OUT, PSDONE=>open, STATUS=>open); end BEHAVIORAL;