/* * armboot - Startup Code for EPXA (Excalibur) devices * * Copyright (C) 1998 Dan Malek * Copyright (C) 1999 Magnus Damm * Copyright (C) 2000 Wolfgang Denk * Copyright (c) 2001 Alex Züpke * Copyright (C) 2002 Altera Corporation, San Jose, California, USA. * * See file CREDITS for list of people who contributed to this * project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ #include "config.h" #include "version.h" #define INT_CTRL00_TYPE #define WATCHDOG00_TYPE #include "epxa/excalibur.h" #include "epxa/int_ctrl00.h" #include "epxa/watchdog00.h" /* ************************************************************************* * * Jump vector table as in table 3.1 in [1] * ************************************************************************* */ .globl _start .globl ___altera_user_start .section .init _start: b reset ldr pc, _undefined_instruction ldr pc, _software_interrupt ldr pc, _prefetch_abort ldr pc, _data_abort ldr pc, _not_used ldr pc, _irq ldr pc, _fiq _undefined_instruction: .word undefined_instruction _software_interrupt: .word software_interrupt _prefetch_abort: .word prefetch_abort _data_abort: .word data_abort _not_used: .word not_used _irq: .word irq _fiq: .word fiq .balignl 16,0xdeadbeef /* ************************************************************************* * * Startup Code (reset vector) * * do important init only if we don't start from memory! * relocate armboot to ram * setup stack * jump to second stage * ************************************************************************* */ /* * the actual reset code */ reset: /* * we do sys-critical inits only at reboot, * not when booting from ram! */ #ifdef CONFIG_INIT_CRITICAL b ___altera_entry #else b ___altera_user_start #endif /* Force the inclusion of the boot data in the image */ .word ___altera_user_entry .text _TEXT_BASE: .word TEXT_BASE .globl _armboot_start _armboot_start: .word _start /* * Note: armboot_end is defined by the (board-dependent) linker script */ .globl _armboot_end _armboot_end: .word armboot_end /* * _armboot_real_end is the first usable RAM address behind armboot * and the various stacks */ .globl _armboot_real_end _armboot_real_end: .word 0x0badc0de #ifdef CONFIG_USE_IRQ /* IRQ stack memory (calculated at run-time) */ .globl IRQ_STACK_START IRQ_STACK_START: .word 0x0badc0de /* IRQ stack memory (calculated at run-time) */ .globl FIQ_STACK_START FIQ_STACK_START: .word 0x0badc0de #endif /* * ___altera_user_start is the address in flash of the first line of code * to be executed after the Altera boot code has configured the device. * This is the line pointed to by user_start. Since this code is linked * to start at zero, we need to correct for the offset of the flash within * the memory map. */ .set ___altera_user_start, user_start + EXC_EBI_BLOCK0_BASE user_start: /* * set the cpu to SVC32 mode */ mrs r0,cpsr bic r0,r0,#0x1f orr r0,r0,#0x13 msr cpsr,r0 /* * mask all IRQs */ ldr r0, =INT_MC(EXC_INT_CTRL00_BASE) mvn r1, #0 mov r1, r1, LSR #16 str r1, [r0] /* * disable MMU stuff and enable I-cache */ mrc p15,0,r0,c1,c0 bic r0, r0, #0x00002000 @ clear bit 13 (X) bic r0, r0, #0x0000000f @ clear bits 3-0 (WCAM) orr r0, r0, #0x00001000 @ set bit 12 (I) Icache orr r0, r0, #0x00000002 @ set bit 2 (A) Align mcr p15,0,r0,c1,c0 /* * flush v4 I/D caches */ mov r0, #0 mcr p15, 0, r0, c7, c7, 0 // flush v3/v4 cache mcr p15, 0, r0, c8, c7, 0 // flush v4 TLB relocate: /* * relocate armboot to RAM */ ldr r0, _armboot_start /* r0 <- current position of code */ ldr r2, _armboot_end ldr r1, _TEXT_BASE /* r1 <- destination address */ /* correct for the current execution address */ ldr r3, =EXC_EBI_BLOCK0_BASE add r0, r0, r3 add r2, r2, r3 /* * r0 = source address * r1 = target address * r2 = source end address */ copy_loop: ldmia r0!, {r3-r10} stmia r1!, {r3-r10} cmp r0, r2 ble copy_loop /* set up the stack */ ldr r0, _armboot_end add r0, r0, #CONFIG_STACKSIZE sub sp, r0, #12 /* leave 3 words for abort-stack */ ldr pc, _start_armboot _start_armboot: .word start_armboot /* ************************************************************************* * * Interrupt handling * ************************************************************************* */ @ @ IRQ stack frame. @ #define S_FRAME_SIZE 72 #define S_OLD_R0 68 #define S_PSR 64 #define S_PC 60 #define S_LR 56 #define S_SP 52 #define S_IP 48 #define S_FP 44 #define S_R10 40 #define S_R9 36 #define S_R8 32 #define S_R7 28 #define S_R6 24 #define S_R5 20 #define S_R4 16 #define S_R3 12 #define S_R2 8 #define S_R1 4 #define S_R0 0 #define MODE_SVC 0x13 #define I_BIT 0x80 /* * use bad_save_user_regs for abort/prefetch/undef/swi ... * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling */ .macro bad_save_user_regs sub sp, sp, #S_FRAME_SIZE stmia sp, {r0 - r12} @ Calling r0-r12 add r8, sp, #S_PC ldr r2, _armboot_end add r2, r2, #CONFIG_STACKSIZE sub r2, r2, #8 ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC add r5, sp, #S_SP mov r1, lr stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r mov r0, sp .endm .macro irq_save_user_regs sub sp, sp, #S_FRAME_SIZE stmia sp, {r0 - r12} @ Calling r0-r12 add r8, sp, #S_PC stmdb r8, {sp, lr}^ @ Calling SP, LR str lr, [r8, #0] @ Save calling PC mrs r6, spsr str r6, [r8, #4] @ Save CPSR str r0, [r8, #8] @ Save OLD_R0 mov r0, sp .endm .macro irq_restore_user_regs ldmia sp, {r0 - lr}^ @ Calling r0 - lr mov r0, r0 ldr lr, [sp, #S_PC] @ Get PC add sp, sp, #S_FRAME_SIZE subs pc, lr, #4 @ return & move spsr_svc into cpsr .endm .macro get_bad_stack ldr r13, _armboot_end @ setup our mode stack add r13, r13, #CONFIG_STACKSIZE @ resides at top of normal stack sub r13, r13, #8 str lr, [r13] @ save caller lr / spsr mrs lr, spsr str lr, [r13, #4] mov r13, #MODE_SVC @ prepare SVC-Mode msr spsr_c, r13 mov lr, pc movs pc, lr .endm .macro get_irq_stack @ setup IRQ stack ldr sp, IRQ_STACK_START .endm .macro get_fiq_stack @ setup FIQ stack ldr sp, FIQ_STACK_START .endm /* * exception handlers */ .align 5 undefined_instruction: get_bad_stack bad_save_user_regs bl do_undefined_instruction .align 5 software_interrupt: get_bad_stack bad_save_user_regs bl do_software_interrupt .align 5 prefetch_abort: get_bad_stack bad_save_user_regs bl do_prefetch_abort .align 5 data_abort: get_bad_stack bad_save_user_regs bl do_data_abort .align 5 not_used: get_bad_stack bad_save_user_regs bl do_not_used #ifdef CONFIG_USE_IRQ .align 5 irq: get_irq_stack irq_save_user_regs bl do_irq irq_restore_user_regs .align 5 fiq: get_fiq_stack /* someone ought to write a more effiction fiq_save_user_regs */ irq_save_user_regs bl do_fiq irq_restore_user_regs #else .align 5 irq: get_bad_stack bad_save_user_regs bl do_irq .align 5 fiq: get_bad_stack bad_save_user_regs bl do_fiq #endif .align 5 .globl reset_cpu reset_cpu: ldr r0,=WDOG_RELOAD(EXC_WATCHDOG00_BASE) mov r1,#0x10 str r1,[r0] /* wait for reset */ 1: b 1b