// megafunction wizard: %ARM-Based Excalibur%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ARM-Based Excalibur
// PROJECT: excalibur
// ============================================================
// File Name: h:\data\excalibur\excalibur.v
// Megafunction Name(s): ARM-Based Excalibur
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// 
// Copyright (C) 1991-2002 Altera Corporation
// Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
// support information,  device programming or simulation file,  and any other
// associated  documentation or information  provided by  Altera  or a partner
// under  Altera's   Megafunction   Partnership   Program  may  be  used  only
// to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
// other  use  of such  megafunction  design,  netlist,  support  information,
// device programming or simulation file,  or any other  related documentation
// or information  is prohibited  for  any  other purpose,  including, but not
// limited to  modification,  reverse engineering,  de-compiling, or use  with
// any other  silicon devices,  unless such use is  explicitly  licensed under
// a separate agreement with  Altera  or a megafunction partner.  Title to the
// intellectual property,  including patents,  copyrights,  trademarks,  trade
// secrets,  or maskworks,  embodied in any such megafunction design, netlist,
// support  information,  device programming or simulation file,  or any other
// related documentation or information provided by  Altera  or a megafunction
// partner, remains with Altera, the megafunction partner, or their respective
// licensors. No other licenses, including any licenses needed under any third
// party's intellectual property, are provided herein.
// 

module excalibur
(
	clk_ref,
	npor,
	nreset,
	uartrxd,
	uartdsrn,
	uartctsn,
	uartrin,
	uartdcdn,
	uarttxd,
	uartrtsn,
	uartdtrn,
	intextpin,
	ebiack,
	ebidq,
	ebiclk,
	ebiwen,
	ebioen,
	ebiaddr,
	ebibe,
	ebicsn,
	sdramdq,
	sdramdqs,
	sdramclk,
	sdramclkn,
	sdramclke,
	sdramwen,
	sdramcasn,
	sdramrasn,
	sdramaddr,
	sdramcsn,
	sdramdqm,
	slavehclk,
	slavehwrite,
	slavehreadyi,
	slavehselreg,
	slavehsel,
	slavehmastlock,
	slavehaddr,
	slavehtrans,
	slavehsize,
	slavehburst,
	slavehwdata,
	slavehreadyo,
	slavebuserrint,
	slavehresp,
	slavehrdata,
	masterhclk,
	masterhready,
	masterhgrant,
	masterhrdata,
	masterhresp,
	masterhwrite,
	masterhlock,
	masterhbusreq,
	masterhaddr,
	masterhburst,
	masterhsize,
	masterhtrans,
	masterhwdata,
	intuart,
	inttimer0,
	inttimer1,
	intcommtx,
	intcommrx,
	debugrq,
	debugext0,
	debugext1,
	debugextin,
	debugack,
	debugrng0,
	debugrng1,
	debugextout
);

input	clk_ref;
input	npor;
inout	nreset;
input	uartrxd;
input	uartdsrn;
input	uartctsn;
inout	uartrin;
inout	uartdcdn;
output	uarttxd;
output	uartrtsn;
output	uartdtrn;
input	intextpin;
input	ebiack;
inout	[15:0] ebidq;
output	ebiclk;
output	ebiwen;
output	ebioen;
output	[24:0] ebiaddr;
output	[1:0] ebibe;
output	[3:0] ebicsn;
inout	[15:0] sdramdq;
inout	[1:0] sdramdqs;
output	sdramclk;
output	sdramclkn;
output	sdramclke;
output	sdramwen;
output	sdramcasn;
output	sdramrasn;
output	[14:0] sdramaddr;
output	[1:0] sdramcsn;
output	[1:0] sdramdqm;
input	slavehclk;
input	slavehwrite;
input	slavehreadyi;
input	slavehselreg;
input	slavehsel;
input	slavehmastlock;
input	[31:0] slavehaddr;
input	[1:0] slavehtrans;
input	[1:0] slavehsize;
input	[2:0] slavehburst;
input	[31:0] slavehwdata;
output	slavehreadyo;
output	slavebuserrint;
output	[1:0] slavehresp;
output	[31:0] slavehrdata;
input	masterhclk;
input	masterhready;
input	masterhgrant;
input	[31:0] masterhrdata;
input	[1:0] masterhresp;
output	masterhwrite;
output	masterhlock;
output	masterhbusreq;
output	[31:0] masterhaddr;
output	[2:0] masterhburst;
output	[1:0] masterhsize;
output	[1:0] masterhtrans;
output	[31:0] masterhwdata;
output	intuart;
output	inttimer0;
output	inttimer1;
output	intcommtx;
output	intcommrx;
input	debugrq;
input	debugext0;
input	debugext1;
input	[3:0] debugextin;
output	debugack;
output	debugrng0;
output	debugrng1;
output	[3:0] debugextout;

wire	proc_ntrst;
wire	proc_tck;
wire	proc_tdi;
wire	proc_tms;
wire	proc_tdo;
wire	[5:0] intpld;

assign proc_ntrst = 1'b1;
assign proc_tck = 1'b0;
assign proc_tdi = 1'b0;
assign proc_tms = 1'b0;
assign intpld = 6'b0;

alt_exc_stripe lpm_instance
(
	.clk_ref(clk_ref),
	.npor(npor),
	.nreset(nreset),
	.uartrxd(uartrxd),
	.uartdsrn(uartdsrn),
	.uartctsn(uartctsn),
	.uartrin(uartrin),
	.uartdcdn(uartdcdn),
	.uarttxd(uarttxd),
	.uartrtsn(uartrtsn),
	.uartdtrn(uartdtrn),
	.intextpin(intextpin),
	.ebiack(ebiack),
	.ebidq(ebidq),
	.ebiclk(ebiclk),
	.ebiwen(ebiwen),
	.ebioen(ebioen),
	.ebiaddr(ebiaddr),
	.ebibe(ebibe),
	.ebicsn(ebicsn),
	.sdramdq(sdramdq),
	.sdramdqs(sdramdqs),
	.sdramclk(sdramclk),
	.sdramclkn(sdramclkn),
	.sdramclke(sdramclke),
	.sdramwen(sdramwen),
	.sdramcasn(sdramcasn),
	.sdramrasn(sdramrasn),
	.sdramaddr(sdramaddr),
	.sdramcsn(sdramcsn),
	.sdramdqm(sdramdqm),
	.slavehclk(slavehclk),
	.slavehwrite(slavehwrite),
	.slavehreadyi(slavehreadyi),
	.slavehselreg(slavehselreg),
	.slavehsel(slavehsel),
	.slavehmastlock(slavehmastlock),
	.slavehaddr(slavehaddr),
	.slavehtrans(slavehtrans),
	.slavehsize(slavehsize),
	.slavehburst(slavehburst),
	.slavehwdata(slavehwdata),
	.slavehreadyo(slavehreadyo),
	.slavebuserrint(slavebuserrint),
	.slavehresp(slavehresp),
	.slavehrdata(slavehrdata),
	.masterhclk(masterhclk),
	.masterhready(masterhready),
	.masterhgrant(masterhgrant),
	.masterhrdata(masterhrdata),
	.masterhresp(masterhresp),
	.masterhwrite(masterhwrite),
	.masterhlock(masterhlock),
	.masterhbusreq(masterhbusreq),
	.masterhaddr(masterhaddr),
	.masterhburst(masterhburst),
	.masterhsize(masterhsize),
	.masterhtrans(masterhtrans),
	.masterhwdata(masterhwdata),
	.intuart(intuart),
	.inttimer0(inttimer0),
	.inttimer1(inttimer1),
	.intcommtx(intcommtx),
	.intcommrx(intcommrx),
	.debugrq(debugrq),
	.debugext0(debugext0),
	.debugext1(debugext1),
	.debugextin(debugextin),
	.debugack(debugack),
	.debugrng0(debugrng0),
	.debugrng1(debugrng1),
	.debugextout(debugextout),
	.proc_ntrst(proc_ntrst),
	.proc_tck(proc_tck),
	.proc_tdi(proc_tdi),
	.proc_tms(proc_tms),
	.proc_tdo(proc_tdo),
	.intpld(intpld)
);
defparam
	lpm_instance.sdram_width = 16,
	lpm_instance.sdramdqm_width = 2,
	lpm_instance.processor = "ARM",
	lpm_instance.device_size = 100,
	lpm_instance.boot_from_flash = "TRUE",
	lpm_instance.debug_extensions = "TRUE",
	lpm_instance.ebi0_width = 16,
	lpm_instance.use_initialisation_files = "TRUE",
	lpm_instance.use_short_reset = "TRUE",
	lpm_instance.dp0_output_mode = "UNREG",
	lpm_instance.dp1_output_mode = "UNREG",
	lpm_instance.dp0_mode = "UNUSED",
	lpm_instance.dp1_mode = "UNUSED";

endmodule